JPH04235656A - Channel device control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel device control system in an electronic computer system.

0002

2. Description of the Related Art Conventionally, when transmitting and receiving data between an input/output device and a storage device, a transfer method has been adopted in which a DMA mechanism is provided to directly transfer data without using a CPU. As the functions of computer systems become more sophisticated, a plurality of DMA mechanisms are provided to speed up data transfer.

FIG. 6 shows a conventional DMA of a conventional electronic computer.
The relationship between a mechanism (hereinafter abbreviated as DMA) and a channel is shown. In the figure, 10 is a storage device for storing data; 33
and 34 are workstation adapters (hereinafter abbreviated as WSA) that control the workstation, 11 and 1
2 is a DMA that exchanges data with the storage device; 2 is a DMA
The DMA channel switching unit 20 that sets the data transfer path between the WSA and the WSA is an initial state setting program that is activated immediately after power is turned on and sets the initial state. In the figure, when the power is turned on, the combination of two DMAs and two WSAs:
Determined by the initial state setting program 20, WSA3
3 uses DMA11, WSA34 is set to use DMA12, and does not change thereafter.

[0004] Therefore, when a failure occurs in one DMA 11 and it becomes inoperable, the WSA 33 connected to that DMA 11 and the storage device 10 cannot exchange data.
The system goes down.

[0005]

[Problem to be solved by the invention] Conventionally, there are two types of DMA
There is a problem in that even if a failure occurs in either of them, data transfer between the WSA and the storage device becomes impossible and the system goes down.

In view of these points, the present invention detects a failure even if a failure occurs in either of the two DMAs, and connects another DMA to a W paired with the failed DMA.
The purpose is to provide a means to connect with the SA, transfer data, and continue business operations.

[0007]

[Means for Solving the Problems] The above problems are solved by a channel device control system configured as follows. FIG. 1 is a diagram showing the principle of the present invention.

[0008] In a channel device having a DMA channel switching section 2 that connects two DMA mechanisms 11, 12 and two input/output control devices 31, 32, if any one of the plurality of DMA mechanisms 11, 12 is in a failure state. a fixed fault state recognition section 4 that detects the fixed fault state recognition section 4; a DMA switching section 6 that switches inputs to the DMA mechanisms 11 and 12 according to a signal from the fixed fault state recognition section 4; Control devices 31, 32
By providing a DMA channel sharing unit 5 that selects a DMA mechanism, when a failure occurs in a DMA mechanism, the fixed failure state recognition unit 4 detects the failure, and the DMA switching unit 6 switches to a DMA mechanism that is not at fault; The configuration is such that the DMA channel sharing unit 5 selects the two input/output control devices 31 and 32 from the DMA mechanism to perform data transfer.

[0009]

[Operation] The fixed fault state recognition unit 4 detects a fault state in one of the two DMAs, and the DMA switching unit 6
Then, the DMA channel sharing unit 5 selects the two input/output control devices from another DMA and performs data transfer.

0010

Embodiment FIG. 2 is a block diagram of an embodiment of the present invention. In the figure, 4 is a fixed fault state recognition unit that detects a fixed DMA fault, 6 is a DMA switching unit that switches between two DMAs,
Reference numeral 5 denotes a DMA channel sharing unit for jointly using the DMA channel switching unit 2 between two WSAs. Other components having the same reference numerals as those in FIG. 3 are the same.

[0011] In the figure, the initial state setting program is composed of firmware, is started immediately after power is turned on, and is configured to control two DMs within the DMA channel switching unit 2.
The connection between A and the two WSAs is set so that the DMA 11 processes the data transfer of the WSA 33, and the DMA 12 processes the data transfer of the WSA 34. When the DMA 11 becomes a failure, it is detected by the fixed fault state recognition unit 4, and the DMA switching unit 6 switches the DMA 1 to
2, and the DMA channel switching section 2
and the DMA channel sharing unit 5 are connected. Therefore, the data transfer that was conventionally performed through the route of the storage device 10, DMA 11, DMA channel switching unit 2, and WSA 33 is now
A channel switching unit 2, DMA channel sharing unit 5
, WSA33.

FIG. 3(A) is a flowchart of the fixed failure state recognition unit 4 and DMA switching unit 6 configured by firmware. After executing the data transfer command in step 61, the result report is examined in step 62, in which
It is checked in step 63 whether there is a report of MA transfer failure. If no transfer failure is reported, the number of the DMA just used is checked in step 64, and the corresponding DMA is transferred in step 65.
Clear the MA error count record to zero and return to the normal route.

If a DMA transfer failure is reported, the number of the DMA in which the error has occurred is checked in step 66, the number of errors is incremented by 1 in step 67, and it is checked in step 68 whether the number of errors has occurred more than a specified number of times. . If it has occurred a predetermined number of times or more, it is checked in step 69 whether the DMA failure state flag is turned on, and if it is turned on, the process ends. Further, if the number of occurrences of errors is less than a predetermined number in step 68, the process is terminated. Also, step 6
If the failure state flag of the DMA is not turned on in step 9, the failure state flag is turned on in step 70, and the number of the normal DMA is recorded in step 71. Step 7
In step 2, the number of the normal DMA is checked, and if it is #1, DMA #1 is designated as WSA #1 in step 73, and if it is #2, DMA #2 is designated as WSA #0, and the process ends.

FIGS. 4 and 5 show D configured with firmware.
It is a flowchart of the MA channel sharing unit 5. The operation starts when the WSA is activated. D at step 77
Check whether the MA failure state flag is ON, and if it is OFF, return to the normal route. If ON, DM in step 76
Check whether A is in operation, and if it is in operation, proceed to step 80; if not, proceed to step 77 to check whether there is a wait for DMA operation to end; if there is, step 83
Proceed to. If not, proceed to step 78 and check whether DMA is used in the WSA operation. If it is used, turn on the DMA operation flag in step 79 and return to the normal route. If not, do nothing and return to the normal route. Return to

In step 80, the WSA operates to perform DMA
If it is to be used, the DM is sent in step 81 to wait for the other currently operating WSAs to complete their operations.
The A completion wait flag is turned ON, and in step 82, the operation of the WSA to be operated from now on is stopped and the process ends. Also, D
If MA is not used, the normal route is returned.

[0016] In step 83, the process waits for the end of the DMA, and when it is finished, the process proceeds to step 84, where the normal DMA number is checked, and if it is #1, the process proceeds to step 86, where the DMA of the WSA currently waiting for a free DMA is checked. DMA the terms of use
If it is #2, the process advances to step 87, and the DMA usage condition of the WSA currently waiting for a free DMA is set to DMA #2. Proceeding to step 88, the standby WSA is activated and operation is resumed.

The above describes the functions of the DMA channel sharing unit, which includes the DMA channel switching unit and the two WSAs 33 and 34.
Establish a communication channel with and enable data transfer. With this configuration, a recovery function for fixed DMA failures can be easily provided without increasing hardware.

[0018]

[Effects of the Invention] As is clear from the above description, the present invention has a remarkable industrial effect in that it is possible to continue business operations by providing a recovery function against a fixed DMA failure.

[Brief explanation of the drawing]

[Figure 1] Principle diagram of the present invention

[Figure 2] Configuration diagram of an embodiment of the present invention

[Figure 3] Flowchart of the embodiment of the present invention (Part 1)
)

[Figure 4] Flowchart of the embodiment of the present invention (Part 2)

[Figure 5] Flowchart of the embodiment of the present invention (part 3)

[Figure 6] Explanatory diagram of the relationship between the conventional DMA mechanism and channels

[Explanation of symbols]

2 DMA channel switching section 4 Fixed failure state recognition section 5 DMA channel sharing section 6 DMA switching section 10 Storage device
11, 12 DMA mechanism 20 Initial state setting program 31, 32 Input/output control device 33, 34 WSA

Claims (1)

[Claims] [Claim 1] A D that connects two DMA mechanisms (11, 12) and two input/output control devices (31, 32).
In a channel device having an MA channel switching unit (2), a fixed failure state recognition unit (4) detects a failure state of any one of the plurality of DMA mechanisms (11, 12).
and a DM that switches the input to the DMA mechanism (11, 12) based on the signal from the fixed fault state recognition unit (4).
A switching section (6) and the DMA channel switching section (2)
By providing a DMA channel sharing unit (5) that selects the two input/output control devices (31, 32) from the above, when a failure occurs in the DMA mechanism, the fixed failure status recognition unit (4) can detect the failure. The DMA switching unit (6) switches to a non-faulty DMA mechanism, and the DMA
A channel device control system characterized in that an A channel sharing unit (5) selects the two input/output control devices (31, 32) from the DMA mechanism and performs data transfer.