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JPH04233512A - Production of active matrix substrate - Google Patents

Production of active matrix substrate

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Publication number
JPH04233512A
JPH04233512A JP2408959A JP40895990A JPH04233512A JP H04233512 A JPH04233512 A JP H04233512A JP 2408959 A JP2408959 A JP 2408959A JP 40895990 A JP40895990 A JP 40895990A JP H04233512 A JPH04233512 A JP H04233512A
Authority
JP
Japan
Prior art keywords
active matrix
matrix substrate
protective film
channel protective
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2408959A
Other languages
Japanese (ja)
Other versions
JP2694912B2 (en
Inventor
Katsumasa Ikubo
井窪 克昌
Yasuhiro Mitani
康弘 三谷
Hirohisa Tanaka
田仲 広久
Yasunori Shimada
島田 康憲
Hiroshi Morimoto
弘 森本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP40895990A priority Critical patent/JP2694912B2/en
Priority to EP91312014A priority patent/EP0493113B1/en
Priority to DE69125260T priority patent/DE69125260T2/en
Priority to US07/813,385 priority patent/US5286659A/en
Priority to KR1019910025097A priority patent/KR950003939B1/en
Publication of JPH04233512A publication Critical patent/JPH04233512A/en
Priority to US08/154,116 priority patent/US5474941A/en
Application granted granted Critical
Publication of JP2694912B2 publication Critical patent/JP2694912B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To realize an active matrix substrate having good TFT characteristics by ion implantation method. CONSTITUTION:P<+> ions are implanted to the upper side of a substrate having a resist 11 remaining on a channel protective film 5. This prevents implantation of impurities in the channel protective film 5. Thereby, leaking of current between contact layers 6a, 6b and source electrode 7 and between contact layers and a drain electrode 8 is precented.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、液晶表示装置等に使用
されるアクティブマトリクス基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an active matrix substrate used in liquid crystal display devices and the like.

【0002】0002

【従来の技術】図3はこの種のアクティブマトリクス基
板の製造方法の一従来例を示しており、図3(a)に示
すように、ガラス基板1上にゲート電極2をまず形成し
、次いで、ゲート電極2上にゲート絶縁膜3を形成し、
その後、絶縁膜3上に半導体層4を形成する。次いで、
半導体層4のゲート電極2の上方に相当する部分にチャ
ネル保護膜5をパターン形成する。そして、チャネル保
護膜5の上方よりP+イオンを注入し、半導体層4の表
面側にコンタクト層6a及び6bを形成する。次いで、
フォトリソグラフィとエツチングによりコンタクト層6
a、6bの不要部分を取り除いて図3(b)に示すコン
タクト層6a、6bをパターン形成する。
2. Description of the Related Art FIG. 3 shows a conventional example of a method for manufacturing this type of active matrix substrate. As shown in FIG. 3(a), a gate electrode 2 is first formed on a glass substrate 1, and then , forming a gate insulating film 3 on the gate electrode 2;
After that, a semiconductor layer 4 is formed on the insulating film 3. Then,
A channel protective film 5 is patterned in a portion of the semiconductor layer 4 corresponding to the upper part of the gate electrode 2 . Then, P+ ions are implanted from above the channel protection film 5 to form contact layers 6a and 6b on the surface side of the semiconductor layer 4. Then,
Contact layer 6 is formed by photolithography and etching.
Contact layers 6a and 6b shown in FIG. 3B are patterned by removing unnecessary portions a and 6b.

【0003】そして、上記のようにしてパターン形成さ
れたコンタクト層6a、6bの上部に、図4に示すソー
ス電極7およびドレイン電極8をパターン形成して薄膜
トランジスタ(以下TFT:Thin  Film  
Transistorと称する)が形成される。そして
、以上のようにして形成されたTFTを覆って基板1の
全面に層間絶縁膜9が形成され、該層間絶縁膜9に設け
られたコンタクトホール90を通してTFTのドレイン
電極8に絵素電極10が電気的に接続される。
Then, a source electrode 7 and a drain electrode 8 shown in FIG. 4 are patterned on top of the contact layers 6a and 6b patterned as described above to form a thin film transistor (hereinafter referred to as TFT).
(referred to as a Transistor) is formed. Then, an interlayer insulating film 9 is formed on the entire surface of the substrate 1 covering the TFT formed as described above, and a pixel electrode 10 is connected to the drain electrode 8 of the TFT through a contact hole 90 provided in the interlayer insulating film 9. are electrically connected.

【0004】0004

【発明が解決しようとする課題】ところで、上記の方法
によれば、半導体層4にイオン注入を行った後でコンタ
クト層6a、6bがパターン形成されるため、パターン
形成後のコンタクト層6a、6bの側面にはコンタクト
層が形成されない。このため、パターン形成した後に、
コンタクト層6a及び6bそれぞれにソース電極7及び
ドレイン電極8をパターン形成すると、コンタクト層6
a及び6bとソース電極7及びドレイン電極8の間に電
流リークが発生し、TFT特性が劣化するという欠点が
ある。
By the way, according to the above method, since the contact layers 6a, 6b are patterned after ion implantation into the semiconductor layer 4, the contact layers 6a, 6b after patterning are No contact layer is formed on the side surfaces of. For this reason, after pattern formation,
When the source electrode 7 and the drain electrode 8 are patterned on the contact layers 6a and 6b, respectively, the contact layer 6
There is a drawback that current leak occurs between a and 6b and the source electrode 7 and drain electrode 8, resulting in deterioration of TFT characteristics.

【0005】加えて、半導体層4の上にチャネル保護膜
5をパターン形成し、その上方よりP+イオンを注入す
る際に、上記従来方法ではそのままP+イオンを注入し
ていたため、チャネル保護膜5上にも不純物が僅かなが
ら打ち込まれる。そのため、イオン注入を行い、コンタ
クト層6a、6bをパターン形成した後、コンタクト層
6a及び6bそれぞれにソース電極7及びドレイン電極
8をパターン形成すると、チャネル保護膜5に僅かに打
ち込まれた不純物を通して、コンタクト層6a及び6b
とソース電極7及びドレイン電極8の間に電流リークが
発生し、上記同様にTFT特性が劣化するという欠点が
ある。
In addition, when patterning the channel protective film 5 on the semiconductor layer 4 and implanting P+ ions from above, the conventional method described above directly implants P+ ions, so that the channel protective film 5 is A small amount of impurity is also introduced into the material. Therefore, after performing ion implantation and patterning the contact layers 6a and 6b, when the source electrode 7 and drain electrode 8 are patterned on the contact layers 6a and 6b, respectively, the impurities slightly implanted into the channel protection film 5 pass through. Contact layers 6a and 6b
There is a drawback that current leak occurs between the source electrode 7 and the drain electrode 8, and the TFT characteristics deteriorate as described above.

【0006】本発明は、このような従来技術の欠点を解
消するものであり、イオン注入を用いて良好なTFT特
性が得られるアクティブマトリクス基板の製造方法を提
供することを目的とする。
The present invention eliminates the drawbacks of the prior art, and aims to provide a method for manufacturing an active matrix substrate that uses ion implantation to obtain good TFT characteristics.

【0007】[0007]

【課題を解決する手段】本発明のアクティブマトリクス
基板の製造方法は、絶縁性基板上にゲート電極と、該ゲ
ート電極とゲート絶縁膜及び半導体層を介して少なくと
も一部が重畳するドレイン電極と、該ゲート電極と半導
体層を介して少なくとも一部が重畳するソース電極とを
有する薄膜トランジスタをスイッチング素子に用いたア
クティブマトリクス基板の製造方法において、チャネル
保護膜をパターン形成する工程と、該チャネル保護膜を
パターン形成する際のレジストを残し、該レジストの上
部よりイオン注入を行ってコンタクト層を形成する工程
とを含んでなり、そのことにより上記目的が達成される
Means for Solving the Problems The method for manufacturing an active matrix substrate of the present invention includes: a gate electrode on an insulating substrate; a drain electrode at least partially overlapping the gate electrode with a gate insulating film and a semiconductor layer interposed therebetween; A method of manufacturing an active matrix substrate using a thin film transistor as a switching element having a source electrode that at least partially overlaps the gate electrode with a semiconductor layer in between includes the steps of patterning a channel protective film; The method includes a step of leaving a resist used for pattern formation and performing ion implantation from above the resist to form a contact layer, thereby achieving the above object.

【0008】好ましくは、前記半導体層のパターン形成
を行ってからイオン注入を行って前記コンタクト層を形
成する。
Preferably, the contact layer is formed by performing ion implantation after patterning the semiconductor layer.

【0009】[0009]

【作用】上記工程によれば、チャネル保護膜上にレジス
トを残してイオン注入を行うので、チャネル保護膜上に
不純物が打ち込まれない。従って、チャネル保護膜上に
ソース電極およびドレイン電極をパターン形成しても、
ソース電極およびドレイン電極との間に電流リークを発
生することがない。
[Operation] According to the above process, since the resist is left on the channel protective film and ions are implanted, impurities are not implanted onto the channel protective film. Therefore, even if the source and drain electrodes are patterned on the channel protective film,
No current leakage occurs between the source electrode and the drain electrode.

【0010】また、半導体層をパターン形成してからイ
オン注入を行ってコンタクト層を形成するので、半導体
層の側面にも不純物がドーピングされることになる。従
って、イオン注入後にソース電極及びドレイン電極をパ
ターン形成しても、イオン注入を行ったコンタクト層の
側面とソース電極及びドレイン電極との間に発生する電
流リークを低減することができる。
Furthermore, since the contact layer is formed by ion implantation after patterning the semiconductor layer, the side surfaces of the semiconductor layer are also doped with impurities. Therefore, even if the source and drain electrodes are patterned after ion implantation, current leakage occurring between the side surface of the contact layer into which ions have been implanted and the source and drain electrodes can be reduced.

【0011】[0011]

【実施例】以下本発明の実施例を説明する。[Examples] Examples of the present invention will be described below.

【0012】図1は本発明のアクティブマトリクス基板
の製造方法を示しており、以下に示す工程を経て図2に
示すアクティブマトリクス基板が作成される。
FIG. 1 shows a method of manufacturing an active matrix substrate according to the present invention, and the active matrix substrate shown in FIG. 2 is manufactured through the steps shown below.

【0013】図1(a)に示すように、まずガラス基板
1上にスパッタリング法によってTaを300nmの厚
さで堆積する。次いで、この状態からTa層の上にフォ
トマスクを用いてゲート電極2をパターン形成する。そ
の後、ゲート電極2を覆うようにしてガラス基板1上の
全面に、プラズマCVD法によってSiNxからなる厚
さ300nmのゲート絶縁膜3、厚さ30nmのアモル
ファスシリコン(以下「a−Si」と称す)層4及びS
iNxからなる厚さ200nmのチャネル保護膜5をこ
の順に順次堆積する。次いで、最上層のチャネル保護膜
5上にレジスト11を塗布してa−Siのパターンでフ
ォトリソグラフィを行って、図1(b)に示すa−Si
層4とチャネル保護膜5をパターン形成する。
As shown in FIG. 1(a), Ta is first deposited to a thickness of 300 nm on a glass substrate 1 by sputtering. Next, from this state, a gate electrode 2 is patterned on the Ta layer using a photomask. Thereafter, a 300 nm thick gate insulating film 3 made of SiNx and a 30 nm thick amorphous silicon (hereinafter referred to as "a-Si") are deposited on the entire surface of the glass substrate 1 so as to cover the gate electrode 2 by plasma CVD. Layer 4 and S
A channel protective film 5 made of iNx and having a thickness of 200 nm is deposited in this order. Next, a resist 11 is applied on the uppermost channel protective film 5, and photolithography is performed to form an a-Si pattern as shown in FIG. 1(b).
Pattern layer 4 and channel protection film 5.

【0014】次いで、この状態からフォトリソグラフィ
を行って、図1(c)に示すチャネル保護膜5をパター
ン形成する。この状態において、パターン形成されたチ
ャネル保護膜5上にはレジスト11が残存している。
Next, from this state, photolithography is performed to form a pattern of the channel protective film 5 shown in FIG. 1(c). In this state, the resist 11 remains on the patterned channel protective film 5.

【0015】次いで、図1(c)に示すように、レジス
ト11を剥離せずに、この状態でチャネル保護膜5の上
方よりP+イオンを注入する。これにより、図1(d)
に示すコンタクト層6a及び6bが形成される。
Next, as shown in FIG. 1C, P+ ions are implanted from above the channel protective film 5 in this state without removing the resist 11. As a result, Figure 1(d)
Contact layers 6a and 6b shown in are formed.

【0016】次いで、スパッタリング法により300n
mの厚さのTi又はMoの金属層をガラス基板1上の全
面に形成し、この金属層をフォトマスクを用いてパター
ンニングして、図2に示すソース電極7及びドレイン電
極8を形成する。そして、ガラス基板1上の全面にイン
ジウム錫酸化膜(ITO)からなる透明電極を80nm
の厚さで堆積させ、この状態からフォトマスクを用いて
パターンニングを行って、絵素電極10を形成する。こ
れにより、本発明のアクティブマトリクス基板が作成さ
れる。
[0016] Next, a 300n
A Ti or Mo metal layer with a thickness of m is formed on the entire surface of the glass substrate 1, and this metal layer is patterned using a photomask to form the source electrode 7 and drain electrode 8 shown in FIG. . Then, on the entire surface of the glass substrate 1, a transparent electrode made of an indium tin oxide film (ITO) was formed with a thickness of 80 nm.
From this state, patterning is performed using a photomask to form the picture element electrode 10. In this way, the active matrix substrate of the present invention is produced.

【0017】このようにして作成されるアクティブマト
リクス基板によれば、上記作用の項で述べた理由により
、コンタクト層6a、6bとソース電極7及びドレイン
電極8との間の電流リークがない(若しくは電流リーク
を格段に低減できる)、TFT特性の良好なアクティブ
マトリクス基板が得られる。
According to the active matrix substrate produced in this manner, there is no current leakage (or (current leakage can be significantly reduced), and an active matrix substrate with good TFT characteristics can be obtained.

【0018】[0018]

【発明の効果】本発明のアクティブマトリクス基板の製
造方法によれば、上記した工程故、コンタクト層とソー
ス電極およびドレイン電極との間の電流リークを格段に
低減できる。従って、TFT特性のIoff電流が低減
される。それ故、TFT特性の良好なアクティブマトリ
クス基板が得られる。
According to the method for manufacturing an active matrix substrate of the present invention, current leakage between the contact layer and the source and drain electrodes can be significantly reduced due to the above-described steps. Therefore, the Ioff current of TFT characteristics is reduced. Therefore, an active matrix substrate with good TFT characteristics can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明のアクティブマトリクス基板の製造方法
を示す工程図。
FIG. 1 is a process diagram showing a method for manufacturing an active matrix substrate of the present invention.

【図2】本発明方法により製造されるアクティブマトリ
クス基板を示す断面図。
FIG. 2 is a sectional view showing an active matrix substrate manufactured by the method of the present invention.

【図3】従来の製造方法を示す工程図。FIG. 3 is a process diagram showing a conventional manufacturing method.

【図4】従来方法により製造されるアクティブマトリク
ス基板を示す断面図。
FIG. 4 is a cross-sectional view showing an active matrix substrate manufactured by a conventional method.

【符号の説明】[Explanation of symbols]

1  ガラス基板 2  ゲート電極 3  ゲート絶縁膜 4  半導体層 5  チャネル保護膜 6a、6b  コンタクト層 7  ソース電極 8  ドレイン電極 9  層間絶縁膜 10  絵素電極 11  レジスト 1 Glass substrate 2 Gate electrode 3 Gate insulating film 4 Semiconductor layer 5 Channel protective film 6a, 6b Contact layer 7 Source electrode 8 Drain electrode 9 Interlayer insulation film 10 Picture element electrode 11 Resist

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】絶縁性基板上にゲート電極と、該ゲート電
極とゲート絶縁膜及び半導体層を介して少なくとも一部
が重畳するドレイン電極と、該ゲート電極と半導体層を
介して少なくとも一部が重畳するソース電極とを有する
薄膜トランジスタをスイッチング素子に用いたアクティ
ブマトリクス基板の製造方法において、チャネル保護膜
をパターン形成する工程と、該チャネル保護膜をパター
ン形成する際のレジストを残し、該レジストの上部より
イオン注入を行ってコンタクト層を形成する工程とを含
むアクティブマトリクス基板の製造方法。
1. A gate electrode on an insulating substrate, a drain electrode that at least partially overlaps with the gate electrode through a gate insulating film and a semiconductor layer, and a drain electrode that overlaps at least partially with the gate electrode through the semiconductor layer. In a method of manufacturing an active matrix substrate using a thin film transistor having overlapping source electrodes as a switching element, a step of patterning a channel protective film, leaving a resist when patterning the channel protective film, and removing the upper part of the resist. A method of manufacturing an active matrix substrate, including a step of performing ion implantation to form a contact layer.
【請求項2】前記半導体層のパターン形成を行ってから
イオン注入を行って前記コンタクト層を形成する請求項
1記載のアクティブマトリクス基板の製造方法。
2. The method of manufacturing an active matrix substrate according to claim 1, wherein the contact layer is formed by performing ion implantation after patterning the semiconductor layer.
JP40895990A 1990-12-28 1990-12-28 Active matrix substrate manufacturing method Expired - Fee Related JP2694912B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP40895990A JP2694912B2 (en) 1990-12-28 1990-12-28 Active matrix substrate manufacturing method
EP91312014A EP0493113B1 (en) 1990-12-28 1991-12-24 A method for producing a thin film transistor and an active matrix substrate for liquid crystal display devices
DE69125260T DE69125260T2 (en) 1990-12-28 1991-12-24 A method of manufacturing a thin film transistor and an active matrix substrate for liquid crystal display devices
US07/813,385 US5286659A (en) 1990-12-28 1991-12-26 Method for producing an active matrix substrate
KR1019910025097A KR950003939B1 (en) 1990-12-28 1991-12-28 Method for manufacturing active mattress substrate
US08/154,116 US5474941A (en) 1990-12-28 1993-11-18 Method for producing an active matrix substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP40895990A JP2694912B2 (en) 1990-12-28 1990-12-28 Active matrix substrate manufacturing method

Publications (2)

Publication Number Publication Date
JPH04233512A true JPH04233512A (en) 1992-08-21
JP2694912B2 JP2694912B2 (en) 1997-12-24

Family

ID=18518349

Family Applications (1)

Application Number Title Priority Date Filing Date
JP40895990A Expired - Fee Related JP2694912B2 (en) 1990-12-28 1990-12-28 Active matrix substrate manufacturing method

Country Status (1)

Country Link
JP (1) JP2694912B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09501509A (en) * 1993-07-29 1997-02-10 ハネウエル・インコーポレーテッド Silicon pixel electrode
JP2016507905A (en) * 2013-02-19 2016-03-10 京東方科技集團股▲ふん▼有限公司 THIN FILM TRANSISTOR, ITS MANUFACTURING METHOD, AND DISPLAY DEVICE

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02196222A (en) * 1989-01-25 1990-08-02 Matsushita Electric Ind Co Ltd Production of active matrix substrate
JPH02224254A (en) * 1989-02-27 1990-09-06 Hitachi Ltd Thin film transistor, manufacture thereof, matrix circuit substrate, and picture display using it

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02196222A (en) * 1989-01-25 1990-08-02 Matsushita Electric Ind Co Ltd Production of active matrix substrate
JPH02224254A (en) * 1989-02-27 1990-09-06 Hitachi Ltd Thin film transistor, manufacture thereof, matrix circuit substrate, and picture display using it

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09501509A (en) * 1993-07-29 1997-02-10 ハネウエル・インコーポレーテッド Silicon pixel electrode
JP2016507905A (en) * 2013-02-19 2016-03-10 京東方科技集團股▲ふん▼有限公司 THIN FILM TRANSISTOR, ITS MANUFACTURING METHOD, AND DISPLAY DEVICE

Also Published As

Publication number Publication date
JP2694912B2 (en) 1997-12-24

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