JPH04230146A - Dynamic packet route setting circuit network - Google Patents

Abstract

PURPOSE: To efficiently and rapidly set a dynamic route in a digital data communication system. CONSTITUTION: A digital data communication system includes first and second processing groups constituted of plural processing cells, mutually connected by a relating bus. A ring route setting cell (RRC) is provided, and an information packet generated by the processing cell is transferred. The RRC is provided with input for receiving the packet from the bus of a first processing group and first and second output for outputting the packet to the bus of the first and second processing groups. A control element sets the route of the packet received by the input, based on the preceding route setting history of data (or a request to the data) referred in the information packet between the first and second processing groups.

Description

Detailed Description of the Invention [0001] [Industrial Application Field] The present invention is directed to digital data communication.
Regarding circuit networks, for example, high-speed distributed multiprocessing systems
Concerning a Packet Switching Network for Use with a System
. [Prior art] Multiple instruction/multiple data (MIMD) parallel processing
A physical computer has an address space, memory organization and
can be classified according to memory hierarchy. Regarding the former,
The system can utilize single or multiple address spaces.
It can be characterized as something that single address space
is generally called shared memory, and any memory access
Includes implied communication as part of. Multiple dedicated address space
e.g. through message passing.
include. Memory organization can be either centralized or decentralized.
characterized. In systems based on centralized memory
In this case, common memory elements are centrally located and any
Access times to physical memory locations are
It is made to be the same for all users. On the other hand, decentralized
In a memory system, system memory is a module.
and some are located near each processor.
I get kicked. Memory hierarchies can be static, mixed or
is characterized as dynamic. One layer is
Although classified as static, this type
Stem data can be stored in local and/or broadband memory.
Split between units, each data is at least partially
explicitly assigned based on the unit location where it is stored.
has an assigned address. On the other hand, completely dynamic
In a block-type system, each piece of data is
Address based on physical memory location to access
No space is assigned. Mixed memory hierarchies are
This may include local and/or broadband memory for
types, the memory hierarchy is dynamic (e.g. cache
(memory), and other parts are static. According to the prior art, a single address space
i.e. a large number of shared memories organized in a centralized manner.
architecture is provided. of such a system
The processing unit is a high-bandwidth shared bus or
Communicate via switching circuitry. This kind of architecture
One problem with servers is that shared memory forms a bottleneck.
except in cases where there are only a relatively small number of processors.
This means that the characteristics of the system are hindered. [0005] To avoid this problem, Frank et al.
Patent No. 4,622,631 each
multiple processors with base memory or cache.
Processors share data contained in main memory elements.
A multi-processing system is disclosed. that common
Data in memory is partitioned into blocks, each of which
Main memory and any one of multiple processors
can be owned. The current owner of a data block is its
It is said to have the correct data for the block. The solution suggested in the above-mentioned patent is that the bottle
Allows for an increase in the number of processors that can be supported without bottlenecks.
However, centralized memory systems are not scalable. [0007] In order to achieve increase/decrease potential, decentralized
Memory organization must be used. This is a process
memory is proportional to the number of processors and memory modules.
Parallel high-bandwidth access can be theoretically increased
It is from. According to the prior art, for this type of tissue
Two alternative programming models are provided. sand
That is, multiple address space formats and single address space
It is a model. Both formats are computer system data
presents a dilemma for designers and programmers. From a programmer's perspective, a single address
A architecture that allows data movement to occur in memory operations.
is implicit, so it is a simple programming model.
Ru. On the other hand, in a multiple address architecture, one
explicit messages for multiple address architectures.
page passing is required. Additionally, multiple addresses
The architecture is designed to generate correct parallel programs.
Explicit data localization, explicit memory allocation and
Requires deallocation, explicit replication, and explicit coherency.
Essential. These aspects are unique to single-address architectures.
theoretically and implicitly in the In the prior art from the hardware perspective view
A single address space, as found by the designer
i.e. concurrent access to logically shared memory
is extremely expensive. This is the switching network
complexity and memory coherency
Lack of a general high-performance solution and its potential complexity
Due to gender. Therefore, Intel/IPSC-like
Distributed memory systems that can increase and decrease their size have been
Historically implemented with multiple address architecture. [0010] The performance of single address architecture
Depends on memory hierarchy. The static memory hierarchy is
, similar to a multiple address architecture for programmers
Explicitly move data for optimal performance in terms of
management is required. static memory hierarchy
Distributed to implement a single address architecture using
Two examples of type memory organizations are BBN butterfly and
It is IBM RP3. This kind of implementation is useful for programmers
requires explicit management of coherency. [0011] Mixed hierarchies necessarily limit the possibilities of increase and decrease.
This includes communication bottlenecks, but still requires the programmer to
requires partial control over the movement of one thing
The hierarchical method of species is described by Wilson Jr. British specials such as
No. 2,178,205, but this
In the patent, the multiprocessing system
Distributed cache memory interconnected via one bus
It is said to have a mori element. 1st bus and higher
Either level cache or main system memory
A second higher level cache note attached to
copy of each memory location in the cache, if any.
system main memory, and caches below it.
maintain a copy of each memory location in the cache. Wilson
Jr. Processors such as
from its own dedicated cache
to the main memory of the system and to the
, its own copy of that newly modified data.
Notify other caches to invalidate. Despite the solutions provided by the prior art
, all high-performance, fully dynamic, and consistent
Unlimited scaling possibilities for memory-based programming environments
There is nothing we have achieved together. [0013] The general object of the invention is to
more specifically, shared memory.
using an addressing model and decentralized organization and
Multiple instruction/multiple data parallel processing with improved herency
The goal is to provide a system. Another particular object of the invention is to provide a shared memory
High performance in distributed systems that utilize dress models
provides a fully dynamic memory hierarchy that achieves
Is Rukoto. Still another specific object of the invention is to provide improved
The objective is to provide a digital data communication network that
. [0016] Still another object of the invention is, for example, to
for use in distributed multiprocessing systems
The purpose of the present invention is to provide a packet switch network. Still another specific object of the invention is to
Routes data and data requests through the digital communication network.
Improved switching for use in setting
It is to provide a mechanism. SUMMARY OF THE INVENTION These and other objects of the invention are:
e.g. for use with multiprocessing computer systems
Improved digital data communications network, packet
by providing switch and associative directories.
will be achieved. According to one aspect of the invention, the system of the invention
The system consists of two groups of processing cells, and
Data referenced within the packet and the process
Data required by the first of the processing groups
or the data assigned to said first, or the previous
routed between processing groups.
Distribute data between these groups based on data identification.
A routing cell that transfers digital data information packets and
Equipped with [0020] Each processing group has an associated
Data packets and request packets via loop bus
Multiple processing centers that communicate by transferring
e.g. central processing unit and associated
Equipped with local cache memory. Individual cells are
Relatedly, data that can be identified by a unique descriptor
data or data copies. Inside the processing cell
If the data request packet is
data or data copies in response to such requests.
Generate a packet to serve. Each packet is
contains descriptors corresponding to the data supplied. [0021] The rules and configuration elements are
first and second inputs connected to the bus of the loop and
Connected to the output section and the bus of the second processing group.
a second input and an output section connected to each other;
The input and output parts of
It sends and receives packets to and from cells. 1st o
and request and response packets received on the second input.
descriptors in those buckets.
The data to be identified is a cell of the first processing group.
one of the outputs depending on whether it is assigned to
Or routed to both. Packets received by the routing cell
To make it easier to decide where to route the
The associative memory-based directory is
corresponds to the data assigned to cells in the cell group
Store a list of descriptors. The directory is
In addition, a second processor is required for processing by those cells.
Descriptors routed to a processing group
list of data, as well as the list of data for the second processing group.
requested by the cell and sent to the first processing group for processing.
Write down the list of descriptors routed to the loop.
I remember. The directory contains these descriptors and
also maintains information about the access state of the data.
. This can be done, for example, in addition to pending state, disabled,
read-only, non-exclusive ownership, exclusive ownership, and
and atomic states. According to related aspects of the invention, the above-mentioned
2 A processing group itself has multiple other
processing group, which group itself
, interconnected via routed cells and network buses.
each interconnected by an intragroup bus.
It has multiple processing cells. As an example,
In a two-level system, each other group has an individual
Selectively send and receive information packets to and from the group bus
Associated with a routing cell. Review below
Bell: 1 A higher level bus referred to as a bus is
These other routing cells are routed to the first processing group.
Connect with loops and associated routing cells. According to the invention, other related aspects include
, each consisting of multiple interconnected processing cells.
Has multiple packet forwarding levels including forwarding segments
A hierarchical digital data communication network is provided. cell
are data that can each be identified by a unique descriptor.
Or a data copy is assigned. The cell also
Request to reference data by each descriptor
Cache control that can generate packets and response packets
equipped with a control unit. The number of transferred segments is higher than each
at the highest transfer level, and one at the highest level.
There are only segments. [0025] Within the network, each routing cell
level processing cells and higher level processing cells.
Enables communication with single cells. Transfer level segment
The route setting cell that transfers information packets between
, the data and underlying transfers required in the packet.
Select request packets based on their association with the segment's cells.
Route selectively. Specifically, these routes
A configuration cell is a derived cell in a higher-level transfer segment.
packets requesting data unrelated to the
and set the lower segment to the lower segment.
Route packets requesting relevant data. According to another aspect of the invention, the request packet
is a request that identifies the processing cell that generated the request.
The requester ID field may be included. The essence
A cell that generates a response to a request sends the requester ID to the response packet.
Copy to cut. The route setting cell is the requester ID
The response pattern is sent to the requester according to the value of the field.
Set the return route for the ket. [0027] In addition, the route setting
packets, i.e. request packets generated by other cells.
1 response packet containing the data requested at the client.
can be routed to one requesting processing cell. Thus, for example, two processing cells can
Contains read-only copies of legally required data
If the response packet has only one of the requester IDs
Regardless of what is included in the response packet, both parties
can be set. These and other objects of the invention and
The advantages are clear from the explanation given with reference to the drawings below.
Become. EXAMPLE [Summary] Switching network constructed according to the present invention
A preferred digital data processing system that utilizes
0, 1 or multiple processing via ring bus
one or more routing interconnects coupled to a cell
multiple processes arranged in a ring hierarchy, each containing
Equipped with goosels. Route configuration links linking interconnects
The ring selectively transfers information packets between rings.
provide a transmission path for Directory within the route configuration cell
The data transferred through the associated cells (and the required
requests) and thereby track subsequent routes for subsequent packets.
Determine the route setting route for the route setting. In one preferred embodiment, the process
Each processing cell has a physical data and control signal store;
a local memory element with directory and control elements;
i.e. equipped with a central processing unit coupled with a cache.
I can do it. Cells are connected along a unidirectional intercell bus ring.
are combined to form units called segments. child
These segments together have "information transfer level: 0"
form a larger unit called. Different levels: Communication between cells of 0 segment
communication at a higher information transfer level, e.g.
Implemented via Level: 1 and Information Transfer Level: 2. These higher levels are themselves unidirectional bus
each from multiple routing cells joined via
It consists of one or more segments. Each roux
The default setting cell is the associated cell at the next lower information transfer level.
is combined with the component. These combined lower
Segments are referred to as "subordinates." [0032] Each information transfer level is connected to the next lower level.
contains fewer segments than the file. the highest level of the system
Apart from a single segment of the level, the signal contains each information
Transfer-level segments between higher-level
Transferred via segment. [0033] The route settings are for each sub-segment member.
The disk corresponding to the data allocated to the memory element.
Contains a directory of files. As an example, level: 0 se
Route settings to connect segment to level:1 segment
The cell is assigned to a cell in its level:0 segment.
Contains a directory of all the data that was
:1 segment to level :2 segment
The level: 1 segment is connected to the segment.
: Data assigned to all cells of 0 segment
Contains the data directory. [0034] The directory, along with the descriptor
, accessing data allocated to lower segments
Remember the state. These states include, for example, possessed
status, read-only status, and disabled status.
Ru. Ownership state, like atomic state,
associated with data that can only be modified by the processor.
It will be done. On the other hand, ownership state is different from atomic state data.
and by other processing cells--e.g.
- can be accessed to generate a do-only copy
. A read-only state is a local central processing unit.
data that cannot be changed but can be read.
associated with ta. An invalid state is an invalid data copy.
be related. [0035] In this regard, preferred embodiments constructed in accordance with the present invention
New digital data processing systems require main memory elements,
i.e. coupled to a multi-processing cell, thereby
It would be acceptable not to make use of shared memory elements.
. Rather, data is stored on an exclusive bus and shared
associated with each of these processors on the bus.
Distributed among local memory elements. any one process
Changes to data stored exclusively in single cells are
, communicated to other processing cells via a circuitry
does not require This results in data that cells dynamically share.
only on the network, i.e. ring bus and route
is transmitted along the set cell, thereby reducing bus contention and
and reduce bottlenecks. [0036] The routed cell directory is also associated with
packets routed by a routing cell that
Write down the descriptor corresponding to the data required in the
I remember. As mentioned above, the directories are
Along with the scripter, the requested access state of the data
Stores ongoing information data that directs. In view of the above points, the route setting cell
contents of the directory -- i.e. the allocated data
and ongoing request list--are processed by the processing group.
Routed data and data requirements between
Reflects the legacy history of request routing. [0038] The route setting cell includes a descriptor and
Use state directories to navigate along level segments.
A particular packet of information that is moving
before other processing cells in the emitted segment.
Should I be routed to another segment instead?
determine whether the route should be routed upward or downward.
do. To further understand this route setting function
In a preferred multiprocessing system constructed in accordance with the present invention,
In the system, data access requests are
to be processed within the processing cell that emitted them.
It would be recognized that Details are combined with each monitor
The controller monitors the cell's internal bus and routes requests locally.
Descriptors listed in cache directory
to respond to local processor requests by comparing
Ru. If consistent data from the cache itself is
Once found, the data is sent along the internal bus to the requesting program.
It is transmitted back to the processor. [0040] If the data request cannot be resolved locally,
The processing cell generates information request packets and
This is done locally via the local cache control unit.
transferred to the processing bus. That packet is sent along the ring
When moving, processing units adjacent to the requester
Knit control element checks its own directory
and put the requested data (if any) into the response packet.
Pass. [0041] Unresolved requests are
When passing through the routing element of the segment to which the cell belongs
and that element also checks that directory. if
The directory also has the required data on the correct address.
indicates that it exists in the local ring in access state.
The configured cell sends the request packet along the local ring bus.
Let it continue. If not present, the routing cell will be
, extract the packet and put it into the relevant level: 1 segment
Pass it through the port. Outstanding request packets are leveled in a similar manner.
Move along one segment, i.e. move along one segment, i.e.
level: 1 compared to the directory of the root setting cell.
Ru. One of these directories is at the lower level: 0
Requested data with proper access to the segment
If you list the data, the request is routed to that segment.
It will be done. On the other hand. The request is at a higher level in the hierarchy (if any)
or return it to the unresolved requester.
. [0042] The packet containing the requested data is
routed back to the requesting cell by some mechanism.
It will be done. The first mechanism is the requesting cell's address or I
Depends on D. Here, each requesting cell is
The packet contains an ID that uniquely identifies that cell.
Ru. When that packet reaches the responding cell, that cell
, requester ID as data and corresponding descriptor
data into the response packet. response packet
When moves along the segment ring, the route setting
The cell tests the requester ID and the requesting cell
or determine whether the packet is in the parent segment
Route accordingly. [0043] As required by the processing cell,
Contains data that is not generated in detail in response to these requests.
A second mechanism is used in conjunction with response packets that include: As an example, this mechanism may
cell for certain data held within a remote cell.
This applies when a read-only copy request is generated.
Ru. According to a preferred embodiment of the invention, these
At least some, but not all, of the requests are
to reach a processing cell that has a copy of the data.
Assuming that the circuitry blocks, the responding cell
Holds only the requester ID of the request packet that reached
Generates a response packet. [0045] The response packet is routed along the network.
When the routing cell is
folders and access information state within those directories.
Compare with the ongoing request entry. By that comparison
, the routing cell sends a data request in the form of a packet.
When it becomes clear that the packet has already been received,
(or a copy of it) is routed to one of the requesting cells.
Can be set. In this way, e.g. reading data
A single packet containing only-copy may have multiple outstanding
It can effectively act as a response to a read-only request.
Ru. [System Structure] FIG. 1 shows a system configured according to the present invention.
Delineate a preferred multiprocessing system that utilizes communication networks.
It is something. The example system 10 includes three information transfer levels.
Bell, i.e. Level: 0, Level: 1 and Level
Including: 2. Each information transfer level is
one or more interface elements having as its characteristics
or multiple segments. To elaborate, an example scenario
Stem 10 level: 0, 6 12A, 12B,
12C, 12D, 12F and 12F respectively.
Contains six segments. Similarly, level: 1 is
14A and 14B, and the other level: 2 is
A segment 16 is provided. Each segment of level: 0, ie 12
A, 12B, ---12F are multiple processing
Equipped with a cell. For example, segment 12A is cell 18A
, 18B and 18C, segment 12B is a cell
18D, 18E and 18F. each of these cells
are connected to each other by an intra-cell processor bus (not shown).
connected central processing unit and memory elements
Equipped with In a preferred embodiment of the invention, each cell
The memory elements contained within the
All control and data used by the
memorize the data signal. As further illustrated, each level: 0 se
A segment is a packet of information between cells in a segment.
has a bus element that provides a communication path for transferring
It can be characterized as a thing. Thus, the example segment
Component 12A has bus 20A as its characteristic and has segment
segment 12B has 20B, segment 12C has 20C,
The same applies below as its characteristics. Detailed below
The digital information packets are
example segment through the memory elements associated with each of the files.
Passed between cells 18A, 18B and 18C of 12A
. Certain interfaces between these memory elements and bus 20A
the cell interface unit as shown.
Provided by Knit 22. A similar direct communication channel, e.g.
As shown, segments 12B, 12C and 12
In D, each cell 18D, 18E, --- 1
Between 8R, cell interfaces 22D, 22E,
--- Set by 22R. As shown in the example and mentioned above, the remaining
Information transfer levels, i.e. Level: 1 and Level: 2
segment, each with one or more corresponding levels:
include. The number of segments in each successive segment is
smaller than the number of segments of things. i.e. level:
The two segments 14A and 14B of 1 level:
0's six segments 12A, 12B --- 12F.
The other level has only one segment 16.
2 has the least number of segments among all. Re
Bell: 1 and Level: 2, i.e. higher level
Each segment of
Contains bus elements that transfer packets. In the example,
Bell: 1 segment 14A and 14B each
24A and 24B, and the other level::2 segment.
Component 16 includes bus element 26 . Routing itself involves successive levels of
Provides a mechanism to transfer information between connected segments
do. For example, routing cells 28A, 28B and 2
8C is level: 1 segment 14A and level: 0
Between each of segments 12A, 12B and 12C
and provide a means for transferring information. Similarly, the rule
Settings 28D, 28B and 28F are level: 1 segment.
ment 14B and level: 0 segment 12D, 12
To transmit information between each of E and 12F
provide the means for Furthermore, route setting cell 30A and
and 30B are level 2 segments and 30B as shown.
and level: between 1 segment 14A and 14B
Provide information transfer path. To be discussed in detail later
, each routing cell includes two processing units.
I'm reading. Routing cells are interconnects on bus elements.
interface those segments through connections.
Continue. That is, the route setting cells 28A each have
Bus element 20 at ring interconnects 32A and 34A
A and 24A are interfaced and element 28B
at ring interconnects 32B and 34B, respectively.
Interface connection of bus elements 20B and (24)B.
The same applies hereafter. Similarly, route setting cell 30A
and 30B are ring interconnections, respectively, as shown.
At the continuation parts 36A, 36B, 38A and 38B respectively.
buses, namely 24A, 24B and 26, are
Connect face to face. FIG. 1 is further constructed in accordance with the present invention.
level of remoteness in digital data processing systems
and illustrates a preferred mechanism for interconnecting cells.
. A server located at a physically remote point from bus segment 20F
18R indicates the fiber optic transmission line indicated by the dotted line.
via that segment's bus and its associated cells (
18P and 18Q). remote interface
The base unit 19 has a cell interface 22R and
provides a physical interface between the remote cell 18R and remote cell 18R.
Ru. Remote cell 18R is configured similarly to other exemplary cells.
and works similarly, for joining fiber optic links.
A remote interface unit is provided. Similarly, level segments 12F and 1
4Bs connect fiber optic links from their parent segments.
interconnected through. As indicated by the dotted line,
The respective portions of routing cells 28F and 30B are
, physically separated but connected to other fiber optic links.
More connected. For example, the route configuration unit 28
Regarding F, the first part is a standard bus interconnect.
Route configuration interface for segment 14B via
34F, while the second part
is the route setting interface 32 of segment 12F.
Directly linked to F. As mentioned above, route settings
Physical interface between unit parts and fiber optic media
The base is connected to a remote interface unit (not shown).
provided by. FIG. 2A shows a multiprocessing system of the type described above.
The preferred method for maintaining data coherency in
This is an example of the format. The illustrated system is
associated memory elements 42A, 42B and 42C, respectively.
multiple central processing units connected together
40A, 40B and 40C. Each pair of processes
Communication between the processing unit and the memory unit is shown in figure
along buses 44A, 44B and 44C as shown.
administered. The level segment and route settings mentioned above
The circuitry 46 represented is an exemplary processing cell 4
Information packets (buses 48A, 4
8B and 48C to network 46)
In an exemplary embodiment, the central processing
The monitoring units 40A, 40B and 40C each have their own
Accessories labeled 50A, 50B and 50C respectively.
A service request element is provided. These access request elements
Data stored in memory elements 42A, 42B and 42C
Generates an access request to the data. Elements 50A, 50B
Among the access request signals generated by and 50C are
, exclusive modification access to the data stored in the memory element.
There is an ownership request signal that represents a request for access. Preferred embodiment
In the access request elements 50A, 50B and 50
C is the central processing unit 40A, 40B and
Contains a subset of instructions that are executed on the 40C. this life
The command subset will be explained later. Memory elements 42A, 42B and 42C are
, each comprising control elements 52A, 52B and 52C.
do. Each of these control elements has a corresponding
through directory elements 56A, 56B and 56C.
and connect to data storage areas 54A, 54B and 54C.
be done. Stores 54A, 54B and 54C are
The data required by the central processing unit
Provides physical storage space for data and command signals
as utilized by the illustrated system. Thus, store 54A is used by CPU 40A.
store 54A and control information.
and 54C are each central processing unit 40.
Maintains information used by B and 40C. Each space
The data maintained in the store corresponds to the system address.
Identified by a unique descriptor. These di
The scripter will write the address storage location of the corresponding directory.
stored in the location. Descriptor is considered unique
However, multiple copies of some descriptors are stored in memory elements
It can exist between 42A, 42B and 42C. in this case
, these multiple copies of the same data element are themselves
Identify copies. Central processing unit 40A, 40
The access request signal generated by B and 40C is
A description of the requested data, along with other control information.
or SVA (System Virtual Address).
Contains the descriptor or SVA request part. control
Elements 52A, 52B and 52C
Processing units 40A, 40B and 40C
In response to access requests generated by
data is recorded in the corresponding storage elements 54A, 54B and 54C.
Determine whether it is remembered or not. If so, please
That item of information is used by the requesting processor.
Transferred for use. If not, the control unit
Ports 52A, 52B and 52C are packets containing requests.
to network 46 along lines 48A, 48B and 48C.
Transmit. Control units 52A-52C also include circuits
network 46 and whether they receive remote access requests (i.e.
requests received from other processing cells).
Decide whether to get it or not. As mentioned above, on the return route network 46
Descriptor and status of access requests received by
descriptors stored in those directories.
Compare with ta. The requested data is visible in the requested state.
When issued, it directs the requesting unit to the
Therefore, the response packet is returned to the network 46 and transferred. request
The data being processed is stored in any of the system's processing cells.
is not present in the system, the operating system
You can search for peripheral devices on the computer. Data coherency refers to data requests and
Due to the cooperative action of processing cells in response to transfers
maintained. More specifically, the first process
Ownership--same as the generation of access request packets
When the memory associated with it is stored in physical space
allocate and hold the requested data. Similarly,
Requests from processing cells where data is stored in
At the same time as the requested data is transferred, the associated memory is
Physical storage previously allocated for storage of stored data
Deallocate space. These cooperative operations are illustrated in FIGS. 2A and 2A.
Illustrated in Figure 2B. The first of these figures
In other words, in Figure 2A, DATUM(0), DATUM(1
) and DATUM (2) are paired with CPU40A.
It is held in the store of memory element 42A. direct
Descriptors foo and bar held in the library 56A
and bas are their
Compatible with data. This descriptor is
A point supporting the location of the relevant information signal in store 42A.
Contains data. The memory element 42B paired with the CPU 40B is
Store DATUM(3) and DATUM(2). Each of these data elements is located in directory 56B.
The retained descriptors car and bas are paired
I am responding. DATUM(2) and its descriptor
The tab bas is copied from store 42A and therefore
have the same label. The system illustrated in FIG. 2A has a CPU
No data is stored in memory element 54C paired with 40C.
stomach. FIG. 2B shows that the data has already been accessed.
Processing cells that are not
exemplify how to move in relation to ownership
It is something. To be more specific, examples include CPU 40C and
DAT by processing cell consisting of memory 42C
Following the issuance of an outstanding ownership claim against UM(0)
It depicts the movement of DATUM (0). First, the system
The control unit 52C, upon request, controls the memory element 42C.
physical storage space is allocated to the store 54C. Mail
The response packet generated by memory 42A is
The data, that is, DATUM(0), is stored in the store 54A.
Request from (the data was previously stored here)
The data is transferred to the data store 54C. At the same time, the control unit 52
A of the store 54A that previously held the requested data.
Deallocate space. At the same time, control unit 5
2A is the descriptor foo in the directory 56A
(To identify DATUM(0) in store 54A
(previously used) and the other control unit
Knit 52C directs the same descriptor
56C. However, the descriptor
The controller then identifies the signal in store 54C.
used for. Memory elements 42A to 42C are disk drives.
access to data and control signals in addition to
Assign state information to each store. disabled, lee
These include do-only, ownership and atomic state.
The access state of data is accessed by a particular processor.
control the manner in which it can be accessed. The associated CPU
stored in a memory element that maintains modified access to the data
An ownership status is assigned to the data that is created. on the other hand
, its associated CPU has priority access for that data.
Data stored in memory elements that do not maintain a
A code-only status is assigned. Furthermore, “bad”
Data and related data are assigned an invalid state
. A digital device constructed in accordance with the present invention
Maintaining memory coherency within a data processing system
For the preferred structure for
USSN 136,930 and USSN 3702
No. 87 may be understood by reference to No. 87. FIG. 3 shows the level of the example shown in FIG. 1: 0 segment.
2 depicts a preferred configuration for the ment 12. Segment 12A is segmented along bus segment 20A.
interconnections 22A, 22B and 22C.
connected processing cells 18, 18B and 18C
Equipped with The route setting unit 28A is set to level 0
segment 12A and segment 14 of level 1 in Figure 1.
It provides an interconnect between A (if it is a parent).
Ru. This route setting unit 28A, as shown in the figure,
It is coupled to bus 20A via cell interconnect 32A. The structure of the illustrated bus segment 20A and its
cell interconnects 22A, 22B, 22C and 32A;
The relationship between the above-mentioned related patents, e.g.
Better seen by reference to U.S. Patent Application No. 509,480.
be understood. FIG. 4 shows an exemplary processing unit of the embodiment.
1 depicts a preferred structure for knit 18A. example
The illustrated processing cell 18A is connected to the processor bus 66.
and external device interface via instruction bus 68.
cache 60, data subcache 62, and instruction subcache 62.
Central processing unit combined with cache 64
It is equipped with 58. A more complete version of the circuit illustrated in this figure
A further understanding is that the related patents mentioned above, e.g.
U.S. Patent Application Nos. 136,930 and 199, dated 2
U.S. Patent Application No. 509,480, dated April 13, 2013;
U.S. Patent Application No. 370,325, dated June 22, 1989
No. 49 and U.S. Patent Application No. 49, dated March 26, 1990.
This can be achieved by referring to No. 9,182. Memory System: As discussed above, the present invention
Therefore, the configured multiprocessing system 10 is a system
Associated with each data based on virtual address (SVA)
By referencing its own descriptor,
Assigned to single cells 18A, 18B, ---, 18R
Allows access to individual data elements that have been created. In the example system 10, the implementation of this capability is
processing cell memory units and these memory units.
request and response packets via network 46 between
provided by the cut transfer operation. In the following discussion
, which are collectively referred to as a memory system. A complete explanation of the structure and operation of the memory system.
Understand its architecture review listed below
It will be achieved through (1) Data storage--the memory of each cache is a page
each page is divided into pages with SVA spaces.
can be dynamically assigned to a page. memory system
, usage and state information about the data in each cache.
maintains information and efficiently transfers information to and from secondary memory.
make it easier to move around. (2) Data locality--The memory system
Data recently referenced by a processor
Keep in subcache or cache in the same cell
. (3) Data movement--memory system refers to it
Move data to the processor's cache. (4) Data sharing--The memory system
maintains a copy of the data in one or more caches and
gram facilitates efficient data sharing. (5) Data coherency - Memory systems are
A well-ordered coherent memory model and
implementation model. Be tech savvy
For example, all processor operations execute in some sequential order.
If the result of any run is the same as if the system
system is "sequentially consistent" and each individual processor
in the order in which the behavior of the program is specified by the program.
It is recognized that it appears in Furthermore, if any one processor
access to data starts in program order,
issued, executed, and if executed by processor I.
At the time the store is observed by processor K, the store is
All to the data carried out regarding I prior to issuance of the Toa
If the access of has to be performed with respect to K, then
Memory accesses are considered "strongly ordered." child
In contrast, if access to synchronized variables is
If commanded, all selection data access is carried out.
synchronized changes in the processor before
Access to the number is not issued and if the variable is synchronized
the processor before the previous access to the
If access to the data is not issued by
Reaccess is weakly organized. A coherent system with a strong command of events
The system is sequentially consistent. SVA space in the example system
The organization of memory is a major departure from ordinary virtual memory schemes.
It is. Traditional architectures set the system address to
It is mapped to a physical memory addresser and
Software control page level that generates page exceptions
Contains file conversion. In these systems, software
page tables across all segments in use.
Controls multiplexing. Example system architecture
software-controlled page-level converter
There is no structure. Memory systems are based on traditional architectures.
address normally performed by software in the
can handle a significant portion of space management. these tubes
Management responsibilities include: (1) Maintain page usage and status information
to do. (2) Reusing old pages.
(3) Shared data access between multiple processors
synchronize and ensure coherency. (4) Data and data copy within the system
- move from place to place on a subpage basis and
Keep your data close to the processors you use most often.
to hold (5) Moving the data SVA together with the data
directly displays the sparse representation of the entire SVA space.
To be implemented.
(6) Moving pages between reference cells (page
There is no fixed origin for the example system's processors, e.g.
The processors 40A, 40B, 40C are the two main logic interfaces.
communicates with the memory system through the interface. 1st i
interface is a data access interface.
and this is accomplished by load and store instructions.
It will be done. In data access mode, the processor
, SVA and access mode information in the memory system
and the memory system sees the subpage containing the data
Satisfy its access by putting it back on
try The second logical interface mode is control
access, and this is a memory system control instruction
Implemented by In control access, the processor
instructs the memory system to perform some lateral action.
and return some information other than the actual data from a page. S
In addition to the main interface, the system software also provides
SPA space for configuration, maintenance, fault recovery and diagnostics
control position within the base. [Hierarchy] The memory system implements hierarchical storage (memory).
give In the illustrative preferred embodiment, each process
A processing cell is a cell that stores 0.5 megabytes of data.
A central processing unit (all
In other words, CEU). These processing cells are
It also has a cache that stores 32 megabytes of data.
include. Furthermore, it has, for example, 15 processing cells.
Preferred level: 0 stores a total of 480 MB
do. On the other hand, it is preferable to have, for example, a level of 32:0
Level: 1 has a total of 15360 megabytes. [Cache structure] The memory system has pages and
Data is stored in units of pages. each individual cache
32-byte SVA subdivided into 2048 pages
Describe a space. Pages are 27 (128) by
214 (16348) bytes divided into subpages
including. The memory system is cached on a page-by-page basis.
memory, and each page of SVA space is
Either completely or not at all represented on the stem
It is. Memory system is a unit of subcache
to share data between caches. [0077] SVA space pages are in the system.
If it exists, the following can be said. (1) One or more
A number cache allocates one page of memory to a page.
Teru. Each subpage of a page has an allocated space.
(
2) Each with space allocated for one page
The cache caches information about all of a page's subpages.
It may or may not include copies. Between cache pages and SVA pages
The association is for each cache in that cache directory.
recorded in the file. Each cache directory is
Constructed by Lipta. Each page of memory in the cache
There is one descriptor for each page. specific time
At that point, each descriptor is said to be valid or invalid.
Ru. If the descriptor is valid, the corresponding cache memo
Repage is related to one page of SVA space
and the descriptor contains the associated SVA page address and
and status information. If the descriptor is invalid
, the corresponding cache memory page is logically
Not in a good condition. Explicit enable flags associated with descriptors are
mooring and holding fields are both clear.
The descriptor can be considered invalid if S
There are no valid subpages for VA pages. Each cache directory has a content address.
Acts as memory that can be accessed. This will cause the cache to
You can perform an interactive search through all of the descriptors of
Disk for a specific page in the SVA space instead of
Cryptocurrency can be found. Each cache de
Directory contains 16 way sets with 128 sets
- Implemented as an associative memory. All of SVA space
Each page has an associated set of cache directories.
It is divided into 128 equivalence classes. for 1 page
only one descriptor is included in the page's equivalence class.
stored in a corresponding set of cache directories
. Equivalence class is selected by SVA[20:14]
. At a given point in time, the cache uses SVA[20:14]
Describe no more than 16 pages with the same value for
Wear. This is because there are 16 elements in each set.
Ru. [Subpages and data sharing] Subpages and data sharing
page exists, each of its subpages may contain one or more
exists in multiple caches. Subpages are cached
for the containing SVA page, if present in the
The descriptor (in its cache)
Records the existence of a page in several states. to cache
The state of a subpage in determines two things. vinegar
(1) The local processor of the cache is
What operations can be performed on the data residing on the page? (2) If necessary, the cache can be used by other caches.
for that subpage that is received through the level from
What response do you make to the request? [0081] The status of the subcache within the cache is as follows:
When a program requests an action that requires a certain state
change over time. One set of conversion rules
sub-processors resulting from processor requests and inter-cache level communication.
Identify changes in page state. [0082] When the processor completes an instruction or data reference,
In order to achieve this, several conditions must be met simultaneously.
do not have. That is, (1) In the case of instruction reference, the subblock containing data is
, must be present in the instruction subcache. sea bream
For most data operations, the subblock containing the data is
, must exist in a suitable state in the data subcache.
Must be. (2) The subpage containing the data resides in the local cache.
must exist. (3) Local cache maintains subpages in an appropriate state.
Must have. [0083] If the data is needed in the subcache
does not exist in the correct state, but the local cache does exist in the correct state.
exists, the CPU gets the data from the cache
. If the local cache does not have the data in the correct state.
, the cache communicates through levels and subpages
or as needed for that subpage.
Get the state, or both. Moshiki
If the cache does not satisfy the request, the cache
returns an error signal to notify the processor of the appropriate exception. The instruction set supports several different types of loading.
and store instructions, which are stored in the program
Expected future data reference pattern for the current thread of control
subpage state appropriate for
requires a protocol between different control threads. This section first describes states and their transformations.
Regarding processor instructions and their impact on cache.
Describe it as follows. [Subpage status] Subpage status and their conversion
Rules offer two general mechanisms to programs.
offer In other words, (1) the mechanism performs normal load processing by the system's processor;
strongly ordered sequential for read and store accesses
Transparently enforce a consistent memory access model. (2) Mechanisms are used in programs to synchronize parallel computations.
A set of transaction properties used by
provide the following information. These primitives come in a variety of conventional forms.
It can be applied to conventional and non-conventional types of synchronization mechanisms. The basic model for data sharing is
Three classes of subpages: do-only and owner
Defined by status. These three classes are
They are ordered with the strength to follow the access they allow. letter of invalidity
status does not allow access. The read-only state is
Allows load and instruction fetch accesses. several kinds
There is an owner state, but these are all loaded access
cache and access data from the interconnect.
respond to requests, and some allow store access.
To tolerate. Only one cache can exist at any given time
A specific subpage can be maintained in an owner state. sa
The cache that holds subpages in the owner state is
owner of the page. Ownership of each subpage is
The processor has store instructions and special requests that require ownership.
When requesting ownership with a load instruction, the cache
and move it to cache. The following sections describe state classes, and
Sequentially consistent memory accesses where they are strongly ordered
how they interact to implement the model.
I will write about it. [Invalid state] If the subpage does not exist in the cache
, it is said to be in an invalid state with respect to its cache.
It will be done. Processor is invalidated in its local cache
Request a load or store to a subpage in the state
Then, the cache is used to satisfy data accesses.
request a copy of that subpage in some other state.
Must be. Two invalid states or invalid disks
There are lipta and invalid. A specific cache for a specific page
If it does not have a descriptor, all subpages of the page are
The descriptor is in an invalid descriptor state in its cache.
It is said that there is. Thus, if you are in an invalid descriptor state,
subpages that are not explicitly represented in that cache.
stomach. [0090] If CEU is an invalid descriptor,
When referencing a page, the local cache uses the descriptor
(in the correct set) to the SVA
. After the descriptor assignment is complete, all pages for that page
The page has an invalid state. [0091] If the local cache is
scriptor, but certain subpages
subpage is in an invalid state.
Ru. Local caches can communicate with other caches
Attempt to obtain subpage data by [Read-only state] Only one read-only state
, that is, read-only exists. subpage place
provided that the owner keeps the subpages non-exclusive.
, any number of caches can read a particular subpage.
It may be possible to keep it in a "do-only" state. subpage
owner of any other state (i.e. exclusive ownership letter)
i.e. exclusive, atomic or transient
atomic one), read-only copy
cannot exist in any cell. CEU is read only
You cannot change a subpage that is in the - state. Owner State: There are two basic owner state forms:
There are non-exclusive and exclusive ownership rights. specific cap
When the browser keeps certain subpages in a non-exclusive state
, some other cache read-only that subpage.
- can be held in the -state. On the program,
Non-exclusive state is the same as read-only state. C
The EU cannot modify subpages that are in a non-exclusive state
. Non-exclusive state is basically used by the memory system.
is the bookkeeping state used, and it is supported
Establish ownership of webpages. Exclusive ownership states are exclusive, atomic,
and transient atomic. specific cap
holds exclusive ownership of certain subpages
and other caches are read-only or subpage
or hold a non-exclusive copy. local cache
Keeping subpages under exclusive ownership allows STT to
Allows write access to the segment and
The condition is that the write/no write flag is cleared.
CEU can change subpage data. [Atomic state] Atomic state is better than exclusive state.
is also a strong form of ownership. Only subpages can be programmed
entering or exiting atomic state as a result of an explicit request by a system
You can do it. Basically, the atomic state is SVA
Single-threaded access to any subpage of a space
can be used for access. If the processor has subpages atomically
gsp. nwt (
When executing the subpage acquisition, no waiting), the instruction is
Always, only if the subpage is not already in an atomic state
Complete. Thus, the atomic state on the subpage is
, can be used as a single lock. The lock is gsp.
The nwt instruction typically first places a subpage in an exclusive state.
and change the state from exclusive to atomic
Therefore, it will be done when it is completed. The lock is rsp(
Locked by executing subpage release) instruction
will be canceled. The rsp instruction indicates that a subpage is atomic.
A cache that is in a dark or transient atomic state
must be present in the queue. Local cache is
subpage, then atomically or
changes from a transient atomic state to an exclusive state
Ru. (If the subpage is transient atomic
operation becomes more complex, but the result is
It is the same on the program. )0097 Atomic state
It should be noted that is only associated with subpages.
is important. A specific running system process (typically
(user program) or has no relation to a specific cell.
. A process executes a gsp instruction and enters an atomic state.
Get the subpage located in the system software, followed by
is switched by the cell and continues execution on other cells.
It is important to ensure that That process is the second
Continue execution on the cell and ultimately resolve the subpage.
Execute the rsp command to release it. these two instructions
In between, the entire memory system has access to that subpage.
There is only a single copy, and it is either atomic or
It will be in a transient atomic state. various
When a processor executes an instruction that references a subpage,
That single valid copy moves from cell to cell. Special
A given process obtains atomic state and other processes
It is also possible to release an atomic. Atomic state is simply associated with a subpage.
additional flags that add to the data state of the subpage.
to implement protocols that use atomic state.
I can do that. Protocols implemented using only data
Just as a file can have errors, atomic
The state protocol may be defective. hardware
without STT and descriptor atomics
Using atomic state over access control imposed by
No checks are imposed on [Transient Atomic State] gsp. nwt life
An order is always completed within its limited execution time, but
(depending on the current state of the subpage in the memory system)
) may or may not persist. order
The second form of gsp. wt (subpage acquisition, waiting
Yes), but this means that subpages can be obtained in an exclusive state.
It will not complete until it changes to atomic state. gsp.
The wt instruction indicates whether the gsp instruction was successful or not.
Relieve the burden of decision-making from the programmer. processor
is gsp. When running wt, the subpage is already active.
atomic or transient atomic state.
, subpages are freed, available in local cache, and evicted.
Atomic or transient atomic
The processor will halt until the state changes to the active state. gsp.
Using the wt instruction causes the cell to wait for an opportunity to lock the lock.
Number of messages sent between caches since
can be reduced. [0100] The transient atomic state is gsp
．． to the memory system to make wt function efficiently.
more automatically used. Its use requires programmers to
It's completely transparent. Subpage is in atomic state
If another cache has gsp.gsp on that subpage. Realize wt
If the subpage is
enters a transient atomic state in the flash. If the subpage is later freed with an rsp instruction, the transaction
gent-atomic state allows you to create subpages with special solutions.
Displace interconnects that are in the open state. is releasing
The cache ignores its own state for subpages.
change it into effect. Any cache running gsp
, encounters a subpage and accepts it. Currently accepting
The cache can then complete the gsp instruction.
subpages can have transients in their cache.
enters atomic state. This behavior applies to each subsequent gs
The subpep that occurs and is evicted for p and rsp
page is not accepted by any other cache.
It continues until the point where it becomes. At that time, the key to carrying out the liberation is
The cache keeps its subpages in the disabled state (the subpages are
set when released) to exclusive state
Ru. [0101] If the CEU loads a packet with a released state,
The cache is executing a read or store instruction.
It is also possible to be accepted. The original cache is
Seeing the page accepted, delete its subpages
Leave it enabled. The cache being accepted is its C
EU and execute a single instruction before withdrawing the subpage.
row and set its own subpage state to disabled.
, sends out the subpage in a free state. load or strike
The cache that was running the release is now
is the owner of the page. As before, other caps
If the cache does not accept the data, this cache
Change subpage state to exclusive state and retain ownership
. Preferably, gsp. wt command can wait
It is good that there is no time limit. The process that issued the command is
Wait until the subpage is freed. The instructions are various
It can be interrupted by the XIU signal. such an event occurs
and the CCU attempts to obtain atomic access.
abandon. subpages are released in the meantime and other
Without a requester, the subpage is transiently atomic.
from the locked state to the free state and finally to the exclusive state
change. In typical system software operation, interrupts
is processed and the interrupted instruction is restarted, so C
The CU issues the request again. As before, it proceeds
In some cases, you may be made to wait. [State Change] This section is used to change subpage data and
We present an example with state flow. The data is owned by
The basic mechanism for moving from one cache to another
structure for instruction drawers and their other caches.
load and store instructions by the local processor
This is the execution of Different load and prefetch instructions are
, those local caches are read-on to the program.
or request to obtain exclusive ownership status.
In addition, store instructions always ensure that subpages are
Requires having an entitled status. in a certain situation
The cache is placed on the interconnection sub
You may get a read-only copy of your page. sub
The page post-store (pstst) instruction
A read-only copy of the cache in all related caches.
Communicate to Finally, the owned cache is
ownership state on the interconnect as part of recombining the
can be sent (described later). [0104] Instruction fetch and load instructions cause the station to
The partial cache requires read-only copies of subpages.
This can lead to the desired result. This request owns the subpage
The cache is responded to by the cache. Owned cache
has subpages in non-exclusive state, then requesting
provides a read-only copy to the cache of
does not change its own state. Owned caches are exclusive
If it has a subpage in the
change the page state to non-exclusive state and then read-only state.
Provide a copy to the requester. keys you own
Caches can be atomic or transient atomic.
If you have a subpage in the current state, the subpage in that state
source and invalidate its own copy. [0105] When a cache requests exclusive ownership,
The owning cache does not produce that copy of the subpage.
Ru. Once a subpage is owned non-exclusively, other keys
A read-only copy may exist in the cache.
There is a potential. All such caches are exclusive property.
Disable those read-only copies in response to a request
become [0106] Because the cache satisfies the store instruction
, if you want to get a subpage with exclusive ownership status, use
Ownership or read-only until the store order is completed.
- Do not give copies to other caches. This rule is
Readers of memory locations encounter changes in the order in which they occur.
In the memory system,
It is a strongly ordered nature. [0107] When a subpage is in an atomic state,
This state can change to a transient atomic state
but as a result of some load or store instruction,
It never changes to any other state. Some other characters
When a cache requests a subpage, its cache
Always atomic or transient atomic state
to get subpages. Subpage released to exclusive state
After the conversion between exclusive and non-exclusive states occurs again.
This is possible, but if subpages are non-exclusively owned,
A code-only copy may exist. [0108] A specific subpage is stored in a specific cache.
and is in an invalid state (i.e., the descriptor is already
, but the specific subpage does not exist.
), a copy of that subpage is available in some other cache.
Obtained at Information Transfer Level Interconnection due to request from
If possible, a cache with an invalid state will
Get a read-only copy of the page. The effectiveness of this mechanism
The result is to accelerate parallel computation. Because this
This is a request to copy a subpage from another cache.
This is because the associated latency period can be removed. The basic mechanism is simple loads and stores.
A program that uses instructions has a strongly ordered memoria
It is important to note that
Ru. The program uses certain conditions to improve its performance.
Forms of load, store, and prefetch that require state
can be used, and in many cases the compiler can
It is expected that the analysis will be carried out. However, this minute
Analysis is optional. [0110] In a simple transaction, the sub
Page atomic state is used purely as a lock.
Ru. Subpage data is not relevant. more technical
For those with a synchronization mechanism of the form, it is maintained in an atomic state.
Use the data of subpages that have been created. In one technique
, the atomic state on a subpage is
Use as a lock on data. The program is 1 or
or put multiple subpages into an atomic state and
Manipulate contents and release them. [Data copy creation strategy] Interaction between states
For example, the load instruction waits for a copy from another cache.
Time, cache space and information spent when
Transfer level bandwidth and store or gsp instructions executed
copies in other caches that are spent when
between the time and bandwidth spent disabling the
It's a compromise. There are many lead options for subpages in the system.
With a clean copy, a read can fill the local cache.
The chances of finding data that already exists increases. deer
while there is some read-only copy in the system
If the owner modifies a subpage, the owner must first
copies of them (by sending a single message)
Must be disabled. The heuristics below are simple
Multiple read/write from one read/writer access
Attempt to dynamically differentiate shares on a short-term basis. [0112] Dual read/write sharing has a high
Multiple read-only copies with locality and low
This results in write updates with sublocality. multiple copies
read-only because it is read multiple times between updates.
It is most efficient to hold peas. being changed
CEU is an exclusive-
Ownership status can be obtained. CEU is pstsp
Use instructions to signal changed data and
Distribute to participating caches. [0113] A single read/write access has a low primary
Multiple read-only copies with locality and
and write updates with high locality. The copy is
Read-only copy because it is updated multiple times between leads
It is not very efficient to maintain single lead/
Write copy (exclusive-ownership state)
does not require information transfer level operation. The strategy for balancing these considerations is as follows.
It's like this. (1) A copy of a subpage must contain information to satisfy the request.
When sent across the forwarding level, the
Copying to a subpage with a descriptor of
Any cache that does not have
Pick up a code-only copy. This mechanism is
Accelerate application with high locality references. (2) A cache with exclusive or read-only status
When a page needs to update a subpage, the subpage
Each other cache that has a copy of the
Invalidate and exclusive ownership moves to the cell being modified. strange
Cells in progress use pstsp to announce changes.
. Attempts by other caches to read the subpage are
This results in copies not being distributed to the involved caches.
obtain. [Cache Layout] Cache directory preferences
A desirable structure is shown in FIG. Reference to SVA
is done, the cache stores the information it needs.
A decision must be made as to whether or not it has. child
This selects one set in the cache and
This is accomplished by testing all descriptors of
. SVA[20:14] selects one set. general a
architecture, each disk in the selected set
Cryptor is also compared to SVA[63:21]
. In a preferred embodiment having 240 MB
, which means comparison with SVA [39:21]
. One of the elements of the set is the index for the desired page.
If it is a script, the corresponding comparator indicates alignment.
will show. Matching diary concatenated with set number
The index within the set of scripters is
1 page of the page. [0116] If one or more descriptors match, the key
The cache signals a multiple descriptor matching exception. Di
If the scripts are inconsistent, the cache
request data from the interconnect. Discount
It is possible that either the guess or the data request will be missed.
However, the cache indicates an error to CEU. SVA[20:1
4] is effectively a
This is a hash function. The system software
Hash functions give good performance in general cases
SVA addresses must be assigned accordingly. distribution
There are two important cases regarding. of a single segment
When referring to many pages, the first of many segments
This is when referring to the page. This set selector
has good caching behavior for consecutive pages
bring about. This is because 128 consecutive pages are 1
28 distinct sets. However,
However, this selector is the same as SVA[20:40].
For many pages with the same value, the hashing behavior is
not enough. The system software is
the latter state by changing the local data source in
can be avoided. For example, users for each process
Stacks can start at different segment offsets.
Wear. [Descriptor contents] The cell responds to a subpage request.
subpage data and certain descriptors.
supply the value of the data field to the local cache. response is
When returning to the requester, the requester returns these fields.
copy the code into the descriptor field (if
If it has no other valid subpages), these
Logically OR fields to descriptor fields
do. Some descriptor fields are passed to the responder.
Therefore, it is not supplied and updated by the requester.
Not even done. In a preferred embodiment, descriptor
The field is a descriptor tag defined as below.
(19 bits) Bits [39:21] of SVA. This field is specified by the corresponding descriptor.
Identifies the specific page of the SVA space that will be displayed. given
For a given set of cells in this field
must be unique among all 16 descriptors.
No. When the software creates an SVA page,
"Set" this field. (This is also
Set during cache initialization. [0120] Descriptor atomic change (1 bit
) Any subpage of this page is in atomic state.
When experiencing a conversion to or from an atomic state,
The cache sets this bit flag to 1. why
If so, was the gsp or sp instruction executed successfully?
It is et al. This also indicates whether the subpage is in an atomic state.
It is also set when changing from transient to atomic state.
will be cut. This flag is also used when gsp is missing.
is not set if rsp is missing. Because
For example, in the former case, the subpage is already in an atomic state.
, and in the latter the subpage is in an atomic state.
That's because there wasn't. This flag can be set to gsp or r
It is not set if sp is missing. Because de
This is because no scripter atomic is set.
. System software recognizes atomic state changes.
Set this flag to zero to indicate that
Ru. This field is propagated from cache to cache
be done. [0121] To the descriptor/change (1 bit) page
When some data is changed in the cache,
Set this bit flag to 1. system software
To indicate that the software has approved the changes to the page,
Set descriptor change to zero. This flag is
, set when there is no attempt to change the data
Not done. This is because descriptor/no writing is set.
This is because This field is from cache
Propagated to cache. [0122] Descriptor LRU position (4 bits)
g) The current position of the descriptor in the set is M
ost Recently Used (0) to Le
Transition to ast Recently Used (15)
The cache maintains this field when [0123] Descriptor anchor (1 bit) etc.
A request for data from the cache cannot be recognized as valid.
Also to indicate that the descriptor cannot be disabled.
, software sets this field. other keys
A read or get request from the cache is served by the requester.
It returns without answering and is treated as if the page never existed. This field allows you to create or destroy SVA pages.
The part that changes the page descriptor and the part that changes the page descriptor.
Set by system software as minutes. [0124] Descriptor/hold (1 bit) subpep
even if the page is not in the cache.
that the scripter cannot be invalidated by the cache
The software sets this field to indicate
do. No descriptor atomic (1 bit
) The cache is cached for this page's atomic state
software to prevent you from changing this field.
Set the mode. Use gsp or rsp to run
There is no attempt to do so, and the processor is notified. Processor
The server broadcasts a page atomic no exception. disk
Without Lipta Atomic, some subpages are atomic.
can be changed even if it has a lock state. child
The flag indicates that the descriptor/no write is in the data state.
The same is true for easily blocking attempts to change the
The method simplifies attempts to modify atomic state.
prevent. This field is cached from cache.
is propagated to. [0126] Descriptor/No writing (1 bit
) to prevent the local processor from modifying the page.
Software sets this field. page
There is no attempt to change it and the processor is notified. The processor signals a no page write exception. This flag can be used for exclusive or atomic/transient
To get subpages in atomic state
Does not affect caching capacity. this field
is propagated from cache to cache. Descriptor summary (3 bits) 1
Aggregate subpage state fields of a set of subpages
. One 3-bit summary for each set of subpages
- field exists. The summary is sometimes
Individual subpages for subpages within a resource set
Ignore (override) the contents of the state field
. [0128] Descriptor subpage status (4
bit) The subpage state is set in the 3-bit state field and
and the single-bit subcached state field.
Ru. This is used to record the state of each subpage, and
Any part of the subpage is placed in the CEU subcache
set by the cache to indicate whether it exists or not.
will be cut. Flags in descriptor were incorrect
may be outdated. There are two reasons for this
There is. i.e. CEU and its local CCU
and the latency between CCUs of different cells.
. In the former case, pages that have not been modified first are processed by the CPU.
This can happen when changes are made. modified sub blog
The local CCU is
, not knowing that the change happened. The latter is used by many
Each page has a description for a particular SVA page.
This can happen when you include data in one cache.
state changes that are affected by the
Not dynamically notified. [0130] There are no valid bits associated with the descriptor.
Therefore, the descriptor is always the name of the SVA page.
has a However, pointing to a specific SVA page
All cache descriptors that have the tag
must have valid subpages within their descriptors.
For example, SVA pages do not exist in the memory system. same
, the cache descriptor is set to a specific SVA page.
If the page does not have a tag that indicates
Not present in stem. Description for such page
field, but the SVA page
field has been logically destroyed.
Value is not valid. For example, a descriptor for a certain page
Consider two caches with . Cash A is
All have subpages in exclusive state, and
Cryptor/change is in clear state, other caches are
If you have no descriptor for that page
do. CEU in cell B changes subpage data.
Execute the store instruction as desired. CEU B is the local
Requires a subpage with exclusive ownership state from the cache
seek The cache allocates a descriptor for the page.
guess, then use the ring to request the subpage. Owner (A) responds by granting exclusive ownership to cell B.
Ru. After the subpage arrives, cell B
Copy cryptor changes (in cleared state). One
Then, B's CEU extracts the subblock from the subpage.
Load that data sub-cache and load that sub-block
change the In this regard, the CEU subcache is
, which indicates that the subblock has been modified.
, the local cache still shows the subpage as unchanged.
vinegar. At some later point, CEU B
sends sub-block data from the cache to the local cache
. This means that CEU B can use subcache for other pages.
If the CPU requires block blocking or the CPU has been changed
An idle cycle is used to write back the block.
using or some other cell requested a subpage
It can happen because of this. Next, the cell B cache contains the descriptor/change flag.
setting. During this time, the descriptor
Furthermore, it is in a clear state on cell A. As a second example, a system running on cell A
If the system software destroys the SVA page here
Assume. Page is exclusive in cache A
Collect all subpages in , and then create SVA
of A so that the page no longer has valid subpages.
Destroyed by changing the descriptor. deer
However, cache B still has the data for that page.
Has a scripter. Files like descriptors and changes
is meaningless. Some other caches followed by SV
Even after re-creating the A page, the cache B cache
The page should remain the same until the first subpage arrives.
cormorant. [0133] The system software uses descriptor information.
When trying to use information, the SVA page is
Must ensure that the memory system exists
. One way to accomplish this is to always set the page anchor to
and enable at least one local cache.
is to get subpages. Changes and atomic changes
be absolutely sure that no change fields are set.
In order to
You have to get the page. The anchor is either
Asynchronously cache other subpages that have already been obtained
prevent them from being acquired. When operation is complete, the system
The system software is a desk in local cache.
Clear Ripta Anchor. At that time, the page
Another cache request for a subpage of
It will be done. [0134] System software also creates a page
Make sure the SVA page truly exists in the memory system before
It is necessary to ensure that this is not the case. As mentioned above
, the mere existence of a descriptor with the correct tag value is
, SVA pages actually exist in the memory system.
Do not instruct. The software sets page anchors.
and then retrieve subpages with exclusive status.
The non-existence can be confirmed by trying. in the drawer
If successful, the software will lose the competition and the page will be left in memory.
exists within the system. If not, the software
software can create pages using the mpdw command,
SVA pager for all pages that are exclusively owned
Set the dress. The simultaneous use of mpdw for this purpose
There is a software interlock for
Note that this is still necessary. Cache Descriptor Usage and Replacement: Example
The system 10 cache is a multi-level storage system.
Can be used as part of system software. child
In some types of systems, physical memory is
multiplexing across large address spaces with
be done. Caching is done by software using SVA pages
Moves data between cache and secondary memory in units of
Features that accelerate the implementation of multilevel memory systems
have [0136] All caches are stored together in the system.
Configure primary memory. However, for a certain purpose
consider each individual cache as an independent primary store.
It is necessary to This means that each cache has a limited number of
This is because only SVA pages can be held. i.e.
, 2048 pages in each cache, any particular set
That's 16. Several ways to balance cache usage
There are automatic and manual mechanisms. [0137] Each cache has access to all existing pages.
to maintain LRU status. LRU data is
For each of the 128 sets of scripter associative memories
are maintained separately and their approximate last reference time is
There are 16 pages in one set. Each cache has disk drives within each set.
Maintain the LRU-MRU ordering of the printer. The order setting is
,descriptor. Maintained with LRU priority. 1 set
Each descriptor in the list is a descriptor. LRU
Priority has a value of 0 (MUR) to 15 (LRU)
. Conceptually, when a page is referenced, it is MR
U and old L of the page referenced from MRU
All pages leading to RU priority are then directed to LRU
Move one step. The descriptor has the following behavior:
It is made into MRU. That is, (1) subcache
Any load from the local CEU, including an increase in state strength.
In de. (2) With any store from the local CEU. (3) Any local CEU that does not store subcache
(4) XCACH operation (cache is local CEU
requests to change the subcache state) followed by
hand. (5) After local CEU allocation from subcache
. [0139] The CEU instruction resides in the local cache.
SVA page not present (in invalid-descriptor state)
may be referred to. The cache is descriptorized as shown below.
must be allocated and then assigned by CEU.
the interconnect for the specific subpage requested.
issue a request. If the corresponding page exists somewhere in the system, the request
The cache in
Cryptor fields and referenced subpage data
Copy. Finally, assign the descriptor
This process fills the elements of a particular cache set.
Tasu. [0140] Each cache has
Changing an SVA page to invalid-descriptor state
The ability to automatically reuse certain descriptors by
have power. As a background activity, cash
The cache also automatically sends owned subpages to other caches.
Move dynamically. All of these automatic actions are
entrained or disabled by system software, and
descriptor. Retention and/or descriptor.
Suppressed when the anchor is set. The following theory is
Cache descriptor correction and background
Describes the activities of movement of managed data. [0141] Occasionally a cache with no valid subpages
one or more descriptors exist in the set
Sometimes. This situation is caused by other caches.
or as a result of recombination activities (discussed later).
can occur as a result of For example, cache data
Suppose the scriptor has only one valid subpage.
Set. In this case, the cache descriptor is exclusive
Has a state. Some other cache owns the subpage
When you request the right, this cache
You no longer have the page. Moshi descriptor. Retention
and descriptor. Anchor is attached to this cache.
When the descriptor is in the clear state, the CE
U is invalid for the same set of caches in this cache.
Reuse when referencing some other page with state
can be done. [0142] The subcache is stored in the subcache.
Provided that the cache is not read-on
Pages with all pages in a read or disabled state (lead
Only Page) will be automatically dropped. This is a memory system
When a system destroys a read-only copy, the information is memorized.
This is possible because it will not be lost due to the resystem. Cash
All copies are removed according to the LRU order setting.
Physically disable or disable a partial range of disks.
It has the option of limiting it to lipta. [0143] A cache is fully owned in some exclusive ownership state.
It has a page and a descriptor. Changes and descriptions
Ta. Atomic A page with changes cleared
drop automatically. Cache has exclusive ownership of all subpages
The fact that other caches have ownership
That is, if you do not have a copy of the page with data state,
The cache is not allowed to communicate with any other cache.
guarantees that the data state will not be destroyed. discreet
Puta. Changes and descriptors. atomic change
The fact that both are in the clear state indicates that the data or
is an atomic state change (as a result of the gsp.wt instruction
From atomic state to transient atomic state
(including conversion) has occurred. This is S.V.
A: Was the page created by system software?
It happens because it was polled last. memory system
, atomic state and page data on secondary memory
Assuming you have a copy, and this is the SV
A Used to recreate a page and destroy it
can. I set the cache to LRU Jun order.
Is it possible to completely disable pure page shedding?
in the form of restricting this to a subrange of the descriptor.
Have a choice. The system software is
If the page is in a transient atomic state, the
Scripter. Atomic Changes are never made asynchronously
It was noted that it should not be cleared. [0144] Descriptor. Retention settings are individual
does not guarantee that a page exists in the local cache
Please note that. In addition, you can also
Scripter. Simply setting the retention
does not prevent users from destroying the page. system software
The hardware automatically drops pure pages.
Explicit action must be taken to prevent
Scripter. set changes). [0145] Reassociation means that owned subpages are cached.
cache to the interconnect and owned by other caches.
It is a movement that gives an opportunity to accept the state of authority.
. The receiving cache is
Should already have a descriptor assigned
and the cache contains the subpages that are being recombined
Assign a descriptor to accept ownership of
do not have. The purpose of page recombination is to assign pages to a specific SVA.
The goal is to reduce the total number of descriptors that can be used. [0146] The cache uses
A rejoin message is issued for this purpose. Reunion message
, does not find any other cache to take over that page
, the rejoining cache retains the data. actually
turns out to be itself the goal of recombination. ownership by some other cache (this is non-exclusive, exclusive)
, atomic or transient atomic state.
), the issuing cache will be
, changes its subpage state to disabled. [0147] The cache is memory refreshed.
Make the subpage a background activity while
automatically tries to rejoin. During each refresh interval
, the cache tests a particular set and finds an acceptable data
search for a scripter. The descriptor is
must not have any subpages stored in the
must have a subpage and exclusive ownership of all subpages
shall not be held in a state of entitlement. A page like this is the headline
cache for some owned subpage.
and issue a rejoin message. Cache is LR
U Perform background recombination globally according to order settings.
or add it to a partial range descriptor.
You have a choice of restricting or constructing. background re
Join causes cache but entire line error
Instead, the newly referenced SVA page is
increase the likelihood of being able to assign
Ru. [0148] CEU also requires that the system software
, you can try to eliminate owned subpages.
provide an instruction. Subpages are stored in subcache
should not be done, but the cache attempts to drive out ownership.
No other constraints are imposed before the [0149] The pages below the working set point are
Since there is little chance that it will be referenced, it is necessary to reconnect the data to actually move it.
In most cases, data is retrieved from a cell that does not refer to data.
Move it to the referencing cell. [0150] If a new descriptor in the set is needed.
When the cache finds a useful descriptor
Step through as many of the operations below as needed to
do. That is, (1) Find an invalid descriptor. (2) Disable read-only copy. (3) Destroy the pure SVA page. (4) Allocating a descriptor by the means described above.
If this is not possible, a lineful exception will be signaled. The individual steps are explained below. Find invalid descriptors. If invalid
If a descriptor exists, it can be used immediately. This requires the following conditions: i.e. - all the
If the page is in an invalid state and the descriptor is
and descriptor anchor are both cleared
be. - A subpage of a page is described by a PRT entry.
Not yet. [0153] Disable read-only copy. if
Also ctl$cculru config. cde
If is 1, the cache is read-only for subpages.
A descriptor containing only a copy is considered to be an identifying use. tree
The cache is waiting for a page with the following conditions:
Search for RU or MRU. - All pages are in read-only or invalid state. - There are no subcached subpages. -ctl$ccu lru config. cdl
LRU value equal to or greater than . −Descriptor retention and descriptor anchor
Both are in clear condition. - A subpage of a page is described by a PRT entry.
Not yet. If an acceptable descriptor is found
, all subpages are changed to an invalid state and their
descriptor is used. Drop pure SVA ctl$ccu lru config. pde
is 1, the cache can be destroyed (memory system
SVA pages (to be completely removed from the system)
try Caching is performed on pages with the following conditions:
Search for LRU or MRU while waiting. −
All pages are in (various) exclusive ownership states. - There are no subpages stored in the subcache. - Descriptor changes and descriptor atomic changes
Both changes are in clear condition. -ctl$ccu lru config. cdl
LRU value equal to or greater than . −Descriptor retention and descriptor anchor
Both are in clear condition. - A subpage of a page is described by a PRT entry.
Not yet. If an acceptable descriptor is found
, all subpages are changed to disabled state (it
), and that desk
Lipta is used. [0157] Line full exception (all line exception) occurs.
In order to reduce the possibility of
Try to reduce its ownership of subpages within the page that are not
shall be. These operations are similar to descriptor allocation operations.
Unrelated, occurs during RAM refresh. [0158] Moshi ctl$ccu lru conf
igu. When bre is set, the CCU
Search from LRU while waiting for a page that meets the conditions
. - A subpage that is in ownership status. - Certain subpages that are not in exclusive ownership status. - There are no subpages stored in the subcache. -ctl$ccu lru config, ble etc.
LRU value greater than or equal to . -Descriptor. Retention and descriptors. anchor
Both are in clear condition. - A subpage of a page is described by a PRT entry.
Not done. An acceptable descriptor is found
, the cache issues a reassociation message to the interconnect
do. [0160] The system software can
monitor the LRU behavior of pages within the cache and
A working setpoint can be set on the line. low
Descriptors with LRU values are in the working set.
descriptors with high LRU are
Not in Kingset. Determine working set point
descriptor tag, LRU value and sub
Iterative testing of page states is available. Change (or Atomic Change) Page
leaves the logical working set, the system software
descriptors will be reassignable in the near future.
It is possible to take actions such as purifying the page so that the [0162] Comparatives where the descriptor is in ownership state
Keeping a small number of subpages allows the software to
Using the csp (subpage recombination) instruction, these
attempt to rejoin subpages of to other caches. Otherwise, get the whole SVA page and pure
could be transformed or destroyed. [0163] When the working set changes, the system
The software controls the cache configuration parameters
can be changed. Pure page drop, copy drop and backlog
The parameters for background recombination are
software behavior consistent with software working set policy.
can be modified to ensure that the A typical use of secondary memory is for each SVA
has a corresponding page allocated in secondary memory,
The cache storage model provided by the hardware
Expand. A page initially exists only in secondary memory
, cached in memory when it is referenced by a program.
is memorized. changes while the page is in memory
(data state or atomic state), the second
A copy of the page in next memory is
memory system pages for other SVAs.
It must be updated before it can be used. Such changes shall
descriptor. Changes and descriptors. Atomy
Can be detected by change field. secondary memory
The act of updating is called "purifying" the SVA page.
be done. System software is usually a working
Since the SVA below the cut point is purified, the cut point is
Cache space is quickly allocated to other SVA pages.
Becomes available. [0165] Only some cells in the system have SV
A disk drive that provides secondary memory for pages
have a physical connection to Eve. Appropriate input/output cells
must be able to obtain page data during I/O operations.
Must be. System software issues I/O instructions.
Allocate a descriptor on the I/O cell before issuing it.
This can be ensured by applying and holding. Purification
After the system software completes, the system software
Ta. Changes and descriptors. atomic change
Clearing lag or destroying SVA pages
I can do that. The actual protocol used is the system
programmatically accesses the page during the purification attempt.
further complexity depends on whether it is possible to
There is. [0166] In general, system software
Unless the system is prevented from destroying the page.
One of the subpages is in a transient atomic state
descriptor if it has. atomic change
Do not clear it. For example, all descriptors are
or if the disk has the flag set
Crypter. If the change is set, the memory system
will not destroy the page. [0167] A particular set of a particular cache is in a full state.
When the software is in a
There is no reason to assume that the system is reasonably full. Thus, the software can select a page from the set.
to the corresponding set in the other cache.
It is desirable to respond with a full set. [0168] In order to use memory efficiently, software
The appropriate pages to be removed from the full set,
An appropriate target cache for that page (if any)
) must use some strategy to identify
. Caching is some kind of strategy for this page replacement
be prepared to promote For exchange within a set
To facilitate selection by the software of the pages of
The cache stores pages in the most recently used (
MRU) to the least recently used (L
RU). When a page is referenced
, it is moved to the MRU. Then other pages
When referenced, it ages towards the LRU. L
RU information replaces the most recently used pages
Accelerate strategies to increase growth. [Processor data access] The processor accesses the
and store instructions and co-execution unit operations.
Therefore, a data request is made to that local cache. Cat
request from its local processor, and the processor:
invalidates that copy of the subpage in the subcache
let [Load and store instructions] Including the referenced address
sub-cache with requested sub-blocks.
When not present, the processor executes load and store instructions.
Pass the command as a request to the local cache. different formats
The read and store instructions follow the instruction access pattern below.
Passes information about the event to the local cache. For example, the command
is a load followed by a store, and the data
The subpage containing the item is still in the local cache.
If not present, you will get read-only for load commands.
Take ownership of the load and then use it at other times.
The point communicates through the information transfer level to the store.
It is more efficient to obtain voting rights. [0171] Status of subblock in subcache
The state is the state of the corresponding subpage in the cache.
does not necessarily reflect the The instruction subcache is always
Get a read-only copy of your data. data sub-cabin
A sub-brochure can be read-only or exclusive.
can hold the lock. A subcache is an exclusive ownership letter.
and a descriptor. No write is set
It can have exclusive status only when it does not. sub cache
is exclusive, atomic and transient atomic.
does not differentiate between subpage states. subcache is supported
With the block in exclusive state, CEU is simply
Store commands can be executed simply by putting new data into the subcache.
It can be executed. st64. All store life except nsc
If a subblock is stored in a subcache,
If not specified, or invalid or read-only.
Having no state, CEU completes the store instruction.
must request exclusive status before. Hello
Scripter. No write is set or subpage
A failure occurs if the page is not present in the memory system. [0172] Subpage request arrives from another cache
The owning cache must then respond. too
If any part of the subpage is stored in the data subcache
local cache only exists in subcaches.
Guaranteed to get any changes that may exist
There must be. Cache also requires CEU
Depending on the request, the sub-cache state for the sub-block is
Change the status to read-only or disabled. a certain place
If the instruction subcache is
to disable that read-only copy of the page.
Guarantee. [0173] In addition, the subcache management unit (block
(locks and subblocks) and cache management unit.
It is important to distinguish between pages and subpages.
It is. Data is stored in sub-blocks in CEU and its
Move between local caches. The data is also
to move between caches. 2 per unit subpage
There are two sub-blocks. [0174] About the different forms of load and store instructions
The details are described below. Each description summarizes the meaning of the instruction
An overview of subcaches and cache behavior, starting with
continues. Load (Read Only) [1d. ro
] Load 64 (read only, subcache recording
memory) [ld64. ro. sc] Program reads data
Continue the pattern. The least amount of work is getting the data.
It will be done. If the containing subblock is subcache storage
then it is used directly. Local cache
If the page has no subpages, the local cache will copy
get. Local caches can be exclusive or read-only, as appropriate.
Supplying subblocks to the subcache in the only state
Ru. Load (exclusive) [ld. ex] load
64 (exclusive, subcaching) [ld64. ex
．． sc] The program writes a subblock using the following command.
imbedded, and the exclusive state is preferable to any other state
. When the data is expected to have few shares,
or when a series of writes was occurring.
system uses this. This means that CEU has changed the data.
Reduces the number of interconnect messages required before
Cheating. A specific example of the use of load (exclusive) is the stack
This is data for each program. Generally, it takes
There is no read-only copy of data. Because, Yui
One copy is for use by the program.
This is because that. However, if one program
If you move from one processor to another, the new
The processor's local cache has no copy and is stale.
The processor's local cache exclusively stores subpages.
Keep it in a vested state. If the program is (read-only)
) When using a load, the local cache
page in read-only state (subpages are
An atomic or transient atomic state that results in
(unless it's in a mic state). Subsequent stores are some C
Caching before EU data changes can occur
make other interconnection requests (exclusively
to gain voting status). ld. As in the case of ro
, the minimum amount of work is done to obtain the data. If
, if the subblock already exists in the subcache,
It is used directly. If the local cache is
If the local cache does not have a subpage, the local cache
to request exclusive ownership of. Local cache is sub
If it has a page, the sub-block can be read-on as appropriate.
supplied to CEU in exclusive or exclusive state. Store [st] Store 64 (Sub-cache) [st64. sc
] If the subblock is already in the exclusive state and the subblock
cache, the subcache state remains unchanged.
, the data is written to the subcache. sub cap
The block must have subblocks in exclusive state.
do not have. Is the subcache a local cache when needed?
requests exclusive status from the local cache, and the local cache
Request exclusive ownership status from a connection. Moshi Desk
If the repter no write flag is set, an error will occur.
Example where CEU is notified and CEU does not write a page
Generate outside. Otherwise, the subcache is
Obtain subblock in other state, data is subcache
will be written to. 0178] Load 64 (read only, non-sub
caching) [ld64. ro. nsc] load
64 (exclusive, non-subcache) [ld64
．． ex. nsc] Programmer writes for ld
Exclusive and exclusive according to the expected reference pattern, as
and use read-only instructions. However,
The number of references to the block is expected to be small, and
The subcache must not be disturbed during this data retrieval.
do not have. If the data exists in the subcache, it
is used directly. Local cache stores subpages
If not, the local cache gets a copy. CEU
gets a copy of the data and loads the instruction register
. Store 64 (non-sub-cache)
[st64. nsc] The number of references to the subblock is predicted to be small (
Typically 1), and the subcache stores this data.
must not be disturbed during memory. If the sub-block
If it is stored in the sub cache in an exclusive state, the sub
Cache state remains unchanged, data remains in subcache
will be written to. If the subpage is read-only
If the subpage is stored in the subcache in
Deactivated immediately. The CPU stores data in a local cache.
supply to Shu. The cache is subdivided with exclusive ownership.
If you don't have the page, request it from the interconnect
. If the descriptor no write flag is set, an error occurs.
is notified to CEU, and CEU does not write the page.
throws an exception. If not, the CEU data is
Written directly to a subpage of the cache. [Instruction fetch] Instruction fetch is always read-only.
– Pull out a subpage that specifies the state. [Subpage atomic state instruction] Subpage atomic state instruction
The lock state instructions are the protocols for the acquire and release operations described above.
gram interface. These instructions are parallel
Available in several formats to allow precise adjustment of the program.
exist. [0182] Subpage acquisition [gsp. nwt] sub
Page acquisition/waiting [gsp/wt] Subpage acquisition
indicates that the subpage should be set in an atomic state.
and request. For both forms of subpage acquisition commands,
If a subcache is atomic to any cache
If it does not exist in the state, the local cache will atomically remove it.
Acquire in the locked state. gsp. For nwt, @ME
The M status code indicates the success or failure of the attempt, and the instruction
, the trap option is present in the instruction and the subpage is
If it is already atomic, trap without changing @MEM
be done. gsp. The wt instruction makes subpages atomic.
CEUs in cache until can be earned in state
stop it. This is before the program can proceed.
If you have to obtain atomic state in the interconnect
Reduce the amount of traffic. If the subpage is one of the keys
cache (including local cache)
If the subpage is freed, the instruction is
wait. The local cache then atomicizes the subpage.
Acquired in a closed state. @MEM state always indicates success
will be changed so that [0183] Subpage release [rsp] Subpage solution
release is used to remove a subpage from atomic state.
used. If the subpage exists in the local cache
If not, it is first requested via the interconnect.
Ru. Once the local cache has exclusive ownership, r
sp progresses. If the subpage is in atomic state
If not, subpage release does not change the subpage state.
stomach. In this situation, if the trap modifier
If present for the command, the CRU is trapped. too
If a subpage is in an atomic state, it is exclusive
can be changed to a certain state. Moshi subpage transient
If it is in an atomic state, it can be changed to an exclusive state.
, so that waiting cells can acquire atomic state.
Driven to the interconnect. [Other subpage instructions] Subpage poststore [ps
tsp] Subpage poststore is in the program,
Drive read-only copies of subpages to interconnects
let everything that has a descriptor for that page
The cache takes a copy of the data. This command is
Used to send data as part of completing an action.
This means that some other cache may store the data.
When you need to use it, there is a read requirement on the interconnect.
reduce the possibility of having to make demands. [0185] Subpage prefetch [pcsp] sub
Page prefetching allows copies of subpages to be
request to be retrieved in local cache in state
do. Instructions may require read-only or exclusive status
. Subsequent references to subpages are
blocked until the patch is completed. [“Manual” control of the memory system] As mentioned above
, the memory system automatically shares data and LR
U Designed to direct maintenance to the virtual memory system.
It is. However, the software is
can take explicit control of the memory system. [0187] In normal operation, all processors
A. Space is shared and data is shared between instructions (and control operations).
automatically move from cache to cache in response to
move. The software uses a portion of memory on cache
or all can be dedicated to its local non-shared use. child
This type of system allocates SVA space between caches.
partition, moving such data from cache to cache.
Explicit control operations must be used to activate the The system software writes a descriptor to each descriptor.
By setting the data retention, the cache
Move or destroy pages to make room for other pages.
You can prevent this from happening. At that time, the system software
hardware is required to multiplex each cache memory.
handle the exception or explicitly destroy it according to
Can be carried out. In automatic mode, the memory system
, may be configured as a shared memory multiprocessor. Memory system when various automatic features are disabled
simulates a more loosely coupled message-oriented architecture
It can be configured to: The message is sent to a special SVA range.
It can be passed by referencing the enclosure. Manual control of the memory system
is used to more closely enforce a particular memory model.
can. [Memory system control instruction] The control operation is performed by an example of a processor.
For example, 40A can directly manipulate the memory system.
enable. There are two classes of control instructions. Sunawa
These are data movement and page state control. data transfer
Dynamic control instructions are used to control pages and pages of data in the system.
Cache to cache in subpage hierarchy
Moving. Page state control instructions are page descriptors
operate. CEU commands can be synchronous or
or cause cache directives to be executed asynchronously. CEU cache instruction in progress, cache PRT
occupies one entry in (hardware table)
. PRT has 4 entries, so up to 4
Cache instructions may be executed in parallel. Most CE
U Instructions remain in use until their requirements are satisfied
Assignment of one PRT entry to provide periodic aspects
receive. For example, load/store instructions are executed synchronously.
Exceptions to certain software controls (missing pages)
or unwritable pages) in a predictable manner.
I can solve it. pcsp (cache subpage
refetch) and pstsp (subpage post
−store) instructions as described in the following sections.
It works asynchronously. Synchronous errors are usually tracked by the CEU.
result in executing the push sequence. Is the asynchronous error due to actual hardware?
or requests from some other cache.
caused by This type of error occurs when the memory system
Reported by system interrupt. [Prefetch instruction] The prefetch instruction is a subpage
A copy of is retrieved on the local cache in a specific state.
request what should be done. pcsp prints subpage
Refetch. The cache is
Allocate one PRT entry. subpage
If already exists, the PRT entry is freed.
pcsp is completed. If not, cache
issues a request and then instructs CEU to complete the order.
. This proceeds asynchronously. Message is a request or response
, the cache accepts the data (if it exists)
) and frees the PRT entry. C.E.
There is no indication to U that the data has arrived. [Subpage post-store instruction] The pstsp instruction is
, copies of the subpages are circulated on the interconnect, and
A key with a descriptor for the page contained by
cache gets read-only copies of subpages
Request what you should get. pstsp is
Reference subblocks within subpages. sub block
is stored in the subcache in an exclusive state, and the
When modified in the cache, the CEU is
request poststore operations from the host. If not
If so, the pstsp instruction has no effect. cache
allocates PRT entries and removes subpenetrations from CEU.
request page data. Then the cache is posted
- Present the store message to the interconnect and the PRT
release the entry and instruct CEU to complete the command.
do. CEU proceeds asynchronously. The message is
When the cache is returned to, it is discarded. [Subpage fetch instruction] The mfsva instruction is
system software to make subpages read-only or read-only.
is imported with exclusive ownership, and the subpage's S
VA Specify the location. This allows the software to
, configure the DSTT conversion as required by pcsp
This will save you the effort of doing so. [Sub-cached subpage flush instruction] mfl
The sp instruction specifies that the specified subpage is in the local CEU.
The subcache is not stored in the cache.
Guarantee. If subpage is invalid - descriptor
state or disabled state, the descriptor is assigned
the subpage is not requested via the interconnect
. [Subpage recombination instruction] The mrcsp instruction
Stem software moves ownership to other caches
activity disk for a page by
The number of ports can be reduced. cache background
Unlike the round reassociation active state, this instruction
not controlled by shape parameters. [0198] The page state control instruction is the SVA space
works on individual pages. [Descriptor anchor instruction] The mpsa instruction is an SVA
Desk with moored to local cache for pages
Provide lipta. If the descriptor is before mpsa
If it already exists, its anchor flag will be set.
It will be done. If not, the cache uses the descriptor
Distribute and then set the anchor flag. page form
The state control behavior is
Requires that the cipher should reside on the local cache
do. [Descriptor write instruction] The mpdw instruction is an SVA
Create and destroy pages, and decrypt existing SVA pages.
Used to change scripter flags. mpdw is
, the system software first uses mpsa to
Get the tethered descriptor for that page
Requires. The discussion below is based on the tethered descriptor
Assume that the file exists on the local cache. [Creating an SVA page] Following mpsa, create a desk script.
page exists, but all pages are in an invalid state. system
The system software ensures that all subpage states are set exclusively.
Run mpdw which specifies what should be done. to this
, a message is sent to the interconnect, which causes
Members of the ring involved become aware of the creation of the page
be able to do so. [0202] There is an SVA page here, but its
Data values are not limited. The software allows the user to
Perform a store instruction or I/O before referencing the page.
You must initialize the page using
stomach. For this reason, software is usually
The page at the SVA location where the program cannot be accessed.
create, initialize the page data, and then
Change the address of the SVA page as described in
Ru. The page executes an mpdw command that clears the anchor.
be released for general use. [SVA page destruction] After mpsa, system software
software must obtain all subpages in an exclusive state.
do not have. This is done using the mfsva instruction. Then,
The software changes all subpages to an invalid state.
Execute the mpdw instruction that specifies what to do. this command
The message is sent to the interconnect and the related
Make ring members aware of page destruction. S
The VA page is destroyed by this operation. software
The software runs a second mpdw that clears the anchor.
free the descriptor for reuse by
. [Descriptor field change] The mpdw command
used to change various fields of the part descriptor
be done. This means no changes, no atomic changes, no writes,
No atomic and set or clear retained fields
and clear the anchor field. mpdw is also associated with tags and therefore descriptors
The SVA space address can be changed. (Dis
Cryptor index forms part of SVA
, the new tag is by definition in the same cache set
. ) [0205] To guarantee the consistency of the memory system,
In order to
Certain rules must be followed when changing a field or tag.
Ranu. mpdw has descriptor anchor set
(The command itself is a discreet
May bring Kriya of Ptah Ankar
Although not). Various sequences have all subpages exclusive
Requires ownership state to be in local cache
. This creates a descriptor anchor for each subpage.
and mfsva. By setting ex
It is carried out. The various sequences show that all subpages
The subcache is not stored in the local cache.
need something good. This provides a subcabinet to the local CPU.
for each subpage that may be stored
This is accomplished by running mflsp. (
mfsva. Executing the ex will tell you which subpages
It is also stored in subcache by CEU of other cells.
We guarantee that you have not. )0206] List below
gives valid constraints for each flag and tag.
Ru. (1) Anchor is set and (usually) assigned
as part of the desired descriptor tag or flag change.
Reared. It stays in the set state for an arbitrary duration.
However, this is not possible in shared memory systems.
It will be cleared as soon as possible. (2) Retention is performed on a specific cell without any constraints.
A descriptor can be modified to hold or release a hold.
Ru. (3) Atomic changes and atomic
The change is that all subpages are in the local cache.
requires that it be in exclusive ownership status in
. (4) Clear changes and set no writing
This means that all subpages are supported in the local cache.
Requires that the book is not cached. this
If the local subcache evicts any subblock,
does not have any other status and does not have any modified sub-blocks.
We guarantee that the Change no modified write
When the change occurs, the system software
Must be recognized by all cells that refer to that page.
You can decide whether or not to do so. To make a wide-scale change, you need to
page is in exclusive ownership state in the local cache.
Need what should be. The system software is
Normally, when clearing a changed flag, you do not make a global change.
vinegar. To make local changes, make sure that no subpage has an exclusive location.
Does not require being in an entitled state. however
, which results in a delay in the recognition of the new state. (5) Change the SVA page by changing the tag.
To change the number of pages, all subpages must have exclusive ownership.
state and are not stored in the subcache in the executing cell
It requires that. [0212] Modification of a single bit field can be performed using a single m
pdw. Performed by the desc command. This command
new values for flags, old values for other flags, and
Contains tags. System software mooring page
unless there is a special reason to maintain the anchor
Clear the flag. [0213] Change the number of SVA pages of the descriptor
What to do is destroy the old page and then restore it with the same data
This is logically the same as creating a new page that may
be. The sequence is as follows. (1) Disk script for old SVA page
moor the page and get each subpage in exclusive ownership status
. Any subpage is atomic or transient
If it has an atomic state, it is a running cell.
be obtained. Once all subpages are retrieved, the old SV
Accessing A results in a dropped page failure. (2) Determining the atomic state of each subpage
Fixed. This is gsp.for each subpage. Realize nwt
and test the @MEM indicator obtained.
Therefore, it is carried out most quickly. Old SVA subpage
gsp. Cells that are already running wt are
extremely resulting in a timer interruption and gsp. wt is
When resumed, results in a dropped page failure. (3) To change all subpages to invalid state
Mempdw. Use alli. This instruction is executed by the local CCU
local C that the SVA page is being destroyed.
Notify IU and RRC (if required)
. Even if all subpages are changed to invalid state, the data is
Stays in local CCU. (4) Set the tag and set flag to the desired state.
mpdw. Use desc. New anchor
– flag must be set. (5) Change all subpages to exclusive status
Because mpdw. Use allx. This instruction
An SVA page is being created in the CCU.
to local CIU and RRC (if required)
urge The old data is now recognized as being in an exclusive state.
be done. (6) Saved atomicity of each subpage
recovery from a locked state. For each subpage that was saved
, gsp. Published nwt. (7) m to clear the anchor flag
pdw. Use desc. [0221] Descriptor. For use without writing,
Including. i.e. of inadvertent modification of certain data.
Prevention, copy-on-write/copy-on-access protocols
Support, debugger monitoring point. In the first case, no writing
is set and remains set. In the second case, the pro
When Gram tries to change the page, the system software
The software makes copies of pages available to other users.
and then clear the no write flag to respond.
Wear. The software can handle this change locally or globally.
It can be done. In the former case, other pages that refer to the page
No write failures will continue to occur on the file. Finally, Deva
A guard point is a specific point in the context address space.
Detect changes in space, e.g. when a global variable is destroyed
The intention is to find out where there is. system software
software sets no writes for the page,
Enforce this by trapping each modification attempt
. For changes outside the scope of monitoring, the software
Moor pages, clear no writes, change data
and ejects the data from the subcache and writes no writes.
Set and proceed. Global for no write
Implement watchpoint support by making changes.
I can do that. [Page Local Discovery - LRU Lookup Instruction] m
The fpl instruction specifies the cache's LRU space.
search for a set of discs that meet a specific set of criteria.
Seek Crypta. The search began at LRU location 15.
Starts with a descriptor and progresses upward until it passes the criteria
do. [Instruction and data system address space division] Correct
To ensure correct behavior, the cache should be
We also need to know if the page exists in CEU.
. This allows the cache to
A request from a local DEU causes a subpage state change.
requesting subcache invalidation when requesting
I can do it. [0224] As part of this mechanism, the CEU
When changing the cache storage state, the cache and communication
believe However, the cache is subcache
Do not maintain per-time information. As a result, the SVA space
The same subpage appears in both subcaches at the same time.
There shouldn't be any. Generally, this means that the same SVA region
A system that cannot be used as both instructions and data.
system software. Self-modifying program
That is, the code and data are in the same context address set.
Programs that are part of a program are not supported. [0225] The system software is special in the following cases.
care must be taken. (1) Breakpoint
When modifying an instruction, such as when inserting or removing
. (2) Trap analysis or program using a debugger
Reading instructions as part of a disassembly operation. (3) Life
Reading a page from an I/O device that is a command page
. [0226] To read instructions as data, the system
The software must perform the following actions: (1) Configure DSTT entry to write SVA
. (2) Check that the subpage is not in the instruction subcache
Guaranteed (using mflsp). (3) As data
(using 1d64.nsc). (4
) DSTT entry invalidation. Instruction subpage with data
In order to write the
work must be done. (1) Configure DSTT entry to write SVA
. (2) Subpage exists in every instruction subcache
(mps to moor the page)
a and all other caches and subcaches.
mfsva.mfsva. ex
). (3) Extract the containing subblock
(Using 1d64.nsc). (4) Change the subblock and write the instruction as data
Enter (st64.nsc). (5) Release page mooring
. (6) Invalidate DSTT entry. [0227] Instruction pages are usually pure and system S
As part of VA space management, SVA space?
does not need to be written to the I/O device from
. Before writing the instruction page, the system software
You must perform the following actions. (1) The subpage
Guarantees that it is not present in any subcache (page
use mpsa to moor the cage and all other
Disable subpages in caches and subcaches
mfsva. (using ex). This cell is this
If the page never runs, this step
is not required. (2) Perform I/O. (3) Pe
ensure that the page is not present in the data cache (
mflsp). This cell has this instruction page
This step is necessary if you never perform
Not considered. (4) Unmoor the page. [0228] SV the instruction page from the I/O device.
A. When reading into a space, the system software
The following actions must be taken. (1) Create a page
(use mpsa to allocate and anchor pages)
, use mpdw to complete page creation)
. (2) Perform I/O. (3) The page is a data server.
ensure that it does not exist in the bookcache (mfls
using p). This cell executes this page of instructions.
If this is never the case, this step is not needed.
stomach. (4) Clear the descriptor change flag and sub
Other descriptor attributes like page atomic state
Set the property and descriptor/no write. (
5) Unmoor the page. [0229] RRC Organization and Data Structure: Structured according to the present invention
The preferred RRCs performed are each on a single sub-ring.
Organized into two independent banks that are connected. 1-4
Banks of RRC have low-order page addresses and alternating
Interleaved placement based on the degree of configuration of the placement
). Interleaving is a system
statically configured during system configuration. Ring: Connected to 0
The connected RRC is called RRC:0 and is connected to Ring:1.
The connected RRC is called RRC:1. [0230] Single ring: For 1 form, RRC: 0 or
and RRC:1 based on SVA [14]
It has been interleafed. Figure 19a shows one cost
It depicts the preferred form. [0231] Double ring with one RRC:0: type 1
(TwoRing: 1/1), a single RRC:
0 is interleaved based on SVA [14],
Two rings: 1 RRC based on SVA[15:14]
It is then interleafed. Figure 19B is one preferred
It depicts the form it takes. [0232] Two Rs
Two Ring with RC: 0: One form (TwoRing
:1/2), RRC:0 is SVA[15:14
] and the two RRC:1 are interleaved based on S
Interleaved based on VA[15:14]. No.
Figure 19C depicts one such preferred form. [0233] For 4-ring:1 configuration, 2 RRCs:
0 is interleaved based on SVA[15:14]
, 4 rings: 1RRC is SVA[15:14
] is interleaved based on Figure 19D is preferred.
It depicts the form it takes. [0234] Multiple RRC:0 is TwoRing:1/
2 and FourRing: single for one form.
Ring: Located on 0. Multiple RRC: 1 is Tworin
g:1/1, TwoRing1/2 and fourRi
The ng:1 configuration is configured on a separate ring:1. [0235] FIG. 6 shows a
Preferred Ring Routing Cell Pair (RRC Pair or R
RCP). pair is connected to a single communication line, e.g.
optical transmission connection (hereinafter referred to as inter-ring link)
includes RRC:0 and RRC:1 connected by RRC:0 and RRC:1. Downlink RRC is the opposite RRC of the RRC pair.
It is. RRC pairs connected to the same ring:0 are R
It is called an RC array. Cell or ring: 0
When discussing local RRC or RRC pairs,
Ring: RRC or RRC pair coexisting on 0
Ru. A remote RRC or RRC pair is a non-local
These are all RRCs. [0236] Each R
The RC bank is divided into three sections: root
Configuration interconnects, root configuration directories and rings
It consists of an intermediate buffer. The routing interconnect is a ring
Implement the RRC portion of the interconnect and route configuration directories.
provides an interface to the insert and
Extract buffer links to RRC internal route configuration bus.
interface. The route setting bus is 2
It consists of two 32-bit paths. Packets from extraction buffer
inter-ring drums via the link routing bus.
transferred to the buffer. The packet is routed to the ring
Transferred from the IBU to the RI insertion buffer via the configuration bus.
It will be done. The IBU also routes the packet to the link.
Inter-ring drum buff for error recording via configuration bus
Transfer to [0237] The root setting directory is
Connected Ring: All allocated pages in 0
Contains entries for the page. root configuration directory
The Root Configuration Directory Unit (RDU) and
Consists of actual ram-based directories. RDU is
, control directory access sequence and route configuration.
Contains fixed rules. For each package, the root configuration phase
The interconnect is pkt. addr, pkt. command
, and pass the fifo state to the root configuration directory
. The root configuration directory is used for root configuration commands and
and route instructions for updating packet commands.
Attribute to interconnect. The interleaving associated with the rings is Rd
MasterConfig Identified by location. [0238] The inter-ring buffer
It buffers incoming packets from the outgoing buffer, and
Interface to the link. interring buffer
is an inter-ring buffer unit (IBU), an inter-ring buffer unit (IBU),
Drum buffer (IDB) and inter-ring link-in
It consists of a surface. IDB allows packets to be sent between rings.
transmitted to the downlink RRC via the link.
and the route configuration interconnect until confirmation is returned.
buffers all packets from IDB Hama
Also includes an RRC error queue. IBU is a
buffers and formats inter-link packets,
Error checking is performed on packets arriving at inter-ring links.
provides buffering and control of the IDB. Rin
The inter-group link interface is a 32-bit wide IB
U sends outgoing and incoming packets to a physical link
- convert to matte or vice versa. RRC banks are separate inter-ring links.
or share a single interring link.
It can be configured to have Dual ring-to-ring link configuration
In this case, the inter-ring links are completely independent. single
In an inter-ring link configuration, both RRC banks are
share inter-ring links. The inter-ring link is RR
Connected to IBU of C bank. RRC is phosphorus
The two groups are arbitrated to share links between groups. IBU In
Incoming packets with tariff configuration and packet address
determines which bank is routed to. [0240] RRC is a UCS system failure detection battle.
It matches the abbreviation. All buses are parity and E
EC protected. Parity or ECC is possible
Instead of being played when possible, the chip is passed through. All DRAM and large SRAM data configurations are
EC protected. Single bit soft or hard error
is a fatal system error (system reboot required).
(required) and if possible soft
modified in a software-transparent manner. Predict high error rates
The data link (inter-ring link) is software transparent.
Perform transient frame-level operations. Frame level operation
errors in frames, including retransmissions where errors are detected.
guarantees free transmission. [Route Setting Interconnect] [Configuration] Each Route Setting Interconnect (RI)
Bank, subring, RRC internal route setting bus and
and the root configuration directory.
Ru. The RI consists of two routing interconnect units (R
IU). constructed in accordance with the present invention
A preferred RIU is illustrated in FIG. Each R
IU is half of a 16-byte wide ring and 8-byte
Interface to half of the twin route configuration bus
be done. The two RIUs store the packet's address and
Pass the command field to your root configuration directory
, the route configuration directory is the packet route configuration command
command, new packet command, and error status. [0242] Each packet has 1 in 10 while on the ring.
Consists of 6-byte double words (20 words). each long pa
packets (containing data) are stored in each RIU extraction buffer.
9 words are stored in the insert buffer as 10 words. Each short packet (no data) is stored in each RIU extraction buffer.
write one word to the file and two words to the insert buffer.
be remembered. RIU0 and RIU1 are ring data [
63:0] and ring data [127:64].
Connect each interface. RIU0 and RIU
1 extraction buffer is the route configuration bus to the link [15:
0] and route setting bus to link [31:16]
interfaces are connected to each. RIU1 and
and the RIU1 insert buffer is the route configuration bus to the ring.
[15:0] and the route configuration bus to the ring [31:
16] respectively. [0243] Ring-in-ring-out part of RIU
consists of a 6-stage shift register. The packet is shifted
can be copied or extracted from the storage register to the extraction buffer,
Packets from insert buffer are inserted into shift register
can. Insert and extract buffers are managed using FIFO rules
be done. RI Operation: The ring interconnect connects two sources to two
routed to one destination. The source is
, the preceding ring interconnect and the insertion buffer. Packets from the preceding ring interconnect are
Packets from the insert buffer are called insert packets.
It is called a cut. The destination is the next ring phase.
interconnect and extraction buffer. next ring mutual contact
The packets that appear in the continuation part are called ring packets and are extracted.
Packets that go into the buffer are called extracted packets. Insert
Incoming packets are fed into the insertion buffer, and extraction packets are
Inter-ring buffer unit (IBU)
removed from the fa. [0245] Packet address and command field
The file is passed to the root configuration directory and the root configuration
Directory returns packet route configuration commands. R
I do everything until I get the packet route configuration command
buffer stores the packets. ring empty feel
assertion that the ring packet is empty
give instructions. A non-empty ring packet is
are processed instead of insert packets. ring packet
If the insert packet is empty and the insert packet is not empty, the next insert packet is
buffer packets are processed by the ring interconnect
. [0246] The command from the root setting directory is
, packet route settings, packet fields, extracted buffer
It consists of a file, an insert buffer command, and an insert buffer command. [0247] Packet route setting code for all packets
command is path and empty. packet path command
The ring interconnect passes all packets unchanged to the next link.
identify what should go through the interconnect. packet empty
The command indicates that the ring interconnect has a ring empty signal.
and set the packet instruction CmdEmpty field.
Specify that the packet is to be emptied by CmdRequestId field is ring interconnect
All packets that match the CellNumber field
The directory is unconditionally emptied and the root configuration directory command
is not required. This causes the ring empty signal
When waiting for a command from the root configuration directory
can be set faster than possible. [0248] Extract buffer command can be used with no push or
and push. The no-push command
Specifies that the buffer does not currently store packets. The push command currently indicates that the ring packet is in the extraction buffer.
specifies what should be copied to the [0249] The insert buffer command is a no-pop and
and pop. No-pop commands insert buffer
Identify that the top packet was not inserted. Po
The insert buffer top packet is processed.
identify that it is being popped. [0250] The packet field command specifies which output
Specifies whether the command field is changed. The packet command fields that can be modified are shown in the table below.
shown. pkt. All fields except Freeze are
, pkt in instruction [31:0]. Packet Command Field Instruction
Description of Freeze
pass, clear, or set
Invalid
Pass, clear, or set
Pcopy
pass, clear, or set
Timestamp
Click from path or rule.
rear
With RingMaster
InvalidatorBusy
pass, kriya, or
Set Responder Busy
pass, clear, or set
InvalidateLookahead
Pass, clear, or set
rrc
pass, clear, or set
RRC Fault
Pass or set Spa
AddrError
Pass or set MarkedFa
ultimate
Pass or set UnMarkedFault
pass, ma
or set 0252 The packet is an empty packet.
Trouble configuration command and push extraction buffer command
extracted by the command. The packet is routed through the path packet route.
Copy by setting set command and push extract buffer command.
- will be done. [Extraction buffer management] The extraction buffer is short (2 words)
and length (18 words) to hold the packet combination.
Ru. This is equal to 512 words. This is the largest, longest
18 packets, 256 short packets, or long
/ produces a combination of short packets. peak sub ring package
The rate at which IBM can empty the extraction algorithm is
Extract buffer management flow control algorithm
algorithm is required. The control algorithm
Maximum forward progress in relation to reduced system load
Based on the principle of system towards completion requirements in progress.
Prioritizing system resource allocation achieves both of these goals.
be done. Because completing one requirement is the same
The most efficient forward direction, reducing system load when
Achieve progress. The control algorithm
Based on the use of separate and ring flow control mechanisms. [0254] The empty space in the ring extraction buffer is 2
one configurable pointer, ExtractAllTh
reshold and ExtractRspThre
It is divided into four areas by shold. current area
is selected by the number of empty words remaining in the extraction buffer.
Ru. The area going from empty to full is ExtBuf:A
ll, ExtBuf. NonOpt, ExtBuf
:PendReq and ExtBuf:Full
be. The extraction buffer status is a unit base per RRC bank.
maintained at the source. The boundaries of these areas are determined by the software.
It can be morphed by a. Ring packets are
for buffer management purposes, into three mutually exclusive categories:
classified into groups. (1) Optional packet The following remote
Packets issued at
It is local. That is, -Pendle:None
and SpState: Recombine with {Inv|Ro}. -Local ring: read-only copy of subpages within 0
- Duplicate for None. data. -Local ring: read-only copy of subpages within 0
sva readro. data. (2) Non-optional packets SpStat
must be extracted based on e. Optional pa
Does not include ket. (3) Locally emitted packets or RRC packets
Ending request (RRC:0Pend{1,2,3},
RRC:1Pend{1,2,3,4,5}) is satisfied
packet. [0256] The categories of these packets are as follows:
Processing is performed using four extraction buffer areas. i.e.
, Area Optional Non-O
optional response packet
packet packet
Ex
tBuf: all acceptance
Acceptance Acceptance Ext
Buf:NonOpt Pass
Acceptance Acceptance Ext
Buf:Pending Pass
path and
RspBsy, InvBsy
Assertion path ExtBuf:Full path
path and RspBsy,
path
Express InvBsy
Text reference 0257 ExtBuf: All
In the region, Empty and ExtractA
llThreshold, normally the extraction buffer is
All packets copied are copied. ExtBuf:
In the NonOpt region, ExtractAllT
hreshold and ExtractRspThr
between eshold and are normally copied to the extract buffer.
All non-optional packets and responses that would
The packet is copied. All optional packets
will be missed. Extraction buffer and RRC are optional
Abandon it as more lelords arrive. E
xtBuf: In the PendReg area, Extra
Between ctRspThreshold and Full,
Only packets related to RRC pending requests are accepted.
Can be put in. All optional packets and
Optional packets (including new incoming requests) are
Sponda busy (rsp busy) or in
Validator Busy (inv busy)
Becomes Bee Gee due to the announcement. RRC uses optional
Abandon both the load and the new request. [0258] When the extraction buffer is full, the RIU
passes optional packets and passes non-optional packets.
Responder busy or invalidator to request
Express Bee Gee. If the packet is in this RRC
If the packet is a response to a request issued by
Remain on the ring, pkt. cmd. timestamp
The field is cleared. Only packets related to RRC pending requests are
Since the package is accepted in the
will be copied on subsequent moves around the group. pa
The fact that the ket is in the middle of its second rotation
transparent (obvious) to all cells within the cell. if
Also, packets that satisfy pending requests (snarf)
packets originated by this RRC
If there is no response to the request, the pending request state is
Pend4: Converted to Reissue state. [Root Setting Directory] [Root Setting Directory Organization] Root Setting Directory
The root configuration directory unit (RDU)
and the actual ram-based directory. R.U.
D controls the directory access sequence and
Contains root configuration rules. The preferred implementation of the rule is SP
A Hardcode the rules and RR the SVA rules
C Allows to be loaded during initialization. FIG. 8 is a preferred embodiment of the invention.
The organization of the root setting directory is depicted. Route setting
The fixed directory is the ring to which the RRC pair is connected: 0
Entries for all assigned pages in
including. SVs allocated over a single local cache
A single root configuration directory for pages
Entry required. The root configuration directory is
3 levels b for each of the 128 subdirectories
organized as a tree. The subdirectory is
A single
All allocated pages in the local cache set
Contains entries for the page. subdirectories up to
64 rings: up to 210 pages supporting 0 cells
can be described. The local subcache of each cell is 1
Contains 128 sets containing 6 pages. Ring: 0
The sub-ring has cache set lsb, SVA[14
] to interleave subpage transfers based on
It is composed of Thus, half of the root configuration directory
Each ring: 0 subring (ring: 0A, ring: 0 subring)
(0B). [0261] L1 entry (Entry) is SVA
Indexed by [39:25]. L1 entry
are statically allocated to each of the 24 pages in a set.
. Each valid L1 entry is a dynamically allocated L2 entry.
Identify the pointer to the bird. Up to 210 L1 entries
is available. An unallocated L2 entry is a single
organized into linked freelists. Ind
exi L2Free List Pointer is
Points to the first L2 free list entry. free list
Each L2Enry in the next L2 free list entry
Contains a pointer to. Last L2 free list entry
The bird contains a zero pointer. Each L2 entry has 16
Contains subentries. Each valid L2 subentry
Contains a pointer to the L3 entry allocated
nothing. A maximum of 210 L3 entries are available. Each L3 entry describes a single page. unassigned
l3 entries are assembled into a single linked free list.
woven. IndexiL3Free List P
ointer sets the first L3 freelist entry to
Point. Each L3 entry in the free list is linked to the next L3 file.
Contains a pointer to a list entry. Last
L3 freelist entries contain zero pointers. Each L3 entry consists of 16 L3 subentries,
And each of them has a subpage shape for 8 subpages.
Describe the situation. [Configuration of root setting directory] FIG. 9 shows the configuration of the root setting directory of the present invention.
The structure of the preferred embodiment root configuration directory is
This is what I drew. The root configuration directory is
Physical data in L1, L2 and L3 tables for the ring
organized. The L1 table is SVA[20:1
4] (set number) and SVA[39:25] (in
dex1). SVA[39:25:,20:14] is index
It is called 1. Each L2 entry has L2 subentries and
and L2V. The L2 subentry is SVA[
20:14], L1Table[indexl]. 12
ptr and SVA[24:21] (index2)
Addressed by concatenation. L2V is SVA[20
:14] and L1Table[index1]. 12
Addressed by concatenation of ptr. L2V fee
If the L2 entry is valid, the
L2 entry valid field.
If the list is invalid, level 2 next free list entry
Interpreted as a repointer. Each L3 entry is an L3
Consists of sub-entries and L3 valid. L3 subue
The entry is SVA[20:14], L2Table. 1
2sub[index2]. ptr and SVA [13
:10] (index3)
. Individual subpage status is SVA[20:14],L
2Entry. 12sub[index2]. ptr,
SVA[13:10] and SVA[9:7] (in
dexsp). L3V
The field is level if the L3 entry is valid.
field 3 is interpreted as a subentry valid field and
If the L2 entry is invalid, level next
interpreted as a list entry pointer. [0263] The C-shaped description of the table structure of one bank is shown below.
show. }L3V; 0264th
Figure 10 shows a preferred ringle constructed in accordance with the present invention.
Root configuration directory entry in root configuration cell
It depicts the format of [L1Entry] L1Entry is the L2 entry.
Repointer (12ptr), L2 pointer valid bit (
11 Enable) and L1 check bit (11 Check
(h)). 12ptr is L2E as described below.
used to address entries. L1 Valid
Set indicates valid 12ptr, clear indicates
Indicates invalid 12ptr. L1 check is 5 bits
Single bit correct and double bit detect ECC
Consists of code. [L2Suventry] L2Suventry is L
3 entry pointer (13ptr) and L2 check
Includes qubits (11 checks). 13ptr is
, used to address L3 entries as described above.
It will be done. L2 check is a 5-bit single bit correct or
and double-bit detection EEC code. [L2 VENtry] There are two L2V Entries.
format, one is L2V entry
(L2V.Valid) for use as
, one of the L2 free list (L2V.Invalid)
If it is a section, it is the second one. L2V. valid is
Array of 16 valid bits and 5 ECC check bits
Consists of A. L2V. valid. 12valid[n
]set indicates valid L2 subentries [n]
, clear indicates invalid L2 subentry [n]
Show. [0268] L2V. invalid is nextoff
Lee L2 entries, unused fields and ECC channels
It consists of a check field. L2V. invalid.
NextFree is a NEXT L2 free list entry.
used to address birds. NextFree
high order bit clear
pointer. [L3Subentry]L3Subentry is 8
Subpage status field pointer (L3Subent
ry. SpState) and check bit (L3
Subentry. check). L3 Sube
ntry. check is an 8-bit single bit correct
and double-bit detection EEC code. [L3VENtry] L3VEntry has two formats.
mat, the first one is L3VEntry (L3V
．． Valid) for use as L3 fr
Part of ee list (L3V.Invalid)
This is the second one. L3V. valid is 16
Bit generated OwnerLimit, Page
Array of Pend and ecc check fields
Consists of A. L3V. valid. 13valid[n
] corresponds to L3Subentry[n] and L3V.
It is a function of generation. 13valid[n] generation
L3Subentry [n] 0
0 all subs
Page invalid 1 0
Actual subpage state
0 1
All subpages exclusive
1 1
Actual subpage status 0272
]L3V. valid. OwnerLimit is a page
Restrict ownership of subpages within the page to local ring: 0
set or cleared by software, such as
. When cleared, any ring: 0 is a subpage
Specify that you cannot own. When set, the station
Division ring: Only cells within 0 have subpages, non-exclusive,
Owns atomic or transient atomic state
Identify what you can do. Remote ring: 0 is lead on
You can receive a copy. Page failure is caused by OwnerL
Ownership is requested by RRC when imit is set.
will be notified. A recombination request is made when OwnerLimit is
Local ring when set: not propagated beyond 0
. Cleared during RRC descriptor allocation. [0273]L3V. valid. PagePend is
, when set, the RRC page is set to deallocate
Indicates that Kens is in progress. [0274]L3V. invalid is nextoff
Lee L3 entries, unused fields and ECC channels
It consists of a check field. [0275]L2invalid. Nextfree is
, used to address the next L3 freelist entry.
used. NextFree high order
bit clear points to the zero pointer. [0276] Eight operable root setting directories
There is a Route Setting Cell (RRC) directory operation. child
These operations occur within a single packet time. all pa
Allow a single action to be performed on a packet type. Level 1 Miss Lookup Operation Level 2 Miss Lookup Operation Normal Lookup Operation Level 3 Subentry Deallocation Level 2 Subentry Deallocation SPA Access Reclamation or Refresh 0277 System Virtual Address (SVA) Lookup
All lookup operations are performed by subdirectory selection.
, level 1 table lookup, level 2 table lookup
lookup, level 3 table lookup and level
Proceed through the five stages of modifying the subpage status.
go Level 2 entries and level 3 entries are
No allocation is required to complete the lookup operation.
It will be. Normal lookup operation Normal lookup operation is performed when level 2 entries are enabled.
If the level 1 table indicates something and the level 3 en
When the level 2 table indicates that the bird is valid,
Occurs when [0279] L1EntryAddr, L2Entr
yAddr and L3EntryAddr are
Calculated as described in the section on configuration directory structure.
be done. L1EntryAddr being set →
11valid means the level 2 pointer is valid
instruct. SVA[20:14] and L1Entr
y[index 1]. ptr concatenation is a subdirectory
is implied or implied by a 10-bit pointer.
Therefore, specify L2Entry. level 2 suben
Tori (L2EntryAdrr →12sub[ind
ex2]) is not determined by SVA[24:21]
and indexed. L2Entry being set.
12v [index2] is a level 3 pointer (L2E
ntryAdrr →12sub[index2]. p
tr) is valid. SVA[20:1
4] and L2Entry[index2]. ptr
The concatenation of subdirectories is done by 10-bit pointers.
Since this is implied, specify the L3Entry. level
L3 subentry (L3EntryAdrr →13s
ub[index3]) by SVA[13:10]
Indexed. Each level 3 subentry is
Contains subpage states for eight subpages,
Indexed by SVA[9:7]. Index3
points to SVA[13:10] and Indexes
indicates SVA[9:7]. L3Entry. v
alid[index3] and L3Entry. c.
reated indicates whether the corresponding subentry is valid or not.
and if invalid the default subpage state
Identify. [0280] The subpage status is sequentially changed to L3EntryA.
drr →13sub[index3]. SpStat
New subpage to be stored in e[indexes]
The root configuration directory rule (Rou
ting Directory Rules)
It will be done. Level 1 miss operation Level 1 miss lookup
a level 1 table lookup is a level 2 table lookup.
Occurs when indicating that the entry pointer is invalid.
Ru. Level 1 miss lookup behavior is
The request system virtual address page and support
level 2 to allow for describing page states.
Assign entries and level 3 entries. level
1 mistake, the address indicated by SVA[39:25]
Ring to address band page: 0 (Ring: 0)
Triggered by the first reference within. If, Pake
If the cut command is ciu ex summary, the required
request is part of the page generation operation. [0282] Level 2 free list head is level 2 free list head.
indicated by the list pointer. Go to free list
L2Entry. NextFree is the next free
Identify a pointer to a level 2 entry. level 2 free
- The list head is LevelEntry. point
Write er with a level 2 free list pointer and write L
1Entry. The level is set by setting valid.
2 entries. level 2 freeli
The stop pointer levels the level 2 free list pointer.
L2 free list head, L2Entry. NextF
It is updated by writing with ree. L2Ent
ry. 12v. 12valid[SVA[24:21]
] is set and the remaining valid bits are cleared.
. [0283] Step
Operation 1 L1EntryAddr
→12ptr = L2FreeListPoint
ter2 L1EntryAddr →
valid = set3 temp
= L2FreeListPointer →12
v. Invalid. NextFree4
L2FreeListPointer →12v.
Valid. 12valid[15:0] = cle
ar 5 L2FreeListPoi
nter →12v. Valid. 12valid [(
SVA[24:21])] = set 6
L2FreeListPointer=te
mp0284] If L2FreeListPoint
If ter is null (blank), the route configuration directory
A cultri fault is signaled. Corresponding ring: 0
Over 210 unique pages within a single subdirectory
level 2 entry or the routing cell assigns a level 2 entry.
If you fail to allocate or deallocate correctly,
This error only occurs if 210 unique pages require 64 processor cells
(210 pages/24 pages per cell)
J). [0285] Level 2 miss operation Level 2 miss lookup operation
Backup indicates that the level 2 entry pointer is invalid.
Occurs when giving instructions. Level 2 miss lookup
The behavior is that the root configuration directory is
It is permissible to describe the page and subpage state of the address.
Assign a level 3 entry so that level
2 miss is indicated by SVA[39:21].
Ring to address band page: 0 (Ring: 0)
Triggered by the first reference within. If, Pake
If the cut command is ciu ex summary, the required
request is part of the page generation operation. [0286] Level 3 free list head is level 3 free list head.
indicated by the list pointer. Go to free list
L3Entry. NextFree is the next free
Identify a pointer to a level 2 entry. level 3 fu
The list head is Level2Entry. 12s
ub[index2]. 13ptr level 3 freeri
allocated by writing with a stop pointer. The level 3 free list pointer is the level 3 free list pointer.
level free list head L3Entry
．． It is updated by writing with NextFree. L3Entry. 13v. 13valid[SVA[1
3:10]] is set and the remaining valid bits are cleared.
will be ascribed. L3Entry. 13sub([SVA[1
3:10])]. SpState[SVA[9:7]]
is set and an appropriate subpage state is set.
and the remaining 7 sub states are set to invalid.
be done. If the packet command is ciu ex summa
ry, L3Entry.ry. 13v. Valid.
created is set. [0287] Step
Operation 7 L1EntryAddr
→12sub. 13ptr = L3FreeLi
stPointer8 temp =
L3FreeListPointer →13v. I
invalid. NextFree9 L
3FreeListPointer →13v. Val
id. 13valid[15:0] = clear
10 L3FreeListPoint
er →13v. Valid. 13valid [(SV
A13:10])] = set11
L3FreeListPointer →13sub[
(SVA13:10])]. S
pstate[7:0] = invalid 12
L3FreeListPointer →
13sub[(SVA13:10])]. Spstat
e[(SVA[9:7])] =
new-sp-state13 L3F
reeListPointer →13v. Valid
．． Created = clear 14
L3FreeListPointer = tem
p0288 System virtual address deallocation operation system
The stem virtual address deallocation operation is performed using the packet instruction ci.
u inv sum alloc, ciu pure
inv sum alloc and RrcDeall
Initiated by ocDesc. All deallocation activities
The process includes subdirectory selection, level 1 table lookup,
lookup, level 2 table lookup, level 2
If you update the entry and unassign the level 3 entry,
It progresses through five stages. If all levels
If 2 sub-entries are invalid, level 2 entries in sequence
is also deallocated. Level 3 Entry Deallocation Operation Level 3
All level 2 subentries after entry deallocation
is not invalid, the level 3 entry deallocation behavior is
executed. The following operation is performed when the packet instruction is ciu i
If it is nv summary, it is executed. [0290] Step
Operation 1 L2EntryAddr
→12v. Valid. 12valid[(SVA[
24:21])] = clear 2
L3EntryAddr →13v. Invalid
．． 1NextFree = L3FreeListPo
inter 3 L3FreeList
Pointer = L2EntryAddr →12
sub[(SVA[24:21])]. 13ptr [
[0291] The following operation is performed when the packet instruction is ciu wr
description. data or ciu in
v sum allocate. If it is data, it is true.
will be carried out. step
Operation 1 L2EntryAddr
→12v. Valid. 12valid[(SVA[
24:21])] = clear 2
Packet. DataWord2[9:0] =
L2EntryAddr →12sub[(SVA[2
4:21])]. 13ptr 0292 Level 2 entry deallocation operation Level 3
All level 2 subentries after entry deallocation
is not invalid, the level 2 entry deallocation behavior is
executed. Step
Operation 1 Execute dea
locate Level3 Entry Opera
ation (performs level 3 entry deallocation operation)
) 2 L1EntryAddr →11V
alid = clear 3 L2E
ntryAddr →12v. Invalid. Next
tFree = L2FreeListPointer
4 L2FreeListPoint
r = L2EntryAddr →12ptr 0
294] SPA operation SPA operation is spa read
requests and spa write requests
It is started by two packet instructions, t. Sp
There are two types: aDirect and SpaLookup.
There is a spa operation. [0295] SpaDirect operation is based on packet access.
Delay for spa location specified in dress
read or write
go Spa write request data
is Pkt. Provided to DataWord0. Spa
read request response data is Pkt.
Provided to DataWord0. [0296] SpaLookup operation
Under controlled conditions from the address space, the RDU looker
to emulate the pop-up behavior and deallocate the behavior.
used. Pkt. Address position offset
and ctl$RiuLookupCommand.
SubAddr forms an emulated SVA
and ctl$RiuLookupCommand
The remainder forms emulated packet instructions. R
DU uses emulated packet instructions.
to emulate normal lookup behavior and
performs a deallocation operation. SpaLookup operation
The result is L2FreeListPointer, L
3FreeListPointer and SpaDir
ect location. Refresh Operation Refresh is performed by each RRC individually.
achieved in a decentralized manner by fresh control
Ru. A single refresh takes one packet processing time
I need. In this way, refresh
It can only be performed during connected packets. Because this
These packets do not require any processing
It is from. RRC performs refresh,
When all empty and frozen and hidden packets
refresh in the background.
Trying to do the same thing. [0298] L1Table, L2Table and
There are three dynamics called L3SubpageState.
RAM-based data structures require refreshing.
Essential. During a refresh operation, one of the 512 columns
Columns are refreshed with their respective data structures. ECC Corrective Action When a route setting cell detects a correctable ECC error.
the additional packet time required to modify the data structure.
It is essential. Ring freeze behavior fixed and re-look
Used to allow multiple packets up time. [0300] When a correctable ECC error is detected
, ECC errors are known from the beginning in packet processing.
Therefore, RRC is Full-1 Ri
Start the ng Freeze method. the first packet is
, as described in the Extract Buffer Full Section section.
and the remaining packets are frozen for one rotation.
Marked as a conclusion. Modified data that has been rewritten
The data structure is saved in RDU and sequentially rotated one ring.
later used to reprocess packets that lead to ECC errors
be done. Only packets for which a routing cell occurred are processed.
and non-occurring packets are extracted by another cell in the ring.
be done. The saving operation of modified packets is based on the route setting cell.
packets emitted by a single bit (modifiable
) to ensure that hard errors are handled correctly. [0301] Initialize root setting directory Root setting
The default cell hardware will automatically change the root configuration directory.
It is not initialized to . All Level 1 Entries
s (Level 1 Entry), Level 2 Subent
ries (Level 2 entry) and Level3Su
ventries (level 3 entries) are initialized to invalid
must be made into Level 2 and Level 3 Freeli
pointers and freelists for all entries.
and to indicate that the subentries are free.
must be initialized to . [0302] InterRing Buffer (InterRing
Buffer) An inter-ring buffer is a ring interconnect buffer.
Buffers and reloads input packets from the extraction buffer.
Provides an interface with the inter-engineering link. Inter-ring bus
The buffer also manages the route configuration cell bank buffer.
Control. The interring buffer is an interring buffer unit.
(InterRing BufferUnit, IB
U), inter-ring dynamic RAM buffer (Int
erRing Dram Buffer, IDB) and
and inter-ring link interface (InterRin).
gLink Interface). Inter-Ring Buffer Structure Inter-Ring Buffer Unit (IBU) The IBU buffers inter-ring link outgoing packets and
packets entering the interring link.
performs error checking and buffer operations, and performs inter-ring diversion.
Controls the dynamic RAM buffer. Output buffer is 72
Contains words and stores packets with a maximum length of 4.
The input buffer is for packets with a maximum length of 4.
Holds 72 words. Input buffer sizing (fixed size)
) behavior depends on the interring link rate and absolute delay (length and
switching delay). 72 word buffer is 1
Directly connected to gbit/sec link, 10km
Sizing is done for maximum length. A short packet takes 2 words
and long packets are sent to the outgoing or incoming buffers.
spend 18 words. Output and inbound buffers are fif
o method. [0304] Inter-ring dynamic RAM buffer (I
DB) Inter-ring dynamic RAM buffer (InterRi
ng Dram Buffer, IDB) is the ring buffer.
Ring Packet Q (RPQ, Ring Packet Q
UEUE) and Routed Cell Error Queue (RRC
ErrorQueue). To the present invention
Therefore configured Preferred Routing Cell (RRC)
The configuration for inter-ring drum cues in
Illustrated in the figure. Ring packet queues allow packets to pass through interring links.
is transmitted to the downlink route setting cell and confirmed.
until an acknowledgment is returned.
All packets from the routing interconnect unit
Buffer. The extract and output buffers are full.
When an extraction buffer packet is
are injected into the IDB until it can receive the ring packet
Queues are organized as circular queues. Ringpa
packet queue push pointer (RPQPushPoi
nter) is about the next packet from the extraction buffer.
point to the first free word to perform the cue action.
Show. Ring Packet Queue Pop Pointer (RPQ)
PopPointer) is
indicates the first word of the next packet to be transmitted. PRQ commit pointer is the downlink route setting
The first of the oldest packets not answered by the cell.
Indicate the word. ring packet queue push point
and the ring packet queue pop pointer.
packets are queued for transmission over the interring link.
ing or waiting operations are performed. RPQ pop
pointer and ring packet queue commit point
Packets between nodes receive responses from downlink route configuration cells.
I'm waiting for the answer. If ring packet queue push
pointer equals ring packet queue pop pointer
If so, there is no queue for transmission on the interring link.
The packet is also not in the ring packet queue. If phosphorus
packet queue pop pointer is set to PRQ commit point.
If equal to the interface, all transmitted packets will be answered
Is receiving. If the ring packet queue overflows
If you load it, a fatal error will occur in IbuMasterConf.
ig. Indicated by RPQFull. [0305] The inter-ring dynamic RAM buffer is
It also includes a routed cell error queue. Roux
The routed cell is each detected by the routed cell.
for each error in the error queue (ErrorQueue).
Place entry. Each error queue entry has an error (if
(if any) corresponding to the packet and one word of error information
Consisting of Error queue push pointer (EQPushPoint
er) to perform the next error entry queue operation.
, indicate the first free word. Error cue poppo
Inter is the least recent queue error (least recent queue error)
tqueuederror)
Ru. If the error cue pop pointer
If equal to the pointer, the routed cell error queue
is empty. The error cue pop pointer is set to
Some files are not modified by SPA access.
will be corrected. IbuMasterConfig. EQ
Full means the route setting cell error queue has overflowed.
It is set when Routing cells operate normally.
It will continue and no new errors will be recorded. Inter-ring link interface Inter-ring
The link interface is a 32-bit wide inter-ring buffer.
Buffer unit output packet/input packet interface
interface to a physical link format or
Convert from different link formats. [0307] Routing cell buffer management rules
The root setting cell pair is fifo type, ring: 0 and
Ring: One of the directions between the pair.
(FIG. 11B). root
The configured cell bank consists of 5 buffers, a ring and an outgoing link.
Three buffers between inter-ring links, incoming inter-ring links and
and manages two buffers between the rings. Copy from ring in uplink route configuration cell bank
packets sent to the extraction buffer and optionally to the ring
packet buffer and inter-ring link out buffer
is transmitted sequentially across the inter-ring link. Pake
The output is sequentially transferred to the interring link input buffer and downlink.
Pass through the insertion buffer of the Clute setting cell bank. Opposition
Packets traveling in the direction of
Extract buffer, link
link packet buffer and inter-ring link output buffer.
It goes through. Packets are sequentially transferred to the interring link input buffer and
and uplink route configuration cell bank insertion buffers.
It goes through. [0308] Extract and insert buffers are ring and insert buffers.
The speed or rate between the routing cells' routing buses.
Make adjustments. Input and output buffers are inter-ring links
and speed adjustment between the routed buses in the routed cell.
conduct. The ring packet queue is filled with pending and
Enable to store the maximum number of packets involved
This reduces possible overflow of these buffers.
and deadlocks between routing cell pairs.
to prevent Buffers are used for extraction and interring link output.
Occasionally used to perform buffer operations between buffers.
The size is determined so that ring packet queue
Additionally, if retransmission is required due to link errors,
, records all packets transmitted on the inter-ring link
It is also used to. In the preferred routing cell bank implementation:
, between the extraction buffer and the inter-ring link output buffer and
and inter-ring links between the out buffer and insert buffer.
Provide a set path. Interring link input buffer empty
and the insert buffer is not full.
The inter-program buffer unit inserts packets from the input buffer.
Transmit to input buffer. [0310] The extraction buffer is not empty and the inter-ring drum
The queue is empty and the interring link out buffer is full.
When the interring buffer unit is not full, the
Transmit packets from the buffer to the output buffer. If it comes out
If the buffer is full, the packet is removed from the extraction buffer.
Transmitted to inter-ring drum cue. drum key between rings
Packets included in the queue are always extracted from the extraction buffer.
It is transmitted to the outgoing buffer before any packet. [0311] Inter-ring link packet protocol and
Formatting inter-ring link packet protocol and
The format supports multiple generations of UCS computers.
is applicable over a range of link speeds.
Needed. Single protocol and format
Long-distance communication with fee structure from 25 meters inside the room
Interconnection range up to 10,000km over the network
distance should be covered. The format is SONET
It should be compatible with emerging telecommunications network standards such as
It is. It was adopted from the SDLC protocol
Based largely on simple concepts. 1978, Addison
-Wesley Publishing Company
Published by R.Y. J. “Co” by Cypser
communication architecture
or Distributed Systems”,
Published by Addison Wesley in 1987
"Te" by Mischa Schwartz,
communications networks
: Protocols, Modeling and
Please refer to "Analysis". Figure 12 shows
used in a ring route setting cell configured according to the present invention.
Illustrating the preferred inter-ring link frame format
are doing. [0312] The connection between confirmation and retransmission routing cell pairs is fully duplex;
Consists of two unidirectional interring links. Rin
Due to the uncertain reliability of inter-group links, very reliable and
Explicit confirmation is required at link level. sending route
Configuration cells are those transmitted over the outgoing inter-ring link.
For each packet, a reliable
Yes, accept positive confirmation. Transmit next packet
Waiting for confirmation beforehand leads to very low efficiency. Inter-ring bus
The buffer unit attaches an ordinal number to each transmitted packet.
However, up to 216 packets are marked as pending before the first check.
It is considered to be a state. The ability of duality allows two independent sets of
A sequence number is used, one for each direction of packet flow.
Ru. This is one inter-ring link recovery route setup.
Proceeds independently of the order of other interring links between cell pairs.
and possible timing ambiguity
Avoid. Only data packets are examined sequentially. [0313] The two ordinal numbers are each inter-ring buffer.
maintained by the support unit. Works with modulo 216
IbuXmitSeqNum is the inter-ring buffer
Each data transport packet transmitted from the
Give a count for each hit. Ib which is modulo 216
uRcvSeqNum is the value of this inter-ring buffer unit.
are in the valid order of each received by the client.
Incremented by one for each error-cleared data packet.
Ru. One interring buffer unit has its IbuRc
Set vSegNum to downlink inter-ring buffer unit.
When sending to
and is indicated by the packet reception order number.
All data received up to (and including) the value
Used to confirm packets. each successive
The transmitted IbuRcvSeqNum of all
Double check that your message was accepted. multiple
data packets can be seen in a single packet
can. Packet Format The inter-ring link packet format is
(Frame Start), Preamble (Pre
amble), Ring Pack
et ), CRC and end of frame (Frame
It consists of five fields: End). Fray
The frame start and frame end fields are link-specific.
Frame indication field and inter-ring link
Added to or added to inter-ring packets depending on the interface.
removed. Frame start and frame end fields
Depends on the type of physical link. [0316] The preamble contains link control commands and order confirmation.
identification field, transmission frame sequence number (TFSN) and
and the received frame order number (RFSN). control
Instructions for word count and ring packet subfields
Clarify the content. Control Cmd
Ring Packet Size Order Idle
(idle) 0 words
unordered initial
initialize request (initialize 0
code unordered
request) Initialization sequence (initialize 0
Do out of order
sequence ) Initialization confirmation (initialize 0
word ordering
(not acknowledged) short packet (short packet) 2
words ordered
long packet 1
8 words ordered
[0318] Instructions are ordered instructions and
Divided into unnumbered instructions. Order of links
The number is set in the route setting for ordered frames.
incremented by pair. About the link
The order number is incremented for unordered frames.
is not printed. [0319] The transmission frame order number (TFSN) is
represents the ordinal number of the system. each consecutive ordered
The frames that were added have their ordinal number incremented by 1.
have Inter-ring links are numbered modulo 216
I used it. When the transmitter reaches its maximum order number
, the transmitter transmits until a frame in the opposite direction is accepted.
and checking for undecided packets is forcibly stopped. reception
Frame order number (RFSN) is the reception of RFSN-1.
and any frames preceding that number are still
Not confirmed. RFSN is the number the receiver expects the ordered number RFSN to be.
Instruct what you are doing. Transmission ring buffer unit
All frames that have not yet been explicitly advertised
buffer. Once securely notified, frame
The system can be wiped out or purged and its order number can be reused.
Ru. [0320] The inter-ring link is a communication link such as HDLC.
The intelligence function is embedded in the frame transmitted in the opposite direction.
Gives "piggyback" nature. Multiple frames can be combined into a single frame.
Notification can be made in the frame. The three possible notifications are:
That's right. [0321] Notification
Function Ready to receive
　　　　　　　　　　　　　　　　　　　　　　　　　
Received frame order number (RF (RR
)
SN) All up to ordinal numbers including -1
　　　　　　　　　　　　　　　　　　　　　　　　　
frames received
make sure that
Approval
do. Not ready to receive
Regarding temporary congestion
Te (RNR)
Gives flow control. Friends
Sort by group
Number (RF
SN) Ordinal numbers including -1
　　　　　　　　　　　　　　　　　　　　　　　　　
Check all frames in
　　　　　　　　　　　　　　　　　　　　　　　　　
. Rejection (REJ)
Packet order number (RPSN)
Snobe
Tenofure
refuse to receive messages.
Received frame order
Number (RFSN) -1
　　　　　　　　　　　　　　　　　　　　　　　　　
All frames up to the ordinal number including
　　　　　　　　　　　　　　　　　　　　　　　　　
Check the system. [0322] The idle command is a ring packet field.
is null and there is no preamble and checksum
indicates that the remainder of the checksum is valid. Initialization
Requests, initialization sequences, and initialization confirmation instructions are
The inter-IBU ordering protocol is implemented at each end of the inter-group link.
Used to initialize and synchronize. Initialization sequence
The transmission inter-ring buffer unit has its order number.
Indicates that it has been reset. The incoming route setting cell is
Reset sequence number, ring packet queue, I
buMasterConfig. Click RPQFull
should be reset and send a reset confirmation control command packet.
be. Initialization requests are sent to the downlink inter-ring buffer unit.
resets the sequence number and sets the ring packet key.
IbuMasterConfig. RPQFul
Clear l and send initialization sequence packet
do it like this. Short packet and long packet instructions are
The packet fields indicate short or long packets, respectively.
Indicates inclusion. [0323] The inter-ring link has two links for error recovery.
Use mechanisms. 1- Refusal to recover. This is between rings
Required whenever possible to increase link recovery speed.
It is considered necessary. But it's a given frame
Can only be used once per program. It's that frame.
Cannot be called for repeated programs. 2-
Time-out recovery. This is always used in addition to denial recovery.
Must be. Isolate without time-out recovery
of an ordered frame or series of frames.
If the last one is transmitted incorrectly, it will not be recovered.
. In addition, recovery rejection occurs once per sequence frame.
Multiple losses of a given frame can sometimes occur because
Must be processed through an interval. [0324] Incorrect check for link packet errors
Total Sequence Transmission Packet Number Out of Range Clock Recovery Error Link Frame Error 0325 RNR Confirmation Input Buffer Full
When giving flow control. Maximum interring link bandwidth
For proper use, use the smallest possible amount of the bag.
The phase size is a round-trip inter-ring link.
is the number of frames received during the delay. [0326] The cyclic redundancy field (CRC)
Calculated from the bull and ring packet fields. [0327] IB operation inter-ring buffer unit buffer management control is as follows.
Performs IB operations and transfers data between five route configuration cell buffers.
Forward the packet. [0328] Packets from the ring interconnect packet extraction buffer are routed through the route bus.
specified by the ring packet queue push pointer.
Both stored start and ring packet queues where
will be forwarded to. Pointer is short packet and long packet
is incremented by 18 words for both. Ring packet is free (RPQ push point
equal to the RPQ pop pointer) and the out buffer
is not full, the packet is pushed further to the outgoing buffer.
and the RPQ pop pointer increments.
will be played. IbuXmitSeqNum is an inter-ring link.
one ink for each data packet transmitted on the link.
Remented. Ring from Dynamic RAM Buffer
The interconnect packet ring packet queue is not empty and the outgoing buffer is empty.
Is the packet in the ring packet queue when it is not full?
is transferred to the output buffer. ring packet cuepot
The pointer is incremented by 32 words. Inter-Ring Link Packet Packets are transferred from the input buffer to the insertion buffer. The count IbuRcvSeqNum is incremented by 1.
is recorded. [0331] Inter-ring dynamic RAM buffer reloading
The fresh refresh sequence is
Performed by inter-ring drum when the component overflows.
be done. Refreshing is not the same as any other route configuration activity.
take a high priority over the work. Inter-Ring Link Retry Each packet received over an inter-ring link is
Specifies the received error clearing packet and whether an error was detected.
Set. If verification does not indicate any errors, link
Packet queue commit pointer and Commit
The PktNumber location is updated in the following manner. 1-RPQCommitPointer=RPQco
mmitpointer+(RcvPktSeqNum
- CommitPktNum) * 32 2 -
CommitPktNum = RcbPktSeqN
um When a reject packet is received, I
BU passes the ring packet queue push pointer.
The order number after the same ring packet queue commit pointer and
Both must retransmit all packets. I
bis to adjust ring packet queue pop pointer
It is executed more. 1-RPQCommitPointer=RPQco
mmitpointer+(RcvPktSeqNum
- CommitPktNum) * 32 2 -
CommitPktNum = PktRcvSeqN
um3-RPQPopPointer=PktRc
vSeqNum4 -Store received
error packet in error queue
e (stores received error packets in error queue)
[0334] For any error detected by the error record RI, the root
IBs and RDUs in configured cells, corresponding packets and
and two words in error are placed in the routed cell error queue.
recorded. If the packet is routed to the downlink
ring packet queue if it is being transmitted to a set cell.
Further queuing should take place. SPA Read/Write Interring Dyna
Dynamic RAM Read or read through inter-ring dynamic RAM locations.
is written. If the output buffer is full or the route
If the fixed cell detects an error, inter-ring dynamic RA
M is modified. Ring: 1 Operation In the following description, the multilevel memory system hierarchy described above will be described.
Preferred routing cell behavior in relation to layer structure
Describe. The route setting cell determines the type and route of the packet.
sub-page format based on root setting cell directory
packets are routed based on rules that are functions of
It can be regarded as a packet switch that performs default settings. First, subpage state, page state and route settings
Describes the state based on the file and the undetermined state.
do. Next, we introduce key rule concepts and sequence explanations.
dawn will be held. Then the complete subpage rule is given
Ru. Page operations and special operations will be explained one by one. page
Achieve page operations, special operations, and subpage operations
Explain the complete rules. Outgoing Rules Figure 13 illustrates the standard request sequence.
Defines positional terms used in the Octopus section
. Originating or parent ring: 0 contains the requesting cell.
ring: 0 and issues the original request packet.
(Step 1). If the requested subpage originates (
or local) Ring: If not enabled with 0, route setting
Cell:0 extracts the packet and routes it locally.
Fixed cell: Send to 1 (step 2). locally transmitted
Requests are sent sequentially to ring:1 by local routing cell:1
is inserted (step 3). Route setting cell: 1 is remote
ring: connected to 0 and valid for the requested subpage
It retains a copy of the data and sequentially extracts requests sent from far away.
(Step 4). Requests sent from far away are routed sequentially.
Inserted into remote ring:0 by set cell:0 (
Step 5). The response cell extracts the request and inserts the response.
(Step 6). Requests sent from far away are routed.
Extracted by set cell: 1 (step 7) and
route setting cell:1 of the toner. this route
Setting cell: 1 calls responding route setting cell: 1
and inserts the response packet into Ring:1 (step
8). Set the packet's outgoing route around Ring:1
cell:1 and the packet is extracted (step
9). The packet is routed to the outgoing ring: 0.
sent to ring:0 and inserted at ring:0 (step
10). The request sequence is an outgoing (
requests) are completed sequentially by the cells (step 11). [0338] Packets are routed according to this standard by the routing cell.
Processed 8 times during a typical sequence. Two route settings
Cell: 0 and 2 routed cells: 1 as shown in the table below
The packet source and packet origin, as illustrated in
Interpret packets in eight unique ways based on their source. Routing cell behavior and rules are
These eight combinations of packet sources and packet sources
It is constructed based on For the most part, the route setting cell
:1 locally originated packet rules are route configured.
Fixed cell: Similar to the remotely transmitted packet rule according to 1.
ing. Local ring: From the point of view of 0, the local route configuration set
local ring: 0 for remotely originated requests;
Allows 0 to logically appear as a single cell. pkt. RequestorId and
RiuCellAddress is the address where the request originates locally.
A comparison is made to determine whether the [0341] Routing Cell Subpage State Description - Preferred
New Example Subpages and Pending Requests
The state does not exist in any cache in Ring:0.
and for that non-local ring: to 0 or non-local
There is a pending request from the ring.
) However, for all subpages, the root setting cell
Stored in pairs. Routing cell: 0 responds to requests from remote ring: 0
The undetermined state is memorized. Route setting cell: 1 is
, remote ring: for local requests stuck to 0.
to store the undetermined state. Routing cells: 0 and ru
Gate setting cell: 1 both remember the subpage state
. Route setting cell: 0 and route setting cell: 1 subpeg
The page state indicates the period during which the subpage state is being updated.
It remains constant except for Rules and pending status as appropriate
Process all window cases. For the preferred implementation of the invention, the subpage status is as follows:
explain. RDU:0 (RduState0) enumeration R
DU:0 state is divided into two separate fields and
It consists of an existing field. The subpage status field is
, local ring: set of all subpages existing in 0
Describe the condition. Undetermined field is this ring: 0
Which remotely originated requests for
Describe whether. Individual states are listed in the following subsections
It is described in 0343]
RDU: 0 status field name
State Number of bits
Description Subpag
eState Invalid
2 rings:
0 subpages
Ro
situation
Next
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
Ex
　　　　　　　　　　　　　　　　　　　　　　　　　
Pend
None
2 remote
decision
Ro
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
Owner
　　　　　　　　　　　　　　　　　　　　　　　　　
[0344]SubPageState:
Inv Ring: Valid copy of any subpage in 0
– indicates that there is no such thing. [0345] SpState:Ro SpState
:Ro is one or more caps in ring:0.
pages may contain read-only copies of subpages
indicates that none of them contain owner state. Under certain circumstances, routed cell pairs can become subpages.
Read-only state (SpState:Ro)
is recorded, but the subpage is invalid with ring: 0
(SpState:Inv). Because no lead
This is because only copies do not exist in any cells.
Ru. [0346] SpState:Nex SpState
:Nex indicates the subpage owner and zero or
Read-only copies of subpages or more subpages are
Part ring: Exists in 0. zero or more leads
An only copy may exist on remote ring:0. if
, any read-only copy is outside the local ring:0
If there is no remote read-only copy
Recombination or first invalidation to indicate that there is also no
The action causes a subpage state change or transition to exclusivity.
Ku. Remote routing cells are assigned descriptors by
and did not give a signal when canceling. [0347] SpState:Ex SubpageState:Ex is local ring: 0
There are no valid copies of any subpages outside of
instruct. Local ring: 0 is any read-only
No copies or exclusive owners or zero or more
Contains a non-exclusive owner with a read-only copy
Ru. Routing cell: 0 is exclusive ownership of local cell
exclusive, atomic and transient
) Records all atomics as exclusive. Pending: NonePending
None request state pertains to the corresponding subpage
Local ring: to 0, remotely originated pending act
Indicates that there is no activity. Pend1:Ro Pendl:Ro is one far ring for local ring:0.
An sva read ro request originating from the server is pending.
Indicates that Additional remotely transmitted sv
A read ro request is executed until the request is terminated.
Partner Routing Cell with RspBsy Set
: Returned to 1. [0350] Pend1:Owner Pend1:O
wner is one or more for local ring:0.
If more than one invalidation request or remotely originated ownership request
Indicates that the In addition, one or
Further remotely originated sva readro requests
can also be considered pending. all remotely originated
Ownership requests, read-only requests, and invalidation requests are
In this state, it is sent to ring:0. ownership claim
are sva read ex, sva get and
sva getw. Invalidation request is write i
nv and lookahead invalidation. RDU:1 (RduState1) enumeration R
DU:1 state consists of three independent fields and
It consists of an existing field. The subpage status field is
, local ring: set of all subpages existing in 0
Describe the condition. Undecided field is against Ring:1
determines whether any locally originated requests are pending.
Describe. Pending 1 field satisfies the pending request.
remote originating ownership packets that were not extracted for
Routing cells: 1 missing and missing
Pending requests need to be resubmitted due to page
Describe whether (snarf, snarf). 0352]
RDU:1 state field name
State Number of bits
Description Subpag
eState Invalid
2 rings:
0 subpages
Ro
situation
Own
r
Pe
nd None
2
Ring: 0 pending
Ro
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
Owner
　　　　　　　　　　　　　　　　　　　　　　　　　
Pend 1
None 1
Ring: 0 pending
ReIssue
　　　　　　　　　　　　　　　　　　　　　　　　　
0353]
SubPageState: Inv Ring: What is in 0?
indicates that there is no valid copy of those subpages. [0354] SpState:Ro SpState
:Ro is one or more caps in ring:0.
pages may contain read-only copies of subpages
indicates that none of them contain owner state. Under certain circumstances, routed cell pairs can become subpages.
Read-only state (SpState:Ro)
was recorded, but the subpage was invalid within ring:0.
(SpState:Inv). Because no lead
This is because the only copy does not exist in any cell.
be. [0355]SubpageState:OwnerS
ubpageState:Owner is the subpage
Local ring: Exclusively (Ex) or non-exclusively within 0
Indicates that it is owned by (Nex). Local ring:
0 is an exclusive owner with no read-only copies or
or have zero or more read-only copies
Includes non-exclusive owners. Route setting cell: 1 is
Local Cell Exclusive Ownership Status Non-Exclusive, Exclusive, Attribute
Owner of all mics and transient atomics
Record as. 0356 Pending: NonePending
None request state indicates pending field and corresponding
Rings related to subpages: To 1, local origination
Indicates that there is no determining activity. Pend:Ro Pend:Ro is one local source to local ring:1.
a trusted svaread ro request is pending
instruct. Additional locally sourced sva reads
The ro request is sent to the RspBsy server until the request is terminated.
Routing cell of partner with: Returned to 1
. Pend:Owner Pend:Owner is one or more for Ring:1.
will not respond to any further invalidation requests or locally originated ownership requests.
indicates that the request is pending. In addition, one or more
Locally originated sva read ro requests
may also be pending. all locally transmitted
Ownership requests, read-only requests, and invalidation requests are
In this state, it is sent to ring:0. ownership claim
are sva read ex, sva get and
sva getw. Invalidation request is write i
nv and lookahead invalidation. [0359] Pend1: ReIssue
Pend1:
ReIssue responds to route setting cell: 1 outgoing request.
Potential non-routed cell to: 1 outgoing response packet
Route Setting Cell: Indicates that 1 can not be lost. Pe
nd1: ReIssue state satisfies pending requests
Remotely originated ownership packets not extracted for
By distinguishing between the case of a missing page and the case of a missing page, pseudo
(Spurious) Missing page error (Page
route setting cell:1 to prevent
(snarf). If route setting cell: 1
Request sent by Pendl with no response:
If it returns without reissue, the return request is routed.
Used by the configuration cell and request processor cell or rule
Causes the cell to reissue the request and creates a pseudo-penetration cell.
page errors are avoided. Pend1: Reissue
, when no locally generated requests are pending.
or first ownership (with data) response time.
will be ascribed. [0360] Routing Cell Subpage State Description - Alternative
EXAMPLE The following describes the use of a first alternative embodiment of the invention.
This is the state of the subpage to be displayed. RDU:0 (RduState0) enumeration R
The DU:0 state consists of four separate fields and
It consists of an existing field. The subpage status field is
, local ring: set of all subpages existing in 0
Describe the condition. 1 undecided field is this ring: 0
Any remotely originated sva read r
o, sva read ex, or write in
Describes whether a validate request is pending
. sva get with 2 pending fields sent remotely
Describes whether the request is pending. 3 undecided fields are
Remotely transmitted sva getw (gate and
wait, acquire and wait) whether the request is pending or not.
or an additional getw request if this request is pending.
Describe whether it was issued at the time. multiple sva
getw requests are logged and transient atomic
Inform the requesting cache of the status. [0362] The three pending fields are per subpage.
Maximum number of remotely originated pending requests for each type separately
recorded. Multiple similar types for the same subpage
requests are closed to the partner by the time the pending requests are closed.
Routing cell: Returned to 1. The individual states are:
Described in subsections. 0363 Field Name Status Bit
number theory
Ming SubpageState
Invalid 2
Ring: 0 subpage
Ro
situation
　　　　　　　　　　　　　　　　　　　　　　　　　
Next
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
Ex
　　　　　　　　　　　　　　　　　　　　　　　　　
Pend 1
None 2
remote pending
Ro
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
Ex
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
OwnerInv
　　　　　　　　　　　　　　　　　　　　　　　　　
Pend 2
None
1 Remote pending
　　　　　　　　　　　　　　　　　　　　　　　　　
Get
　　　　　　　　　　　　　　　　　　　　　　　　　
Pend 3
None 2
remote pending
Getw
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
Atomic
　　　　　　　　　　　　　　　　　　　　　　　　　
0364
SubPageState:Inv Ring:0
indicates that there is no valid copy of the page. [0365] SpState:Ro SpState
:Ro is one or more caps in ring:0.
pages may contain read-only copies of subpages
indicates that none of them contain owner state. Under certain circumstances, routed cell pairs can become subpages.
Read-only state (SpState:Ro)
was recorded, but the subpage was invalid within ring:0.
(SpState:Inv). Because no lead
This is because the only copy does not exist in any cell.
be. When there are no read-only copies,
First locally originated request, remotely originated invalid or
Read-only requests can be made remotely.
The invalid subpage state is adjusted to the invalid subpage state.
Ru. [0366] SpState:Nex SpState
:Nex indicates the subpage owner and zero or
Read-only copies of subpages or more subpages are
Part ring: Exists in 0. zero or more leads
An only copy may exist on remote ring:0. if
, any read-only copy is outside the local ring:0
If there is no remote read-only copy
Recombination or first invalidation to indicate that there is also no
, leading to a subpage state transition toward exclusivity. remote
Routing cells are used when they deallocate descriptors.
Sometimes they don't signal. [0367] SpState: Ex SubpageState: Ex is local ring: 0
There are no valid copies of any subpages outside of
instruct. Local ring: 0 is any read-only
No copies or exclusive owners or zero or more
Contains a non-exclusive owner with a read-only copy
Ru. Routing cell: 0 is exclusive ownership of local cell
exclusive, atomic and transient atomic
record all links as exclusive. [0368] Pending [1, 2, 3]: None
PendingNone Request status is pending field
local ring related to the code and corresponding subpage: 0
to ensure that there is no remotely originated pending activity.
Instruct. Pend1:Ro Pendl:Ro is a remote call to local ring:0.
sva read ro request is pending
instruct. Additional remotely originated sva reads
The ro request is sent to the RspBsy server until the request is terminated.
Routing cell of partner with: Returned to 1
. [0370] Pend1:Ex Pend1:Ex is a remote call to local ring:0.
sva read ex request is pending
instruct. Preceding remotely originated sva read
ro Request may be pending. additional remotely originated
An sva read ex request is executed until the request is terminated.
And route configuration of partner with RspBsy set
Cell: Returned to 1. [0371]Pend1:OwnerInv
Pend1:
OwnerInv is a remote call for local ring: 0.
write invalidate request or rule
write-ahead invalidation
e. lookahead, sva read ex.
lookahead, sva get. lookahe
ad or sva getw. lookahead)
Indicates that the request is pending. Preceding remote transmission
There may be pending sva read ro requests. Ring: Consecutive lookahead invalidation from 1 is empty
be done. Subsequent remotely transmitted sva reads
ex, write inv requests are used. that
Each subpage has a single owner and the owner's
only can issue a write invalidate request.
additional write disabling in this condition will cause an error condition.
Instruct. Subsequent sva read ro request is R
spBsy and duplicate data packets
is emptied. Pend2:Get Pend2:Get is the remote ring for local ring:0.
Indicates that the originated sva get request is pending.
Show. A subsequent remotely originated sva get request
, pkt. until the request is terminated. has a data set
is returned to the originating cell and the subpage is already atomic.
instruct something. Subpages are still atomic
may not exist, but before subsequent requests are completed
Become atomic. Pend3:Getw Pend3:Getw is one for local ring:0
or more remotely originated sva getw requests
indicates that it is pending. All loading required
Unlike requests, every getw request
It is not sent when it is in this state, but when it is in this state. ring: getw response from 0 if page is already attached
When specifying that it is a microphone (getw.data
．． RspBsy), Pend3: Atomic state is
recorded. [0374] Pend3: Atomic ownership package
has a pending getw request for atomic ownership.
Instructs that it is required to satisfy the requirements. Owned caches are transient atomic
It is guaranteed to be in the state (tat). continued remoteness
The originated getw or get request is returned and the sub
Indicates that the page is already atomic. Pull
Continued ring: 0 ownership packets (release.d
ata or sva readex. data) is extracted
and send to the other ring that is pending atomic:0
sent to Ring:1 (RRC:1 Pend3:
Atomic). [0375] Pend3: Atomic has two conditions.
is set under. First, the getw response
This is the time to specify that it is atomic. Second
, remotely activated releases. data is the ring
:0, Pend3:Atomic is set, and the rule is set.
Other rings where 0 is pending atomic
:0, followed by release. data
It is time to extract the release. data is
, if the ring:0 cell is atomized by a remote originating release.
Once ownership of the network has been acquired, a local transmission will be made. RDU:1 (RduState1) enumeration R
DU:1 state consists of 6 independent fields
. The subpage state field is set for all subpages present in local ring:0.
Collective state and whether owner invalidation is in progress
Describe. Pend1a field is locally transmitted
sva read ro request is pending on ring:1
Describe the meaning. Pend1b field indicates local transmission
sva read ex request is pending on ring:1
Describe whether or not the decision is made. Pend2 field
but a locally originated sva get request is pending
Describe whether or not. Pend3 field is one
Are locally originated sva getw requests pending?
Is there any additional getw request if this request is pending?
Describe whether it was issued during a certain period of time. multiple sva
getw requests are logged and transferred to the request cache
signals an atomic state accordingly. Pend5 Fu
field is not extracted to satisfy a pending request.
Cells that route remotely originated ownership packets: 1
Due to missing and missing pages,
Describes whether a pending request should be resubmitted
(Snarf, snarf). [0377] The five pending fields are independently
Maximum of locally originated pending requests of each type, one per page
The number was recorded. Multiple requests of similar type are busy
, the partner's route configuration will take place before the pending request is closed.
returned to the fixed cell. 0378 Field Name Status Bit
number theory
Ming SubpageState
Invalid 2
Ring: 0 subpage
Ro
situation
　　　　　　　　　　　　　　　　　　　　　　　　　
Owner
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
OwnerInvalidtg
　　　　　　　　　　　　　　　　　　　　　　　　　
Pend1a
None 1
Ring: 0 pending
Ro
　　　　　　　　　　　　　　　　　　　　　　　　　
Pend1
b None
1 ring
:0 undecided
Ex
　　　　　　　　　　　　　　　　　　　　　　　　　
Pend2
None 1
Ring: 0 pending
Get
　　　　　　　　　　　　　　　　　　　　　　　　　
Pend3
None
2 rings:
0 undecided
Getw
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
Atomic
　　　　　　　　　　　　　　　　　　　　　　　　　
Pend4 No.
ne 1
Ring: 0 pending
ReIssue
　　　　　　　　　　　　　　　　　　　　　　　　　
[0379]SubP
ageState:Inv Ring:No sub in 0
Indicates that there is also no valid copy of the page. [0380] SpState:Ro SpState
:Ro is one or more caps in ring:0.
pages may contain read-only copies of subpages
indicates that none of them contain owner state. Under certain circumstances, routed cell pairs can become subpages.
Read-only state (SpState:Ro)
was recorded, but the subpage was invalid within ring:0.
(SpState:Inv). Because no lead
This is because the only copy does not exist in any cell.
be. When there are no read-only copies,
First locally originated request, remotely originated invalid or
Read-only requests can be made remotely.
The invalid subpage state is adjusted to the invalid subpage state.
Ru. [0381]SubpageState:OwnerS
ubpageState:Owner is the subpage
Local ring: Exclusively (Ex) or non-exclusively within 0
Indicates that it is owned by (Nex). Local ring:
0 is an exclusive owner with no read-only copies or
or have zero or more read-only copies
Includes non-exclusive owners. Route setting cell: 1 is
Local cell ownership status: non-exclusive, exclusive, atomic
all locks and transient atomics with their owners.
and record it. [0382]SubpageState:OwnerI
nvalidatingPend1:OwnerInv
is a remotely originated write to local ring:1
Indicates that an invalidate request is pending.
Ru. Each subpage has a single owner and
Cannot issue a write invalidate request.
Therefore, additional write invalid in this state
dates indicates an error condition. sva read ex, sva read get
or implied by sva read getw
The invalidations are Pend1b:Ex and Pend1b:Ex, respectively.
2: Get or Pend 3: Recorded as Getw state.
will be recorded. Continued locally transmitted sva rea
The d ro request is marked RspBsy and
Duplicate data packets are emptied. [0383] Pending [1a, 1b, 2, 3]:
None Pending: None request status is pending.
Rings related to fields and corresponding subpages
: To 1, there are no locally originated pending activities.
to instruct. [0384] Pend1a:Ro Pendl:Ro is the locally transmitted signal for Ring:1.
sva read ro Indicates that the request is pending.
Show. Additional locally sourced sva read r
o The request is terminated by the RspBsy set.
partner's routing cell with: Returned to 1. Pend1b:Ex Pend1:Ex is the locally transmitted signal for Ring:1.
sva read ex request is pending.
Show. Additional remotely originated sva read e
x request is terminated by the RspBsy set.
Routing cell of partner with: Returned to 0. [0386] Pend2:Get Pend2:Get is the local transmission for ring:1.
sva get request is pending.
Ru. A subsequent remotely originated sva get request
By the time the request is terminated, pkt. has a data set
is returned to the local originating cell and the subpage is already atomic.
Indicates that the Subpages are still atomic
may not be completed, but before subsequent requests are completed.
becomes atomic. Pend3:Getw Pend3:Getw is one for local ring:0.
or more locally originated sva getw requests
indicates that it is pending. All other reading requirements
Unlike requests, every getw request
It is not sent when it is in this state, but when it is in this state. ring: getw response from 1 indicates page is already attached
When specifying that it is a microphone (getw.data
．． RspBsy), Pend3: Atomic state is
recorded. [0388] Pend3: Atomic ownership packet
satisfies the pending getw request for atomic ownership.
Indicates what is required to be added. Owned caches are transient atomic
It is guaranteed to be in the state (tat). continued remoteness
The originated getw or get request is returned and the sub
Indicates that the page is already atomic. Pull
Continued ring: 0 ownership packets (release.d
ata or sva readex. data) is extracted
and send to the other ring that is pending atomic:0
sent to Ring:1 (RRC:1 Pend3:
Atomic). Pend3: Atomic is one more
is that further getw requests are still pending
is not guaranteed. [0389] Pend3: Atomic has two conditions.
is set under. First, the getw response
This is the time to specify that it is atomic. Second
, remotely activated releases. data is the ring
:0, Pend3:Atomic is set, and the rule is set.
Other rings where 0 is pending atomic
:0, followed by release. data
(RRC:1 Pend3:A
tomic). release. data is
G: Atomic ownership with the release of 0 cells being remotely transmitted
If it is obtained, it will be transmitted locally. 0390] Pend4: ReIssue Pend4
:ReIssue is route setting cell:1 for outgoing request.
Potential non-routed cells for: 1 outgoing response packet
Route the cell: 1 to indicate that you will not lose or gain. P
end4: ReIssue state satisfies pending requests.
Remotely originated ownership packets that were not extracted to
By distinguishing between missing pages and missing pages, pseudo
(spurious) missing page error (page error)
route setting cell: 1 to avoid
(snarf). If the routed cell:
If the request issued by Pend 1 has no response and
:If it returns without Reissue, the return request will be routed.
The requested processor cell or
Causes the routing cell to reissue the request and creates a pseudo
Page errors are avoided. Pend4: Reissue
when no locally generated requests are pending.
or click during the first ownership (with data) response time.
will be ascribed. [0391] Routing Cell Subpage State Description - Alternative
Example 2 What follows is used in a second alternative embodiment of the invention.
This is the state of the subpage to be displayed. 0392] Subpage State Subpage
Information related to the routing cell about the state
I will explain it. [0393] Invalid: Inv invalid subpage
The state is: There is no valid copy of the subpage in the ring:0
Indicate that there is no such thing. Read Only (Ro) The read only state is one or more of Ring:0.
Read-only copy of subpage with more cache
Indicates that it may include. Routing cells are recorded
When the read-only state is read-only, the
cache contains read-only copies of subpages
It is possible to Last retained specific subpage
cache deallocates descriptors
but another cache with ring:0 is allocated
Contains descriptors for similar system virtual address pages.
In this case, the routing cell is not notified immediately and
Temporarily maintains a read-only state. Another case is r
ecombine. nex. data is ring: from 0
Under rare circumstances (e.g., pending lead orders)
The route setting cell for the request (PlRo) is the lead
Considering that only copy can exist in ring:0
It is a must. Usually recombi
ne. nex. inv busy claim is subpage
Indicates that a read-only copy of the file exists. what
If there are no read-only copies of the first
A read-only request or a remote read-only request
Adjust subpage state to invalid subpage state
be done. Non-exclusive (Nex) The non-exclusive state indicates the subpage owner and has zero or
read-only copy of further subpages is local
Ring: Exists at 0. Zero or more lead-offs
A free copy may exist in a remote ring:0. if,
Any read-only copies will be outside of the local ring:0.
If it does not exist, there is a read-only copy that is not far away.
At recombination or first invalidation, which tells you to
Causes a subpage state transition to sex. remote routing
Cells signal when they deallocate descriptors
I didn't. Exclusive (Ex) The exclusive state means that there are no subpenets outside the local ring:0.
indicates that there is also no valid copy of the page. local ring
:0 means exclusive or non-exclusive owner and zero or
Contains further read-only copies. Route setting
The local cell is exclusive, which is the exclusive ownership state of the local cell.
Eliminate all atomics and transient atomics.
Record it as something else. [0397] Pending request subpage state The pending request state indicates the type of pending request and whether additional requests have been deleted.
whether the request needs to be reissued
or whether the request was completed and the routing cell
is waiting for the original request to be returned.
Instruct. A value of 0 or 1 for # is pending, respectively.
Indicate ring:0 or ring:1, respectively. 0398] Pend: None (P#None) P
endingNone The request status is the corresponding subpage.
indicates that there is no pending activity related to the
Show. PendWait(P#Wait)PendingWa
it is a read request (sva read {ro,
nex, ex}, get, getw) is still pending.
, but a response or a response to be erased has already been issued.
Instruct the person to do the following. When a return request packet is received
, the packet is freed and pending requests are terminated. If the return request packet contains data and ownership
If so, the error should be signaled. [0400]PendWaitMergeRo(P#W
aitMrgRo) PendWaitMergeRo
If the read request is still pending and one
or more sva readro. nodata
packet(s) is deleted while waiting for a return request.
Indicate what is being left out. The second request is the first request
cannot be issued until it is finalized. return request packet
When received, the packet is considered free and any pending requests are
terminated and an sva read ro request is normally issued.
will be carried out. If the return request packet is data and ownership
an error should be signaled. [0401]PendWaitMergeEx(P#W
aitMrgEx)PendWaitMergeEx
If the read request is still pending and one
or higher sva readex. nodata
packet(s) is deleted while waiting for a return request.
indicates that it has been removed. Pending states are always cleared.
This condition is further reduced to zero as we acknowledge the strongest request
or more sva read ro packets to be erased
Including cuts. The second request is terminated until the first request is terminated.
It cannot be issued. When a return request packet is received
, the packet is freed, pending requests are terminated, and
A sva read ex request is typically issued. if
If the return request packet contains data and ownership,
Errors should be signaled. [0402]PendWaitMergeAt(P#W
aitMrgAt)PendWaitMergeAt
If the read request is still pending and one
or more {get, getw}. nodata
packet(s) is deleted while waiting for a return request.
indicates that it has been removed. Pending states are always cleared.
This condition is further reduced to zero as we acknowledge the strongest request
or more to be erased sva read{ro, ex
} Contains packets. The second request ends, the first request ends.
It cannot be published until it is done. A return request packet is received.
the packet is freed and pending requests are terminated.
and a getw request is normally issued. If you request a return
If the packet contains data and ownership, errors will be
should be illustrated. 0403] PendReIssue (P#Rei)
PendReIssue
The read request is pending and the request returns
Indicates when it should be reissued. This state is typically requested on event detection while a request is pending.
is returned with no response or the response is stale data.
Charged when indicating to return with. and
For example, if sva read ro is pending and
If invalidation is detected, the returned data will be stale.
. Sometimes pendreissue status is charged
, local ring: 0 transactions, remote ring:
completed before the transfer of ownership to 0. [0404]PendReissueMergeRo(
P#ReiMrgRo) PendReissueMer
geRo indicates that a read request is pending and the request is
should be reissued when it returns and one too
is more than sva read ro. nodata
packet(s) erased while waiting for return request
Indicate what is being done. Pending states are always cleared.
This condition is further reduced to zero by granting the strongest request.
or more sva read ro packets to be erased.
Including. the second request until the first request is terminated.
cannot be issued. when a return request packet is received
, the packet is empty and the stronger erased svar
ead ro or pending request is reissued. [0405]PendReissueMergeEx(
P#ReiMrgEx) PendReissueMer
geEx indicates that a read request is pending and the request is
should be reissued when it returns and one too
is a further sva read ex. nodata
packet(s) erased while waiting for return request
Indicate what is being done. Pending states are always cleared.
This condition is further reduced to zero by granting the strongest request.
or more sva read ro packets to be erased.
Including. the second request until the first request is terminated.
cannot be issued. when a return request packet is received
, the packet is empty and the stronger erased svar
The ead ex or pending request is reissued. [0406]PendReissueMergeAt(
P#ReiMrgAt)PendReissueMer
geAt indicates that a read request is pending and the request is
should be reissued when it returns and one too
is more than {get, getw}. nodatap
acket(s) cleared while waiting for return request
Indicate what is being done. Pending states are always cleared.
This condition is further reduced to zero by granting the strongest request.
or more erased sva read {ro, ex
}Contains packets. The second request is completed when the first request is completed.
It cannot be issued until it is completed. Return request packet is received
When the packet is empty, the getw request recurs.
will be carried out. [0407] PendRo (P#Ro) PendRo is
, sva read ro indicates that the request is pending.
Show. sv received during any pending ro state
A read ex request is ReissueMerge
Invites conversion to Ex pending state. [0408] PendRoMergeRo(P#RoM
rgRo) PendRoMergeRo is sva
read ro request is pending and one or more
sva read ro. nodata pa
cket(s) is cleared while waiting for a return request.
Indicate what is being done. [0409] When a return request is received, the packet is
Marked as erased. In any pending ro state
An sva read ex request that is also received is
sueMergeEx Causes conversion to pending state. [0410] PendEx (P#Ex) PendEx is
, sva read ex indicates that the request is pending.
Show. [0411]PendExMerge(P#ExMrg
) PendExMerge is sva read e
x request is pending and sva read {ro
, ex} indicates that the request is deleted. Need to return
When a request is received, the packet is marked as erased.
It will be done. [0412]PendExMergeAt(P#ExM
rgAt) PendExMerge is sva re
ad ex request is pending and get or g
Indicates that the etw request is being deleted. When a return request is received, the packet is marked erased
be attached. 0413]PendAtomic(P#At)Pen
dAtomic has a pending get or getw request.
or getw. nodata response returned
Instruct that there is. [0414]PendAtomic(P#AtMrg)
PendAtomic requires get or getw
pending request or getw. nodata response
The answer is returned and get, getw and
The sva read {ro, ex} request is cleared.
Instruct that there is. When a return request is received, the
mark as erased. [0415]PendRecombine(P#Rec
) PendRecombine
e. data. {tat, at, ex, nex} is local
Ring: From 0 to undetermined or pending status.
Instruct. PendRecombine is an RDU
:1 is only used. 0416]PendMrsp(P1Mrsp)Pen
dMrsp contains the request to be erased from this ring:0
indicates that a response is currently circulating on Ring:0.
Ru. This request to be erased from ring:0 is Rdu:1
P0RoMrg*, P0ExMrg* or
or P0AtMrg. Pe
Set the cell transaction completion criteria during ndMrsp.
Additional sva read requests become free to satisfy
be done. [0417]PendMrspMrgRo(P#Mrs
pMrgRo)PendMrspMrgRo
Ring: The response containing the request to be erased from 0 is Ring:
0 currently in circulation and during this period remote sva
read ro Indicates that the request is being erased
. [0418]PendMrspMrgEx(P#Mrs
pMrgEx)PendMrspMrgEx
Ring: The response containing the request to be erased from 0 is Ring:
0 currently in circulation and during this period remote sva
read ex request and svaread ro required
Indicates that the requested request has been deleted. [0419]PendMrspMrgAt(P#Mrs
pMrgAt)PendMrspMrgAt
Ring: The response containing the request to be erased from 0 is Ring:
Currently in circulation at 0 and during this period, remote get
or getw and sva read ex also
means that the sva read ro request has been deleted
instruct. PendInvalidate(PInv
) PendInvalidate is a pending write.
invalidate, write invalida
te. Indicates that lookahead is pending.
Ru. sva read {ro, ex}, get or
The invalidation implied by getw is PendRo, Pe
Recorded as ndEx or PendAt state. [0421] RDU:0 state (RduState0) column
RduState0 is ring:0 service.
page state and ring: 1 pending request (remote ring
(starting from 0). Ring:0 subpage state and Ring:1 pending state
Illegal combinations are shown as dashed lines. that
Each RduState1 is a ring:1 pending state name.
as a suffix after the Ring:0 subpage state.
The name is given by RDU used in this alternative embodiment: 0
A table showing the pending status is illustrated in FIG. [0423] RDU:1 state (RduState1) column
RduState1 is the ring:1 subpage state and
ring: 0 status of pending requests (from remote ring 0)
Remember. Ring:0 subpage state and Ring:0 pending state
Illegal combinations are shown as dashed lines. that
Each RduState1 is a ring:1 pending state name.
as a suffix to the Ring:0 subpage state.
The name is given by used in this alternative embodiment.
RDU: 1 A table showing the status is illustrated in Figure 18.
There is. Page Status The descriptions in the sections that follow describe the preferred (as opposed to alternative embodiment)
Assumes the use of new subpage states. 0425] Owner limit (Owner limit, Own
rLimit) OwnerLimit is set by software or
Cleared and locally linked ownership of subpages within the page
G: Limit to 0. It is routed cell: 0 and
Route setting cell: Stored in both 1. when clearing
, OwnerLimit is both ring: 0 and sub
Identify that you can own the page. When configuring it,
is local ring: only cells in 0 are non-exclusive, exclusive,
Atomic or Transient Atomic State Sub
Identify that you can own the page. Remote ring: 0
can receive read-only copies. OwnerLi
When mit is set, a page fault is
Return request with Bsy and RspBsy clear
The ownership request is signaled by the root setup cell. Own
When erLimit is set, the rejoin request is
Local ring: does not propagate beyond 0. route setting cell
The default state for descriptor allocation is cleared.
It will be done. 0426 Ownerlimit Nemo
nick description
0 OL: All
local phosphorus
G: limited to 0
　　　　　　　　　　　　　　　　　　　　　　　　　
ownership rights
1 OL: Lo
cal local
Ring: limited to 0
　　　　　　　　　　　　　　　　　　　　　　　　　
ownership rights
[0427] DupLimit DupLimit is the duplicate. data is
A provision that allows the data to be sent from local ring: 0 to ring: 1.
Identify the issue. DupLimit is route setting cell: 0
Stored by DupLimit
mnemonic
Description 0
Dup:CondForward
Conditional feed motion
1 Dup:
AllForward always
Send to [0428]Du
p: Duplic in CondForward page
ate. data packet, if the page is local ring
:root configuration, unless owned exclusively by 0
Conditionally sent to ring 1 by cell:0. Dup:
CondForward assigns the route configuration cell descriptor
This is the default state for guessing. [0429]Dup:AllForwardDupli
cate. data is always reset by route setting cell: 0
ng: Sent to 1. Pending Request Page Status How does a pending route setting cell operation
SVA request to which subpage within the page is the setting cell
Decide what to do with it. Corresponding Level3VEN
The pending request page state field of the try contains this pending information.
Identify. Page: None Any pending page-level route setting cell operations are also supported.
No progress on descriptors. Page: None
is the default for routing cell descriptor allocation.
state. 0432]Page:PendDeallocate
In route setting cell:0, the route setting cell pair is
Whether the descriptor should be deallocated or its rules
Set cell: 1 signals to deallocate the descriptor.
indicates that they are in the process of determining whether
. Route setting cell: Within 1, the route setting cell pair is a descriptor
is in the process of deallocating. [0433] The route setting cell descriptor is
in response to a single cell indicating that it is being unassigned.
Answer and go to Page:PendDeallocate
Convert. If the descriptor is in any cell in Ring:0
If not present, route setting cell: 0 and route setting
Cell:1 deallocates the descriptor. ciu inv
sum. no data, ciu invsum a
locate. no data and ciuex
sum. Other page-level packages such as nodata
The port is said to be busy during this state. Remotely transmitted services
If the page request is routed to routed cell: 0 and routed
1: Busy. Locally transmitted subpage
request is not executed in the rooting cell:0. Na
If the local cache you are requesting is an allocation descriptor
and the routing cell pair assigns its descriptor.
This is because it avoids removing the data. Locally transmitted subpe
The route request is busy by route setting cell:1. Because routed cell pairs deallocate descriptors.
This is because they are inclined to The descriptor is
After being unassigned, the next request will continue to cause reallocation.
be exposed. [0434] Other RRC Status The following status fields are
Stored based on a fixed cell bank. These state files
unless otherwise declared or mentioned.
Applies broadly to all subpages and pages
. Extract Buffer Status Ring Extract buffer free space can be configured in two ways.
Pointer ExtractAllThreshold
and ExtractRspThreshold
It is divided into four bands. The current band is in the extraction buffer
The selection is based on the number of free words remaining. from vacancy
The band going full is ExtBuf. All, ExtB
uf:NonOpt, ExtBuf:PendReq
and ExtBuf:Full. extraction buffer
State is maintained based on the routed cell bank
. These band boundaries are software configurable.
be. Ring packets are used to manage extraction buffers.
, grouped into three mutually exclusive categories
. 0436]1) Optional packet continuation
Packets that are transmitted over a long distance are
is optional: -Recombine with SpState: (
Inv | Ro) -Duplicate. data S
pState: Inv-sva read ro. da
ta with SpState:Inv 2) Non-op
packet A packet that completes a remotely originated request.
must be extracted based on SpState in order to
do not have. Does not include optional packets. 3) Response packet locally sourced
Packets to be transmitted or Route Setting Cell Pending Requests (RR)
C: 0 Pend (1, 2, 3), RRC: 1 Pen
Packet satisfying d (1, 2, 3, 4, 5)) 04
37] There are four packet categories as follows:
Processed with extraction buffer bandwidth of 0438 Bandwidth Optional
non-optional
response packet
packet
Packet ExtBuf reception
acceptance
acceptance
:All
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
Ex
tBuf:N passing
acceptance
Acceptance onOpt
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
ExtBuf: P passing
passing and claiming
Acceptance endReq
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
ExtBuf:F pass
passing and claiming
Passing u
ll
RspBsy, InvBsy
Text reference
　　　　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　　　　　　　　　　　　　
0439] ExtBuf:
All ExtBuf: All bands are free and Extract
It is between AllThreshold. all pa
Kate is ExBuf. Accepted in All band. [0440] ExtBuf: NonOpt ExtBu
f: NonOpt band is ExtractAllThr
eshold and ExtractResponseTh
during reshold. Non-optional packet
and response packets are accepted in this band. optioner
If the packet is not accepted, the packet is not accepted.
No diagrams are required either. [0441]ExtBuf:PendReqExtBu
f: PendReq band is ExtractRespon
seThreshold and extract buffer
r full . Only response packets are sent to this band.
accepted by the community. Non-optional packets are RspBs
Rejected by the arguments of y and InvBsy. Op
If the packet is not accepted, what should the packet do?
Signals from them are also not required. [0442] ExtBuf:Full ExtBuf:
Full band is when the extraction buffer is full
. No packets are accepted into this band. Non-O
The optional packets are RspBsy and InvBsy.
rejected by the argument. Optional packets received
If not, no signal in the packet is required.
Not possible. A locally transmitted packet is pkt. TimeS
It is passed along with tampclear. packet
will be extracted by this routing cell at the next ring turn.
It will be done. to remotely transmitted response packets that carry no data.
Both RspBsy and InvBsy are set for
It will be done. Remotely originated responses with read-only data
The packet is passed. Ownership response packet sent remotely
routed cell: 1 is Pend1
:Convert to ReIssue. [0443] Pend1: ReIssue status is
remote-originated data that was not extracted to satisfy the resolution request.
Distinguish between lost ownership packets and missing page cases.
Therefore, spurious missing pa
route to avoid ge errors (page faults)
Setting cell: Used by 1. When setting, Pend
1: Reissue is the root setting cell: 1 is the root
A potential non-routed cell origination request for a configured cell origination request.
Indicates that transmission response packets may be lost. if root
Config Cell: If a request issued by 1 does not result in any response and
Pend1: If it returns without Reissue, return request
is said to be busy by the routing cell and the request processor
Causes the cell or routing cell to reissue the request.
, pseudo page faults are avoided. Route settings
Cell: 0 uses SpState field, mi
ssing page error is avoided. Roux
Setting cell: 0SpState field specifies the request.
Read-only copy or ownership removed to satisfy
Record whether it is at 0. If the route settings
If a request originated by: 0 returns unanswered and
If there are sufficient copies or ownership of 0, then the request
will be reissued. Ring Frozen State In addition to the following mention, the route setting cell is marked as frozen.
must maintain track of the first and last packets sent.
No. [0445] Fz:None Fz:None indicates that the route setting cell is a ring freeze sequence.
to indicate that something is not in the context. 0446]Fz:SingleEccErr This parameter
During the lookup sequence corresponding to the packet time, the modification
Indicates that a possible Ecc error has been detected. Ring: 1 Beginning of freezing sequence. Always the next packet
Conversion to Fz:Freeze during freezing time. Corresponding package
The cut is processed as described in the extract buffer full section.
be done. Fz:Freeze Indicates that the route setting cell is in a ring freeze sequence.
Show. All not previously marked as frozen
Packets are marked frozen. [0448] Fz: Unfreeze route setting cell
indicates that the ring freezing sequence has ended. Below
All packets previously marked frozen are now unfrozen
and is normally handled by the route setting cell.
be done. Any condition that triggers a ring freezing sequence
Fz:SingleEccErr or Fz:Fre
It would be a transition to an eze state. Fundamentals of Rule Tables Ownership The basis of strong ordering is based on the concept of rule ownership. memo
Each subpage of a resource has a single owner
. For subpage values to be modified, the owner
All copies of subpages are disabled
It must be exclusive. subpage lee
When a do-only copy exists, the owner is non-exclusive.
Yes, and subpages cannot be modified. Subpage ownership
rights are the owning cache's dynamics about subpages.
cache in a safe home or retreat.
can be dynamically transferred between Memory devices and routes
The settings for cells are based in detail on the nature of the inclusion. Route settings
Cell directory contains all subpages of ring:0
status and ring: charged at 0 or ring: removed from 0
Maintains track of the status of all pending requests. Other Concept Owners and Invalidation Requests All Owner Requests and Writes
The only invalidation request depends on whether any other requests are pending.
Regardless, go to the cell that you own completely. all
The owner requests and invalidates the packet when it is inserted into the ring.
When the route setting cell is sent to Pend:Owner
Let's go. That is, route setting cell:1 is
When the ket is inserted into Ring:1, Pend:Ow
go to ner, and route setting cell:0 is it
When inserting a packet into Ring:0, Pend:Ow
Go to ner. A route setting cell is a Pen in the following cases:
Convert from d:Owner to Pend:None
. 1 - The packet carried by the owner is sent by the routing cell.
Extracted. 2-SpState: (Inv|Ro)
The route setting cell with pkt. ! Have InvBsy
Extract invalidation or remote owner requests. 3-SpState: Route configuration set with Owner
pkt. ! Remotely originated with InvBsy
Extract invalidations. 4 - Page destruction always occurs along with allocated pages
, Local Routing Cell: 0 and Routing Cell: 1 or
and all remote routed cells: all in one page
For the subpages of SpState:Inv and
and Pend: None. all pending states
, so that page faults are signaled to other pending requests.
Cleared (request is otherwise busy and pulled)
(or time will run out). Read-Only Request A read-only request that is locally transmitted is if RC:1 is
Pend: If not Ro, local route setting cell: 1
It is only inserted by . This is the link to ring:1
and the result is a flood of numerous similar requests to responders.
This is the best way to avoid this. Such a request
Instead of inserting the route setting cell:1 extract it
and pkt. Set RspBsy. By the way, response
Route setting cell in answerer: 0 leads on in this way
Do not reject Lee's requests. Instead, read-only
Requests are inserted at ring:0. [0453] A route setting cell is a place that carries packets.
The read-only data carrying the owner or packet is
When extracted by the routing cell, Pend:Ro
to Pend:None. [0454] Packet carrying read-only data
However, it is a route setting cell in Pend:Owner state.
It is "erased" when passing through. sva read
ro packet is sent to pkt. Setting RspBsy
is "erased" and duplicated by
It is considered vacant. Clear operation and packet busy bit
Interpretation RspBsy is the response to the request packet with data.
It can always be cleared when answering. [0456] InvBsy is the output from the outgoing ring:0.
Always clear when starting. Because the route settings
le:0, if pkt. If InvBsy, the packet
This is because it does not extract the Routing cells are packets
and pkt. InvBsy, RspBsy
Set to cause the request to be reissued. InvBsy
is remote ownership claim or invalidation remote ring: 0
Always clear when charging. Because root
Setting cell: 1 if pkt. If InvBsy,
This is because the requirements are not extracted. Route setting cell: 1 is pa
through the pkt. InvBsy. RspBs
Set y to cause the request to be reissued. look
Ahead effectively continues and SpState:Ro
Remaining rings held: Start invalidating with 0. Packet route setting cell bit usage sv
Use with a read ro if the request is completed.
If not, the calling or routing cell
reissue to indicate that the packet should be reissued.
Coupling and uncoupling are performed. Pkt. rrc has two
used in a manner. [0458]Pkt. rrc is the route setting cell: 0
Rather than prematurely extracting the packet, svar
ead ro. no data or recombi
ne. Allow requests for data to cross all rings:0
and used to ensure that requests are completed locally
be done. Pkt. rrc is the locally transmitted sva
read ro. nodata or recombi
ne. When data passes through route setting cell: 0
Set. If the request completes before returning to the originating cell,
If not (sva read ro.data or
recombine. no data), the originating cell is
Pass the packet. Route configuration cell: 0 is the packet with set rcc.
extract the cut and process the request normally. 0459 Route setting cell: 0 or route setting cell
:1 makes a request (called snarf) to satisfy a pending request.
(recombined), non-originated recomb
ine. data (non-originated recombined data) or r
release. Unable to extract data (open data)
When the rrc bit is set so that the packet can be recirculated
Set. If release. data is the originating cell
If it returns, it must be reissued. If rel
ease. If data is extracted by another cell, what
No further action is required. Because transition
The atomic subpage state is saved so another
This is because a release is issued (tat). recom
Bine. data should be extracted by any cell.
and passed by the originating CIU for reissue.
conduct. [0460] Pkt. rrc is always initialized to clear
and passed by the CCU and CIU. it is,
When a locally originated packet is extracted, the routing cell:
Cleared by 0. [0461] Invalidation method Multiple types of packets cause invalidation of read-only copy.
Strain. Write-invalidate produces an explicit invalidation.
Same, sva-read-ex, get and getw package
A cut results in an implicit invalidation in addition to a read request. All invalidations are performed in two ways:
Disable mode-only copy. In the first method,
Validate packets contain all lead-ons that they pass through.
Disable copying. In the second method sva-re
ad-ro sends a request with an invalidate packet
, the requester claims rsp-busy and sends the packet.
indicates that the data in the page has been invalidated, and the fake page
Prevent damage defects. duplicate-data is not yet
If you send a request with processing invalidation, the packet will be empty.
be made into The first method is to disable all cells or RRC
However, in the second method, the old read-only data is already invalid.
prevent transmission to cells that are set to 0462 Strong sequential unity and strong order of events
In order to maintain all subpages, the invalidator
Subpage B is invalidated before updating and distributing
I have to be there. If invalidate packet
Each ring: invalidated if processed serially by 0
Time all rings with subpage copies: 0
This will be the sum of the ring transition times. Moshi Invalidate
is just copied by each RRC:1, the subpage
The invalidation of page A means that the original invalidator is
page B and it still has subpage A disabled.
Not guaranteed to be completed before distribution to processors
Not done. All processors access subpage A in the same order
, we see no change to B, so strong order is violated. [0463] Invalidate - called lookahead
The technique is to disable all rings in parallel: 0, but the event
maintain a strong order. The invalidate packet is
When reaching the first RRC:1,
This packet is copied and sent to Ring:1, and then
The lookahead packets are ring: 1 packet.
Ring by setting Quarhead mode: 1 on
generated. Lookahead packet is SpState
:Ro is copied by each RRC:1 and the true request
read-only copy before the strike packet gets there
- Disable. The original request packet is the subsequent RR
Once C:1 is reached, the packet passes through at Ring:1 speed.
, this means invalidating the lookahead
This is because it has been completed in advance by the de-packet. Rutsu
Quahead packets are always considered short packets. FIGS. 14A and 14B show preferred rings:
1 Indicates the invalidation order. Write-Invalidate
If RDU:0 SpState is Nex
is extracted from ring:o (step 2), and sva
-(read-ex, get, getw) is RDU:
0 Ring if SpState is not Nex:
extracted from o. The packet is sent to RRC:1,
Ring: 1 is inserted (step 3). of subpages
First RRC with read-only copy: 1 is packet
Copy the cut and set the lookahead mode to non-lookahead.
mode and sends the packet to ring:0 (send
Step 5). Passed ring: Packet generation mode of 1
remains unchanged. Subsequent RRs with read-only status
C:1 commands the invalidate-lookahead packet.
(steps 6, 7, 8, 9). Invalidate
- Lookahead is sent to ring:0, inserted and its
and PendState is a transition to OwnInv
. When the ring:0 is invalidated, SpState is in
Transition to v and PendState transition to none
, the packet returns to RRC:1 and RDU:1Sp
State is updated to inv and lookahead packet
empty (steps 13, 14, 15, 16). [0465] On the other hand, the first RCC:1 and its corresponding
ring: When 1 completes the invalidation or ownership response, the packet is
is inserted into Ring:1 in a non-lookahead state (step
Step 12). This non-lookahead packet was
Invalidation was completed by lookahead packet in
If subsequent RRC:1 (and corresponding Ring:1) is encountered
then this packet is sent at full ring:1 rate.
(Steps 17, 18, 19, 20). If the actual
Invalidate - the actual value before the lookahead is completed
When the invalidate arrives, the actual invalidate is
Ring: 0 also passes through. The lookahead packet is
When RRCi reaches RRC:1, the packet
is emptied (step 11). non-lookahead or
The generated lookahead packet reaches the required RRC:1.
Once reached, it is extracted and sent to the requesting ring:0
(step 22) and returned to the requester (step 22).
24). [0466] False RRCSpState: If there is Ro
The RRC pair is in read-only state for subpages.
(SpState:Ro) is recorded, but which cell
Since there is no read-only copy in subpage
is invalid in ring:0 (SpState:inv
). The RRC pair is the last cache in ring:0.
disk only when unassigning the corresponding descriptor.
deallocate. Cash
When a descriptor is deallocated by a descriptor, the
What is the status of the subpage? Disabled or read-only
. When the cache allocates a descriptor, it
Do-only copies are simply erased, but RRC is not involved.
Not notified of individual read-only subpages. child
Then, other caches in ring:0 were allocated.
If the cache has a descriptor
Remove the allocation and read the subpage within ring:0.
If only copies are erased, RRC will
Still incorrectly remembering read-only state for
do. Another example is when the non-exclusive packet recombination state is
Leaving :0, there is also a read-only copy inside ring :0.
If present, RRC:0 and RRC:1 are SpSta
This is the case when te:Ro must be recorded. fake ri
The code-only state is SpState: (Inv | Ro)
Take a copy of a read-only data packet when
Corrected by RRC:1. [0467] Read-only copies of duplicate distribution subpages can be created in two ways.
cache. The copy is
When locally allocated and SpState: (
Inv | Ro), any RRC: 1 or read
Copy packets originating remotely that have only data
distributed internally by the cache that Therefore,
The copy has RRC:1 (carries read-only data)
all the packets are bound to (send it to ring:1)
Ring: 0, so read-only requests
The number of strikes will be reduced. [0468] Duplicate data packet is DupL
Sent based on imit. Moshi Dup: Cond
Forward, the page is local ring: 0
Duplicate, provided that it is not exclusively owned.
The request packet is sent to Ring:1 by RRC:0.
It will be done. If Dup:AllForward,
Uplicate packets are always ringed by RRC:0:
Sent to 1. Ring: 1 duplicate data packet
The cut is the page it corresponds to inside the local ring:0
Also when you have a descriptor assigned to E
xtractBuffer is ExtBuf: All area
is copied by the remote RRC:1 when [0469]Pkt. pcopy is set by RRC:1
The packet was copied from Ring:1.
shows. Copy by ring:1 with pcopy set
packets are returned to RRC:1 or Ring:1
No need, RR after successfully passing ring R:1
Empty by C:0. [0470] Recombining (Recombining) The recombining data packet is
If no other cells accept recombining,
Outgoing ring: Sent from 0. RRC:1 means that the packet
Departure Ro request with false RRCSpState:Ro
The starting ring in a similar manner as for: sent from 0
decide what needs to be done. recombiner day
On the first pass of the data, RRC:0 is pkt. Set RRC
to Moshi recombine no data rrc departs
Upon returning to the cell, the recombining is extracted and aborted. If the recombined data rrc returns to the starting cell,
Cells send packets. RRC: 0 is then recombined
Extract the link data rrc and insert it into ring:1
For this purpose, send to RRC:1. 0471 Ring:1 Recombined Data Packet
indicates that remote RRC:1 has a corresponding peer in local ring:0.
has a descriptor assigned to the page and has an Et
ractBuffer is in the Extbuf:All area.
If so, it is extracted by remote RRC:1. recombiner
Data is also used to satisfy any outstanding requests.
It can be used for Release Once the locally generated release is inserted into the ring,
Pend: The Owner state is recorded so that subsequent
The release of the starting ring: is returned to 0 and the preceding already
Possible outstanding getw requests with atomic responses
can be satisfied. Releases that occur remotely
When inserted into ring:0, Pend:Owner state
state is recorded so that subsequent releases are in Ring:1.
Can be returned. Page Fault A page fault occurs when any RRC
Requests that completely pass through ring:1 without detecting any
Detected by Ring:1 system due to strike. packet
Clear RspBsy and InvBsy for no data.
Clearing indicates a page fault. packet
is then extracted by the starting RRC:1 to ring:1.
returned and sent to the requesting cell. [0474] When a page fault occurs, local RRC
:1 is Pend:Owner or Pend:Ro status
placed in This state is set in the system prior to page creation.
must be cleared by system software.
. Faulting (after the page has been pinned)
(of course) mpdw・inv from any cell
Execution of the sum command results in a CiuInvSum packet.
let The following Tables 1 to 11 are a series of rules in this order.
It is an instruction manual. [Table 1] [0476] [Table 2] [0477] [Table 3] [0478] [Table 4] [0479] [Table 5] [0480] [Table 6] [0481] [Table 7] [Table 8] [Table 9] [Table 9] [Table 10] [Table 11] [0486] Page operation The page allocation descriptor is optional.
allocated by the local cell prior to the desired cell SVA request.
Can be attached. The RRC pair is a request packet originating from the first locality.
Receive packet (always no data) from local ring: 0
and assigns a descriptor. Moshi page fall
When a request is issued for a request, the descriptor
remains assigned to the cell and RRC pair. More than one
If the above descriptor is not present in the memory system.
can be assigned to a page. The descriptor is
Must be allocated for the page to be generated
. The following table shows the default status of allocated descriptors.
Specifically indicate the situation. [0487] Page deallocation (Deallocate)
The local cache and local RRC pair descriptor is C
iuInvSumAlloc. nodata, CiuP
ureInvSumAlloc. nodata, or R
rcDeallocDesc. to nodata packet
Therefore, it is only deallocated. These three packets are
called a deallocate packet.
. If the deallocation packet is sent to another cache in Ring:0.
indicates that the page has no allocated pages.
For example, a local RRC pair is a descriptor corresponding to the page.
Remove the data assignment. Deallocation packet with multiple descriptors
prevent race conditions between packets destined for other pages
While deciding whether to deallocate for
RRC:0 transitions to Page:PendDealloc
do. If other cells are assigned to the page
If you don't have a descriptor, you'll end up with a disk.
deallocate the printer. Both of the RRC pairs are either
Before RRC deallocates a descriptor, Page
: Must be in PendDealloc state. station
For local RRC pairs, the descriptor is deallocated to the remote RRC.
Don't let them know what happened. First, the deallocation sequence is
described, and then subpages and page behavior are considered.
Ru. [0488] The deallocation sequence is
The CCU may send CiuLoadDopReg to the CIU.
It is started by. Packet address and CCU
prt entry is the page to be deallocated.
corresponds to The CIU sets the address to its dropping level.
Load to register, extract packet and send it to CCU
return. When loaded with a legitimate address, the CIU dropout
The ping register is used to register requests for owned subpages.
Let the CIU claim RspBsy against the strike and all other
droppin page or subpage address
Ignore matches for Gregister. droppin
Group register matches take precedence over cache group matches.
Ru. [0489] CiuLoadDopR with CCU returned
When the eg packet is received, a new disk is installed at that location.
Allocation of old descriptor by writing descriptor
, remove the prt entry assignment, and
The deallocated page must be pure.
If so, a CiuInvSumAlloc packet is sent. too
If the deallocated page is pure
Issue CiuPureInvSumAlloc packet
. The deallocation packet contains the address of the page to be deallocated.
(pkt.address [5:5] is CC
U descriptor group), and datawords
0 contains the page address to be allocated. Unprocessed CE
U requests are processed even with newly allocated addresses.
come. Because prt is deallocated
This is because there is no need for packets. mrdd(R
The RC deallocation descriptor) command causes the CCU to
RrcDeallocDes without allocating prt
c packet is sent. FIG. 15 shows a preferred embodiment used in the system of the present invention.
The preferred deallocation sequence is shown below. CIU is newly
The allocated descriptor is moved to the old descriptor location.
Unallocate the old descriptor by writing to
and invalidate the dropping register.
CiuIn
vSumAlloc or CiuPureInvSumA
Process the lloc packet (step 1). CIU is
Packet without any modification to the CIU directory
RrcDeallocDesc parameter by inserting
process the packet. [0491] The deallocate packet is
Ring: Since it passes through 0, the device to which RsyBsy is assigned
claimed by the CIU with the scriptor (step
2, 3, 6). 0492 RRC:0 is if RsyBsy claims
CiuInvSumAlloc or RrcD
Empty eallocDesc and unlink the descriptor.
Log: Indicates that the cache is allocated to another cache within 0.
(Step 3). If RspBsy is not claimed
If so, the RRC:0 deallocation packet will be assigned this allocation.
to examine all local caches for the page
To complete the ring: 0 must be passed. why
If so, this packet is deallocated cache and RRC:
This is because only a part of the ring:0 has passed between 0 and 0.
Ru. Ring 0 passes the packet and sets the RRC bit.
, clear RspBsy, and Page:
Transition to PendDeallocate. RRC bit
to indicate that the packet has passed RRC:0.
used for If RRC is updated (refresh
) or ecc. Unable to process packet due to error
If not, RRC sets IndBsy and
Transferring the deallocated packet to the next rotation
). Subsequent allocation.
! RCC packet is PagePendDealloca
Received while te is empty. Because this
The cells that issued these deallocation packets are
Assert RspBsy during the current rotation of release packets
That's because there isn't. RRC:0 sets RspBsy to the first
The reason for denial at the time of an unassignment packet is the subsequent
The cell that issued the deallocation packet is the first deallocation packet
Win asserted RspBsy during the first partial rotation of
This is to process the dough. [0493] If the deallocation packet is CiuPur
If eInvSumAlloc, RRC:0 is
pkt. cmd-pend-deallo
c, send the packet to local RRC:1, and
Jump to step 8 (RRC: 1 processing). CiuPureIn
vSumAlloc keeps all subpages within a page.
and any other allocated
The descriptor has all pages invalid.
We guarantee that you will. Therefore, RRC:0 is skipped.
and reloads the CiuPureInvSumAlloc packet.
around the page to which any cell is allocated.
Determine whether you have a The page is provided by RRC.
and one of the cells in Ring:0 is assigned to the next page.
Request my brother's subpage. 0494]Page:PendDealloc state
Ring: All remotely-originated packets received from 1 are sent to it.
Ring as it is: Returned to 1. Moshi sva-read
- When the ro packet is returned (Ring: 0 state is SPS
tate: Ro) Other rings: 0 is a copy of the subpage
will supply. Cell and RRC pair descriptor
is about to be deallocated, so reco
nbine. data is returned. page destroyer
always invalidates all pages before deallocation
Since it is set to SpState: {Nex, Ex}
would not exist. [0495] If the configuration includes RRC,
If not, both InvBsy and RRC will deny the
be done. The original requester may send packet. re
quest-id is cell-address,! In
vBsy and! Deallocation pattern when matching RRC
Empty the container (step 5). [0496] If the cache page is RspBsy
You instructed that the assignment be made by asserting the
RRC:0 is assigned after a complete passage of Ring:0.
Empty the attachment release RRC packet (step 7). The denial of RspBsy is in Ring:0 which cache
also has no allocated pages. R
RC:0 extracts the deallocation packet and pkt. c.
Set md-pend-dealloc and do this
packet to local RRC:1. RRC:0 and
A certain 1 is allocated by a descriptor to avoid conflicts.
Page:PenDeallo before being canceled
Must be within c. [0497] RRC:1 sends this packet to Page:P
Transition to endDealloc, pkt. cmd-d
Set ealloc-page and extract the packet
, and returns it to RRC:0 (step 8). Pa
ge: Receive from ring:1 in PendDealloc state.
All received remotely originating packets remain in the ring: 1
will be returned to. 0498 RRC:0 deallocates descriptor
Process the packet by
e, extracts the packet and returns it to RRC:1.
(Step 9). RRC:1 is for returning packets.
Similarly, deallocate and transition to Page: None,
Empty the packet. [0499] Packets for pages and subpages are P.
age: Specially when in PenDeallocate state
It is processed. CiuInvSum. nodata, Ci
uInvzSumAlocate. nodata and C
iuExSum. Other page levels like nodata
packets in the file are busy. Remotely derived subpages
Request is busy with RRC:0 and RRC:1
be done. Subpage requests originating locally are RRC: 0
It won't be affected. After all, I am requesting
A local cache has an allocated descriptor.
, the RRC pair deallocates its descriptor.
This is because it prevents Locally derived subpage requests are
Busy by RRC:1. After all, RRC
This is because the pair deallocates the descriptor.
. The descriptor is created after the page is deallocated.
will be subsequently reallocated on the next request. Local sent between steps 7 to 9 by RRC:0
The originating packet is also kept busy by RRC:1. Local origin processed by RRC:0 after step 9
The request is made by RRC:1 after step 10.
is guaranteed to be processed, and the descriptor is
Allocated. 0500 Create page memory system
When the system's software updates the current page in memory,
certify that it has not been refurbished, and
Suppose. System software also has one or more pages.
are not simultaneously generated by the cache of
must be guaranteed. memory system hardware
Air does not detect these conditions immediately. [0501] The mpsa instruction is local to an SVA page.
Provide an anchored descriptor in the cache
. If the descriptor already exists before the mpsa
If so, its anchor flag is set. others
, the local cache stores the descriptor above
disk as described in the page allocation/deallocation section.
Assign a printer. [0502] The local cache then mpdw. alle
x instruction result ciu-ex-sum. nodata package
and owns all subpages within the page.
Transition to state. RRC:0 is ciu-ex-sum.
Extract the nodata packet and write the descriptor if necessary.
allocate the data and send the request to RRC:1. too
If Page:PendDealloc, then RRC
:0 makes a request and pkt. Set InvBsy
to RRC:1 extracts the packet and decrypts it if necessary.
Allocate a scriptor and set all subpages to SpSta.
Transition to te:Owner and RR the request
C: Return to 0. RRC:0 inserts packets and pages
Transition all subpages within to SpState:Ex.
let The originating CIU extracts the packet and sends it to the CC
The CCU returns completion status to the local processor. The mpdw instruction is issued next to clear the anchor bit.
Ru. Page Destruction Problem A page can be destroyed in three ways. the page is destroyed
At any time, all subpages within that page are
must be owned exclusively by the cache
. In the first method, pure pages are deallocated
When the page is deleted, these pages are destroyed. Ciu
The PureInvSumAlloc packet is
indicates that the page is deallocated. Second method
Now, if the address of the descriptor is changed,
, the old page is destroyed and the new page has its contents
do. RrcDeallocDesc Packet Local RR
C indicates that the page should be deallocated. Third
In this method, the page and its contents are explicitly destroyed.
. The CiuInvSum packet is sent by the local RRC to all
Instructs the page to be set to an invalid state. [0504] If the page is destroyed, CiuPu
reInvSumDealloc, RrcDeallo
cDesc and CiuInvSum packets ring:
1 to the remote outstanding or Rei
Clears the ssue (reissue) status. For three cases
The local cache and RRC functions are different, so there are three types.
different packet formats are required. [0505] The page destruction mpsa instruction destroys the local cache for SVA pages.
Provides an anchored descriptor. too
If a descriptor already exists before mpsa,
Its anchor flag is set. in other cases
, the local cache stores descriptors using the above allocation solution.
Remove the descriptor as described in the Remove/Reassign section.
Assign. [0506] The mfsva instruction uses local cache for all
Used to gain exclusive ownership of a subpage. Next, the local cache is ciu-inv-s
um. nodata packet to mpdw. allinv
Occurs as a result of an instruction that invalidates all subpages within the page.
(invalid) state. RRC: 0 is ciu
-inv-sum. Extract the nodata packet and
Send the request to RRC:1. Moshi Page: Pe
If ndDeallc, RRC:0 passes the request.
pkt. Set InvBsy. RRC: 1
extracts the packet and all subpages with SpStat
Transition to e:Inv and send request to RRC:0
return. RRC:0 inserts the packet and in the page
Transition all subpages to SpState:Inv.
let The originating CIU
and returns it to the CCU, and the CCU is in a completed state.
to the local processor. [0508] Page destruction sequences and especially ciu-i
nv-sum. nodata is local cache or RR
Do not deallocate C pair descriptors. local cache
descriptors are reused.
It is not deallocated until it is used. 0509] Change (Change) Descriptor Change
The descriptor page address logically points to the old page.
destroy and then generate a new page with the same data.
That is. Memory system is system software
guarantees that pages currently in memory will not be created
Assume that you are doing so. The system software is
page is not created by two or more caches at the same time
must be guaranteed. Memory system hardware
The hardware does not detect these conditions immediately. [0510] Change descriptor uses three types of instructions.
use i.e. mpdw, mrdd, and mrwd
It is. mpdw instruction is local cell (CCU and CIU)
It is not inserted into Ring:0. RRC allocation from CCU reserved memory system
The attach release descriptor (mrdd) instruction is an operation code.
to become a computer. The CCU codes this instruction from the CEU.
RrcDeallocDsk. nodata package
issue a cut. ! m0 is similar to instructions in other memory systems
and supplies the page address to be deallocated. The CIU inserts this packet into Ring:0. R.R.C.
copies the packet and starts the deallocation sequence.
Ru. If RRC is able to copy or process this packet,
If not, it is packet RspBsy (responder
Busy). CIU returns RrcDa
llocDesc. Extract the nodata packet and
Send this to the CCU. If RspBsy is issued,
The request is reissued by the CCU. If Rsp
If Bsy is clear, CCU marks successful completion as CEU.
Return to If RRC:0 is configured
), the return packet RrcDeallo
cDesc. nodata. ! RspBsy is the original Riku
Same as est and CE of successful completion status in CCU.
Bring it back to U. This instruction is used in the CCU or CIU data structure.
It does not affect the structure. The addition of this instruction is transparent to CEU.
It is clear. [0512] RRC write from CCU reserved memory system
The write descriptor (mrwd) command is
code. The CCU receives this command from the CEU.
RrcWrDesc. nodata packet
give out ! m0 is the page address to be allocated to other
It is supplied in the same way as a memory system instruction. CIU is
Insert this packet into ring:0. RRC: 0 is Pa
Extract the ket. Local RRC: 1 is disabled if necessary.
Allocate the descriptor and set the descriptor to exclusive.
, RRC resident descriptor bit (owner
limit), extract the packet, and retry it.
NG: Send back to 0. If RRC processes the packet
If you don't come, paket. Set RspBsy. CIU returns RrcWrDesc, nodata packet.
and send it to the CCU. RspBsy is set
If so, the CCU reissues the request. too
If RspBsy is clear, CCU will rise above CEU.
Returns successful completion status. If RRC:0 is configured
If not, return packet RrcWrDesc,nod
ata. RspBsy is the same as the original request,
Have the CCU return successful completion to the CEU. This command is
It does not affect the data structure of CCU and CIU. this
Adding instructions is transparent to the CEU. [0513] The change descriptor sequence is as follows:
That's right. 1-Anchor the old page (mpsa). 2- Collect all subpages of the old page in exclusive ownership
. 3-Deallocate RRC descriptor (mrdd
) (old page). 4-Write new RRC descriptor (mrwd
) (new page) 5-Write a new descriptor to the cell and set the anchor bit.
clear (mpdw). [0514] The mrdd and mrwd instructions are descriptors.
It is not necessary if the tag part of the data is not changed. Furthermore,
Gathering all subpages of an old page in exclusive ownership
to change some descriptor bit as above
may not be necessary. Atomic and transient atomic
state is maintained within the cell. RRC subpage status is
, atomic and ization and atomic are in the latter category
Only record non-exclusive and exclusive ownership if the RRC is lost in change descriptor sequence
Holds unprocessed getw state. getw requester
will time out. [0515] Page operation rules allocation rules are shown in the table.
12. [Table 12] [0516] [Table 13] [0517] [Table 14] [0518] [Table 15] [0519] [Table 16] [0520] 0521] Special operation RRC extraction buffer. Full (Extract Buf
fer Full) peak packet rate is
This is faster than the buffer can be freed, so RR
C extraction buffer flow control algorithm is required
. The control algorithm reduces system load while
Based on the principle of maximizing progress. of an ongoing request
By prioritizing system resources for completion, you can achieve both of these goals.
I can achieve my goal. This is because request completion is
This is because it achieves a reduction in system load and advances in maximum efficiency.
. 0522 Extract or copy to extraction buffer
packets that do not originate from this RRC.
Processed based on whether the If the packet is
If the packet did not originate from the RRC of
have no data, have read-only data, or
It will be processed depending on whether you have ownership rights or not. Packet Bi
Gbit RspBsy and InvBsy (conveniently
), and SpState and
and Pendl subpage state fields are
It is used to force the robot to perform legitimate tasks. [0523] All packets issued by RRC
For pkt. TimeStamp is cleared,
As a result, the packet can go around the ring again.
Make it. [0524] For all packets that are not of RRC origin
Also, pkt. The TimeStamp is cleared and the result
The packet can go around the ring again if necessary.
I'll do it. All page operations are performed using no data request packets.
It is considered that For packets with no data
, RspBsy and InvBsy are set. Rs.
pBsy and no data is sva-read-ro0.
set for data response, duplicate is empty
I get kicked. An ownership packet is sent and R
RC:1 transitions to Pendl:Reissue state
. Pendl:Reissue status is RRC:1
and are not extracted to satisfy outstanding requests.
In the case of remote-originated ownership packets that are
By distinguishing between fake and missing pages,
Prevent page-errors
used for. Pendl: Reissue is set
RRC:1 responds to requests originating from RRC.
and lost potential response packets that were not of RRC origin?
Indicate what might happen. If the link derived from RRC:1
Quest returns without response and Pendl: Reiss
ue, the return request is busy due to RRC.
and the requesting processor cell or RR
C to reissue the request, thereby creating a fake page
prevent faults. RRC:0 is SpState
Missing-page-er using field
Prevent ror. RRC:0 SpState field
Read-only copy or ownership ring:
Records whether it is within 0 and satisfies the request.
Ru. What if a request originating from RRC:0 gets no response?
Go back and have enough copies or ownership for Ring: 0
If it exists, the request will be reissued. Next, we analyze the behavior of all cases. Ring: 1 to RRC: 0, Ring: 0 to RRC: 1
Received from RRC:0(1) to RRC:1(0)
If the packet is on ring:1 (0), the packet is
is rerouted back to the other RRC. this is inserted
This is done by immediately extracting the received packet. one
An example is an outstanding request (s in Pendl:Ro state).
local requests of the same type as va-read-ex)
This is the case when the strike is processed in RRC:1. Rs.
pBsy is claimed and the request is local ring:0
will be returned to. [0526] If the extraction buffer is rerouted packet
If the extraction buffer cannot be received,
until it is no longer full and you get an empty packet.
It is held in the insert buffer until of rules
Notation insert. extract follows this behavior.
Indicates routed packets. Ring: 0 to RRC: 0, local ring: 0
Packets issued request packets - returned to point of origin (possibly satisfied along the way), required
If so, get a reissue. Read-only data-carrying packets
- Return to the originating point (maybe satisfied along the way) and as needed
If so, get a reissue. Ownership data carrying packet
Return to the point of origin (probably satisfied along the way) and make the necessary
Get reissued. But if the other ring: from 0
If requested, this packet will not be satisfied.
It should have been. When that packet returns to RRC:1, R
Ownership of RC:1 is still included in Ring:0
The request is sent back to ring:0.
Dew. 0527 Ring: 0 to RRC: 0, Remote Ring:
packet request packet originating from 0 - ring: around 0 (possibly satisfied along the way), R
It will be extracted on the next encounter with RC:0. Read-only data-carrying packets - ring: around 0 (maybe filled along the way), R
It will be extracted on the next encounter with RC:0. Ownership data carrying packet - ring: around 0 (maybe not satisfied along the way);
It will be extracted on the next encounter with RRC:0. 0528 Ring: 1 to RRC: 1, Local Ring
Packet request packet originating from Ring: 0 - around Ring: 0 (possibly satisfied along the way), R
It will be extracted on the next encounter with RC:0. Read-only data-carrying packets - ring: around 0 (maybe filled along the way), R
It will be extracted on the next encounter with RC:0. Ownership data carrying packet - ring: around 0 (maybe not satisfied along the way);
It will be extracted on the next encounter with RRC:0. 0529 Ring: 1 to RRC: 1, Remote Ring:
Packets originating from 0 Request packets - Return to point of origin (possibly satisfied along the way)
If so, get a reissue. Read-only data-carrying packets
- Return to the originating point (maybe satisfied along the way) and as needed
If so, get a reissue. Ownership data carrying packet
It will return to the point of origin and fulfill the request. deer
and unprocessed requests from ring:0 connected to this RRC.
If there was a quest, this packet was not satisfied
It should be. When this packet returns to RRC:1, RR
Ownership of C:1 is still included in Ring:0.
Notify the request and return the request to ring:0. 0530 Ring freezing (freezing) Freezing (phyllo
bits) are packets on the ring for one rotation.
used by the cell to freeze all ring freezing
The result is that all packets on the ring
members cannot change or copy the information in the packet.
It means being in a bad state. Cells are all on the ring
all packets passing through it are frozen.
By systematically claiming frozen bits in the
Freeze the ring. During the freezing period, each cell receives a ring packet.
Freely execute any action without requiring any additional processing. one
Once each ring has frozen a packet, the cell
Unfreeze each packet starting with the first frozen one, and then
Unfreeze frozen packets. ring freezing sequence
If conditions are detected during the unfreeze period to initiate the
The freezing sequence will begin immediately. RRC is that
Packets that were previously frozen and are being refrozen
must be memorized. Figure 16 shows complete ring freezing.
Indicates a full ring freeze. lightly shaded area
indicates a packet slot that is not marked frozen, while
Darkly shaded areas indicate slots marked as frozen
. Processing multiple cells whose rings are to be frozen
In order for each cell to try to freeze the ring most
It behaves as if there is only one cell. but,
The cell will only unfreeze packets that it marks as frozen.
There must be. Therefore, each cell marks it as frozen.
must always remember the packets it has checked. Se
the first and last packets it marked as frozen.
Always remember marked packets by knowing. child
This simplification is possible because the freezing mechanism can be
freezes one contiguous string of packets.
This is because it guarantees that Therefore, shift register nests et al.
Do not use large tubes to freeze the beginning and end of the package.
It is possible to maintain the [0532] Ring freezing can be done in two ways: full
You can start with ring freezing and full-1 ring freezing. cm
Because dFreeze is in the first part of the packet instruction
, the conditions leading to ring freezing are known early in packet processing.
There must be. Freeze the whole ring when the freeze bit freezes.
when used for the first packet to be connected
. The conditions necessary to freeze the ring occur early enough in packet processing.
If it is not available, the full-1 ring freezing method can be used.
. [0533] The full-1 ring freezing method uses the first ring to be frozen.
Do not freeze packets. Instead, packet busy
That is, RspBsy and InvBsy (conveniently
), and SpState
and Pendl subpage status fields are
The correct thing to do to call (Fz:SingleEccEr
r state). The remaining packets are
Frozen and unfrozen are displayed in the same way as full ring freezing.
Ru. The first packet is the extraction buffer full (Extrac
tBufferFull), extract to the extraction buffer.
Or the same as explained regarding packets that cannot be copied.
processed in a manner. [0534] Update (refresh) Update is performed in RiuMasterConfig. Rfresh
Update independently when enabled by Enable.
This is done in a distributed manner by each RRC. 5 every 8ms
Must be updated 12 times. The update interval is 1
5.6 seconds and RiuRefreshIntervc
Indicated in the ring clock by al. [0535] One update requires one packet processing time.
. Therefore, updates are required for blank periods or frozen packets.
It can be done. because these packets require processing.
Because they don't ask for it. RRC is blank and frozen at every update.
update using all invisible packets.
try to RRC sends RiuRefr for each update.
eshiCount. By increasing NumRef
The number of updates up to 31 is stored. At the end of each renewal period, Nu
mRef is decremented by 1. If NumRef is 0
, the update is immediately sent to RRC using the full-ring freeze method.
(NumRef is the first frozen packet)
all RRCs in the ring (not incremented for
Records a number of updates equal to the number of formatted packets.
I can remember. The full ring freeze renewal method
will only be needed if it is fully utilized. The update interval is
0.94 microseconds (15.6*31/512) to 14.
It is adjusted to 7 microseconds and has the effect of saving up to 31 updates. [0536] ECC correctable error (correcta
ble error) When RRC detects a correctable ECC error, additional
Packet time is required to correct the data structure. ring
Freeze multiple packets for correction and relulling
Used to allow time. [0537] When a corrected EEC error is detected, the RRC
begins the full-1 ring freezing procedure. This is ECC error
This is because the information is not known at the beginning of packet processing. The first packet is as described in the extraction buffer full section.
The remaining packets are frozen and mapped for one rotation.
will be tracked. The corrected data structure is rewritten and
Saved in RDU, then E after one rotation of the ring.
Reprocess packets that cause CC errors. Derived from RRC
packets are processed; other packets are processed by other packets in the ring.
is extracted by the cell. When you save the correction packet
, RRC-derived packets are single-bit (correctable)
error is handled correctly. [0538] RRC is pkt. Correct RrcFault
Set in the packet corresponding to possible ECC errors. RRC packets also have uncorrectable ECC errors detected.
When pkt. RRC Unmarked Fault
Claim on provenance packet. [0539] The processor cell issuing the request is
Interpret the RrcFault bit as follows. R
The rcFault bit indicates that an RRC fault has been detected.
Instructs to be stored by RC. If the remaining frames
Marked Fault, Local
Fault, DescFault, and Unmark
dFault) is clear, the packet request is
It ends successfully. If the return packet is busy, leave
The cell sends a fault in the RrcAtt situation and requests
should not be attempted again. Other CIUs and CCUs
Normally process this packet. additional fault
Once the bits are set, the
The effect of the RrcFault bit is ignored. [0540] RDU:0 Rule The RDU:0 subpage and page rule defined earlier is here.
Referenced in this rule. [Table 17] [0542] Table 17 continued [Table 18] [0543] RDU:1 rule The previously defined RDU:0 subpage and page rules are as follows:
Referenced in this rule. [Table 19] [Table 19 continued] [Table 20] [0546] Table 20 continued [Table 21] [0547] Ring: 0 Rule assumption Ring: N For operation, packet details, ring detail
The following changes are required to , CCU Rules, and CIU Rules:
It is. 0548 Cell descriptor deallocation cell descriptor
Cryptor allocation has been changed. The write descriptor RCC has two write descriptor operations.
Action is required. RRC is the old SVA descriptor
deallocate the same descriptor to a new address.
Assign. These two operations affect the packet address field.
field deallocation address and packet data
When two packets are sent to the assigned address in code 0
It requires time. As explained in the change descriptor section
The new sequence is a write descriptor (mpdw).
), the two RRC operations required for
Describes whether it is split into separate instructions and CCU requests
do. 0549]CiuUpdateStateCiuUp
dateState whose only use is ciu. pe
Assuming it is to change the nding state to invalid.
If so, there is no need to send it to the ring. Packet Operations Three RRC-related operations: RrcDealloc
Desc, RrcWrDesc and CiuPureIn
Added vSumAlloc. page＾foul
The t operation was removed as it is not needed for the Rrc operation. The following table shows the revised encoding. [Table 22] 0552 Invalidator and Responder Busy
Invalidator busy, response as a function of packet behavior
The definition of ``busy'' for ``busy'' is listed in the following table. to a certain action
For cell or ring: these bits are also assigned by 0.
has a page named (descriptor match)
This is set to indicate that the This information is RRC
:0 is used to set the page to the cell deallocation sequence.
Assigned to any additional cell within ring:0 during the
Indicate whether or not you can be kicked. [Table 23] [0554] Table 23 continued [Table 24] [0555] Packet Subpage Status Field Next Table
is the valid service as a function of packet behavior.
It lists the page. [Table 25] Ring Freeze Ring Freeze EEC Single Bit Error and Foreground
used to handle code updates. packet pcop
y pcop bit for CIU, RIU, RRC usage
as pkt. Assign cmd[33]. Always CI
It is initialized by inserting U. pcopy set
Packets copied from Ring:1 at RRC:1
Or, there is no need to return to Ring: 1, and Ring: 0 is successfully set.
It is vacated by RRC:0 when it passes through. Packet Freeze CIU, pkt as freeze bit for use in RIU
．． cmd[32] is assigned. Always CIU or R
It is initialized by inserting an IU. set
, the contents of the packet are ignored by all cells. Must be cleared by the same cell that sets it.
No. If cleared, the packet is interpreted as normal
. Valid for empty and non-empty packets. 0559 Packet invalidate looker
Head paget. Change cmd[13] to hold. Next code
paket. cmd[28] cmd-lo
Name it okahead[0]. paget. cmd
[28] Description 0 NoLook
ahead1 L
ookaheadPkt. Lookahead is always
It ignores the data and displays that the packet is short. [0560] Packet RRC bit As the RRC bit, packet. Assign cmd[8]
Teru. Always initialized and passed by CCU and CIU
be given Used by sva-read-ro and read
Combine, release, and if cells in ring:0 become subpepe
If the page is not removed, the packet should be reissued.
Indicates that Packet RrcFault bit RrcF
The fault bit has been changed by RRC. Rrc
The Fault bit indicates that an RRC fault has been detected and the RR
Indicates that it has been stored by C. If the rest of the
Marked Fault, LocalF
fault, DescFault, and Unmarked
Fault) is cleared, the packet request is
Finished in the tail. If the request to return is busy
The departing cell reports a fault in the RrcAtt situation,
Requests are not allowed. Additional faults
Once the bits are set, the actions dictated by these bits
The program ignores the effect of the RrcFault bit. Packet RrcCmd pkt. for RRC and RIC use. cmd[23:
16] to RmcCmd. RrcCmd is
RRC:0 and RRC:1 for deallocation sequence
Used to send status between. [Table 26] CEU aborted requests
EST's cell processing CEU is busy responding to a failed CCU request.
Packets returned as
It's not possible. System error status is stored in local cache
Reported and local cache not hanging
The local processor is notified and the failed request is logged.
processed by the local processor and local cache.
guaranteed. [0565] The control point SPA space address is 64 bits, and the cell address
It is divided into two parts: address and cell address offset. Serua
A dress specifically identifies a particular cell in the ring hierarchy. Also, the cell address offset specifies a specific location within the cell.
do. Cell Address Structure Cell addresses are divided into three levels of the ring interconnection hierarchy:
Cell location inside ring:2, ring:1 and ring:0
Identify. Leaf cell address halling: 2 addresses
, Ring: 1 address Ring: Hierarchically from 0 address
configured. 3 rings: n address field is ring
absolute or relative address to a leaf or non-leaf cell
used to configure. Referring to the table below, there are three types of rings:
:n address, normal address, local address,
and the routing address are shown. Normal a
The address is for one of the 128 cells within a level of the ring hierarchy.
This is an absolute standard. The cccccc field is
Determine the absolute number of cells. Local address is ring hierarchy
is the internal relative standard of level n-1 of . routing
In-addresses are used to address non-leaf cells in the hierarchy.
used for rrrrr in the routing address
The r field is determined by the number of rings or due to proximity to non-leaf cells.
Second ring: Identify the route to n+1. locala
Address and routing encodings are synonymous. Ring: n address description
0cccccccc Normal address
1xxxxxxxxx Local address
Response 1xrrrrrr routine
Ringing: n+1 0568 Cell address mode is
– cell address and non-leaf (RRC) cell address
classified into modes. Cell address mode is cell address
Determined by the combination of address types within the address. [0569] The relative mode of a fief cell is that the cell is
Address yourself without knowing all cell addresses
make it possible. Ring: 2 addresses, Ring: 1 address
Address and Ring: 0 address specifies local address.
Set. Local ring: leaf relative to mode 0
The cell has a Ring:1 address and a Ring:2 address.
Without knowledge, a cell can
allows cells to be addressed. Ring: 0a
The address field identifies the addressed leaf cell.
Ru. Local ring: Leaf cells relative to 1 are actually
Ring: 2 A cell without knowledge of its local address
Ring: Able to address other cells within 1
Make it. Ring:1 address is within local ring:2
Ring: Identify the number of zeros. Ring: 0 address is Ring
Specify the number of cells in 0. Ring: Symbol in 2 modes
A specific leaf cell in the stem has a full (all) cell address.
allow access. Ring: 2 addresses
, Ring:1 address, and Ring:0 address are
The field is hierarchically ring:1, ring:0 and access.
Determine the number of leaf cells that will be 0570 Local ring: relative to one mode
RRC:1 (non-leaf) pairs are non-local RRC:1
that the pair is addressed without knowledge of the Ring 2 address
enable. Ring: 2 address type is local
The address type of Ring:1 is normal and Ring:1 is normal.
Identify the non-leaf cells in Ring:1 and also identify the non-leaf cells in Ring:0 address.
The type of the route is a route and specifies the route.
. RRC:0 interleave configuration (configura
tion) and Ring:0 address fields are
used to send a message to a specified ring:1. RRC:1 pair mode is RRC:1 pair is ring:2 add
address and ring: address by specifying one address.
allow you to be answered. RRC: 2 pair mode is
RRC: 2 pairs ring: 2 addresses, ring: 1 address
Address Routing and Ring: 0 Address Routing
address by specifying the
Ru. In the following table, 1, 2, 3 indicate ring, l is local,
n indicates normal and r indicates routing. [0571] SPA[39] is the addressed RRC or its counterpart.
control whether it is accessed. [0572] Routing of mutually coupled packets (SVA
, SPA) SVA request packets are RRC directory look
up, packet command, pkt. Requestor
ID, CellAddress, RRC rule, and input
Based on the taleave configuration
route is set. The SPA request packet is
ket command, pkt. Addle [63:40]
match, cell address, pkt. RequestorID
, CellAddress, and interleaved configuration.
routed based on. If pkt. Requs
If torID and CellAddress match
, the packet returns a response and the requesting leaf
returned to the cell. In other cases, RequestorI
If D and CellAddress match, the packet is
Depending on the CellAddress mode, the
Requests for child or child leaf cells
. Packet RequestorID match and SPA address
The code at the dress is the ring level where the RRC is connected.
is a function of [0573] [Table 27] [0574] Interleave configuration parameters are RduM
asterConfig. RingInterleav
e, RduMasterConfig. RingVal
ue, and IbuMasterConfig. Link
Interleave. [0575] SPA parameters to leaf cells and non-leaf cells
ket requests take the same route. SPA packet
Request is interleaved matching of cell address
Ring: n address field (n is R for root)
(corresponding to the level of RC) by the RRC bank.
routed. RingInterleave structure
The configuration is ring:n Which bits from address [3:0] are mapped?
Determine if it is connected. For non-leaf cell access
For example, the Ring address [3:0] indicates the exact route.
Identify. For leaf cell access, request
accessing ring: 0 and accessed ring: 0.
An exact route is not required. Routing is addressed
Based on cells. Non-leafling: Access to 2 devices is
, both ring:0 and ring:1 fields of cell address
requires that the code be specified. [Table 28] [0577] Both RRC banks have a single InterRin
In a configuration that binds to gLink, incoming packets
is IbuMasterConfig. LinkInte
One buffer based on rleave and single bit address.
routed to the link. [0578] Offset structure The offset part of SPA is
Select register and select RR where SPA[39] is addressed.
Identify whether C or its counterparty has been accessed
. If it is in each unit, the control location is the type and location.
bounded by the offset. Location off for each type
The scope of a set is specified by its respective description. 0580 Cell address [38:32] - Number of units
The units of banks A and B are sub-ring A (odd number of rings).
) and B (even ring number), respectively. Unit is cell addressing: n address field
The unit is associated as identified by
accessed only when accessed through a subring that
accessible. 0581 Cell address [31:28] - Location type
Unit numbers 0x0 and 0x2 that address the RDU
The types of locations are as follows. [Table 30] 0583 Unit number 0x1 addressing RIU
The types of locations from 0 to 0x13 are as follows. [Table 31] 0585] 0x1 and 0x3 that address RBU
The types of locations are as follows. [Table 32].

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the structure of a preferred multiprocessing system constructed in accordance with the present invention.

2A is a diagram illustrating a preferred memory configuration for providing data coherency in a multiprocessing system of the type shown in FIG. 1; FIG.

FIG. 2B is a diagram illustrating the movement of data in conjunction with ownership claims by processing cells that are not accessing the data in a preferred multiprocessing system constructed in accordance with the present invention.

FIG. 3 is a block diagram illustrating a preferred form of the example level:0 segment of FIG. 1;

FIG. 4 is a block diagram illustrating a preferred configuration of a processing cell used to implement the present invention.

FIG. 5 is a block diagram illustrating a preferred structure of a cache directory in a processing cell constructed in accordance with the present invention.

FIG. 6 is a diagram illustrating a preferred ring routing cell constructed in accordance with the present invention.

FIG. 7 is a diagram illustrating a preferred ring interconnect unit for a ring routing cell used in embodiments of the present invention.

FIG. 8 is a diagram illustrating the organization of a routing directory constructed in accordance with the present invention.

FIG. 9 is a diagram illustrating the organization of a routing directory constructed in accordance with the present invention.

FIG. 10 is a diagram illustrating the format of a routing directory entry used in the implementation of the present invention.

FIG. 11A is a diagram illustrating a preferred configuration of an inter-ring buffer of a ring routing cell constructed in accordance with the present invention.

FIG. 11B is a diagram illustrating a preferred arrangement of inter-link deal rams in a ring routing cell constructed in accordance with the present invention.

FIG. 12 is a diagram illustrating a preferred inter-ring link frame for use in a system constructed in accordance with the present invention.

FIG. 13 is a diagram illustrating a preferred request routing sequence in a system configured in accordance with the present invention.

FIG. 14A is a diagram illustrating a preferred invalidation sequence in a system configured in accordance with the present invention.

FIG. 14B is a diagram illustrating a preferred invalidation sequence in a system configured in accordance with the present invention.

FIG. 15 is a diagram illustrating a preferred deallocation sequence used in a system constructed in accordance with the present invention.

FIG. 16 is a diagram illustrating full ring freezing in a system constructed in accordance with the present invention.

FIG. 17 is a diagram showing the RUD:0 state in another embodiment of the present invention.

FIG. 18 is a diagram showing an RUD:1 state in another embodiment of the present invention.

FIG. 19A is a diagram illustrating a preferred alternative ring interleaving embodiment of the present invention.

FIG. 19B is a diagram illustrating a preferred alternative ring interleaving embodiment of the present invention.

FIG. 19C is a diagram illustrating a preferred alternative ring interleaving embodiment of the present invention.

FIG. 19D is a diagram illustrating a preferred alternative ring interleaving embodiment of the present invention.

[Explanation of symbols] 10 System 12A to 12F, 14A, 14B, 16 Segment 18A to 18R Cell 20A to 20F, 24A, 24B, 26 Bus 28A
~28F, 30A, 30B Route setting cell 40A,
40B, 40C Central processing unit (CP
U) 48A, 48B, 48C Bus 42A, 42B, 42C Memory element 50A, 50B
, 50C Access request elements 52A, 52B, 52C
Control elements 54A, 54B, 54C Stores 56A, 56B, 56C Directory elements

Claims (9)

[Claims] [Claim 1] A. A processing group each comprising a plurality of processing cells each connected by an associated bus means for transferring signals representing packets of information between the processing cells, wherein each processing cell is configured to: (1) refer to data or copies; (2) generating and receiving a signal representing an information packet containing a descriptor of the data to be referenced; B. first and second processing groups comprising CCU means for performing at least one of the following; RRC means for transferring information packets between the first and second processing groups, comprising:
(1) first input means coupled to said first processing group bus means for receiving information packets from said bus means; and (2) first input means coupled to said first processing group bus means for receiving information packets from said bus means; (3) a first output means for selectively outputting information packets; and (3) the second output means.
RRC means (first RRC means) coupled to the bus means of the processing group and comprising second output means for selectively outputting information packets to the bus;
C. The first RRC means is a routing means connected to the first input means and the first and second output means, wherein the first RRC means routes information packets received on the first input means to the first and second output means. between a second processing group and route the data referenced in the information packet or request thereto (or requests thereto) to selected ones of said first and second output means based on a previous routing history of the data referenced in said information packet or request thereto; A digital data communication device comprising a route setting control means for setting a route. [Claim 2] A. A processing group each comprising a plurality of processing cells each connected by an associated bus means for transferring signals representing packets of information between the processing cells, wherein each processing cell is configured to: (1) refer to data or copies; (2) generating and receiving a signal representing an information packet containing a descriptor of the data to be referenced; (3) each said descriptor is independent of the processing cell to which the corresponding data is assigned, and with respect to other data (if any) assigned to the same processing cell; B. first and second processing groups having values independent of data allocation; B. RRC means for transferring information packets between the first and second processing groups, comprising:
(1) a first input means coupled to the bus means of the first processing group for receiving information packets from the bus means; and (2) a first input means coupled to the bus means of the first processing group; (3) a second output coupled to bus means of said second processing group for selectively outputting information packets to said bus; C. RRC means (first RRC means) comprising: C. The first RRC means is a route setting control means connected to the first input means and the first and second output means, and the first RRC means is a route setting control means connected to the first input means and the first and second output means, and the first RRC means is a route setting control means connected to the first input means and the first and second output means. A digital data communication device comprising a route setting control means for setting a route to a selected one of the output means based on a correspondence between data assigned to the first processor. [Claim 3] A. B. first input means for receiving information packets from a first processing group;
first and second output means for transferring said information packets to a corresponding one of said first and second processing groups, each said processing group being coupled by associated bus means; a plurality of processing cells;
input and output means are coupled to bus means associated with said second first processing group, said second output means coupled to bus means associated with said processing group, and each processing cell is configured to: (1) (2) a signal representing an information packet having zero, one, or more data assigned to the cell, each corresponding to a unique descriptor for referencing data or copies; (3) comprising CCU means for performing at least one of generation and reception;
Each said descriptor is independent of the processing cell to which the corresponding data is assigned and other data (if any) assigned to that processing cell.
has a value independent of its corresponding data assignment, and furthermore, C. RRC means for transferring information packets between the first and second processing groups, comprising:
is connected to said first input means and said first and second output means, said information packet received by said input means being based on a correspondence between a descriptor in said information packet and data assigned to said first processing group; a first route control means for routing selected ones of the output means;
A digital information packet route setting switch device comprising: RRC means. [Claim 4] A. B. each having (n) packet forwarding levels, each designated as level (k), where (k) represents a sequential integer between (0) and (n-1); B. Each packet forwarding level has multiple segments,
where the number of segments within each packet forwarding level is
With the exception of packet forwarding level (0), which is less than the number of segments in packet forwarding level (k-1), packet forwarding level (n-1) has only one such segment, and each segment has (1 ) zero, one or more processing cells, and (2) bus means for conveying information packets within its level (k) segments, each said processing cell having: (1) reference data or copies; (2) generating and receiving a signal representing an information packet containing a descriptor of the data to be referenced; (3) each said descriptor is independent of the processing cell to which the corresponding data is assigned, and with respect to other data (if any) assigned to that processing cell; D. has a value that is independent of the data assignment;D. Each level (k) segment for (k) between (1) and (n-1) has multiple RRCs for selectively forwarding information packets between those segments.
means coupled to the bus means of the segment of the level (k), first input means for receiving information packets from the bus means; , a first output means for selectively outputting information packets onto the bus, and a second output means coupled to the bus means of an associated level (k-1) segment for receiving information packets from the bus means. input means;
a plurality of first RRC means coupled to the bus means of its associated level (k-1) segment and comprising second input means for selectively outputting information packets to the bus means; , each associated level (k-1) segment and each sub-segment thereof (if any) is referred to as a sub-segment of that level (k) segment and is associated with a sub-segment of a certain level (k) segment. E, the processing cells other than those associated with the lower segments of a certain level (k) segment shall be referred to as the second group of processing cells; At least one of the 1RRC means is connected to the first input means and the first and second output means, and assigns the received information packet to a descriptor in the information packet and to the first processor group. Based on the correspondence between the data
A digital data communications network, characterized in that it comprises routing control means for routing to selected ones of those output means. [Claim 5] A. B. each having (n) packet forwarding levels, each designated as level (k), where (k) represents a sequential integer between (0) and (n-1); B. Each packet forwarding level has multiple segments,
where the number of segments within each packet forwarding level is
With the exception of packet forwarding level (0), which is less than the number of segments in packet forwarding level (k-1), packet forwarding level (n-1) has only one such segment, and each segment has (1) (2) bus means for conveying information packets within the level (k) segment, each processing cell having its own descriptor for referencing data or copies; corresponding to each,
having zero, one or more data or copies thereof assigned to said cell, each processing cell further comprising:
B. means for generating a signal representing an information packet, said information packet comprising at least one request packet to which a descriptor corresponding to data is assigned and one of a response packet constituting a response to the request packet; D. CCU means coupled to said processing cell for selectively deallocating data assigned to a first cell and simultaneously assigning the data exclusively to a second cell; The segments of each level (k) for (k) between (1) and (n-1) are each connected to the bus means of that segment and the bus means of the associated level (k-1) segment, and a plurality of routing cells for selectively transferring information between segments of the level (k-1), where each associated level (k-1) segment and each sub-segment thereof
Each of said routing cells, E, shall be referred to as a lower segment, based on the correspondence between the descriptor in its request packet and the data assigned to the processing cells of its level (k) lower segment. A digital data communication network comprising means for selecting request packets for transfer between associated level (k) and level (k-1) segments. [Claim 6] A. Processing cells interconnected by associated bus means for conveying information packet representation signals, wherein zero, one or more data or copies thereof each correspond to a unique descriptor for referencing the data or copies; providing first and second processing groups each having a plurality of processing cells assigned thereto, wherein each descriptor is independent of and assigned to the same processing cell to which corresponding data is assigned; B. Other data (if any) assigned shall have a value independent of the assignment of its corresponding data. generating in one or more of said processing cells signals representative of information packets each including a descriptor of data to be referenced; selectively transferring to bus means associated with one or more processing cells; B. The information packets are routed between the first and second processing groups based on the prior routing history of data or copies thereof referenced by descriptors within those packets.
selectively routing between bus means associated with each of the processing groups. [Claim 7] A. Processing cells interconnected by associated bus means for conveying information packet representation signals, wherein zero, one or more data or copies thereof each correspond to a unique descriptor for referencing the data or copies; providing first and second processing groups each having a plurality of processing cells assigned thereto, wherein each descriptor is independent of and assigned to the same processing cell to which corresponding data is assigned; B. Other data (if any) assigned shall have a value independent of the assignment of its corresponding data. generating in one or more of said processing cells signals representative of information packets each including a descriptor of data to be referenced; selectively transferring to bus means associated with one or more processing cells; B. The information packets are transmitted between the first and second processing groups based on the correspondence between descriptors in the information packets and data assigned to the first processing group. selectively routing between each associated bus means. [Claim 8] A. zero, one or more processing cells interconnected by associated bus means for conveying information packet representation signals, each corresponding to a unique descriptor for referencing the data or copies thereof; receiving information packets from a first processing group having a plurality of processing cells each assigned thereto, wherein each said descriptor is independent of and assigned to the same processing cell to which corresponding data is assigned; B. Other data (if any) assigned shall have a value independent of the assignment of its corresponding data. selectively routing the information packet to a corresponding one of the first and second processing groups based on a correspondence between a descriptor in the information packet and data assigned to the first processing group; and each second processing group includes processing cells interconnected by associated bus means for conveying information packet indicating signals between the cells, each second processing group having a unique a plurality of processing cells to which zero, one, or a plurality of data or copies thereof each corresponding to a descriptor are allocated, and each descriptor is independent of and the same processing cell as the processing cell to which the corresponding data is allocated; A method for switching digital information packets, characterized in that, with respect to other data (if any) assigned to the data, the value is independent of the assignment of its corresponding data. [Claim 9] A. A processing group comprising a plurality of processing cells, each processing cell connected by an associated bus means for transferring signals representing packets of information, wherein each processing cell refers to (1) data or copies; having zero, one or more data or copies thereof assigned to said cell, each corresponding to a unique descriptor for (
2) first and second processing groups comprising CCU means for at least one of generating and receiving signals representative of information packets containing data or copy descriptors to which reference is made; B. RRC means for transferring information between said first and second processing groups, said first input means being coupled to said first processing group bus means for receiving information packets from said bus means; (2) first output means coupled to the bus means of the first processing group for selectively outputting information packets to the bus means; and (3) first output means coupled to the bus means of the second processing group. B. a first RRC means coupled to a second output means for selectively outputting information packets to the bus means; The first RRC means is connected to the first input means and the first input means and the first and second output means, and a descriptor corresponding to at least selected data or copies assigned to the first processing group. a correspondence between a referenced descriptor in the information packet and a signal representing the directory in the directory means; Based on the first and second
1. A digital data communications network comprising: route setting means for setting a route to a selected one of the output means.