JPH04228179A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To facilitate high-density integration without impairing the trend toward the higher speeds of operations by wiring one piece of data bus line to one of input/output bus and specifying the constitution of balance circuits. CONSTITUTION:The selection of any of memory cell arrays 4a to 4d, 4e to 4h to be operated is executed according to inputted X addresses. Half of the selected arrays (of the 4 arrays) are subjected to reading out or writing of data via respectively 4 pieces of the data bus lines RWD1 to RWD4. The balance circuits BA1 to BA4 are connected respectively to the bus lines and these circuits are disposed on the short sides 1-2 of the chip and are constituted to maintain the prescribed levels of the bus lines according to the address change detection signals ATD supplied from an address change detection circuit in an Y address buffer 11. The reading out and writing of the data are executed with one piece of the bus line to one bit of the input/output data.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a data bus line for reading and writing data provided along the periphery of a semiconductor chip.

0002

2. Description of the Related Art Generally, a semiconductor memory device has a memory cell array consisting of a plurality of memory cells arranged in an array and a plurality of bit lines and word lines respectively connected to the memory cells, and a predetermined memory cell is selected. A row decoder and a column decoder are arranged adjacent to this memory cell array. Further, a data bus line is arranged as a path for reading and writing data to memory cells selected by these row decoders and column decoders. This data bus line is provided at the periphery of the semiconductor chip, one end is connected to an output pad via an input/output buffer, and the other end is connected to an I/O line (input/output line) via a data amplifier or write amplifier. It is connected to the.

Various measures have been taken to increase the speed of such semiconductor memory devices. As one means of achieving this, when the data bus line is supplied with data read from the memory cell array or data written to the memory cell array, the data bus line is connected so that the level of the data bus line quickly reaches the level of that data. The level is set to 0 just before data is supplied.
A method of setting the voltage to an intermediate level between 1 and 1, that is, 1/2 Vcc, has been used.

Conventionally, a data bus line is composed of a pair of wirings each having a complementary level, and each pair of wirings supplies one piece of data. In order to set the level of the data bus line composed of such a wiring pair to the above-mentioned 1/2 Vcc, conventionally, a means for short-circuiting the two wirings forming the wiring pair has been provided. In other words, the levels of the two wires forming the wire pair complementarily maintain the level of the previous data until the next data is supplied, so one wire is always at Vcc. level, and the other wiring is at GND level. Furthermore, since these two wirings have the same length, the wiring capacitances are the same, and the gate capacitance and diffusion layer capacitance of the transistors connected to the wirings are also approximately equal. Therefore, if the two wires are short-circuited using a gate transistor etc. before the next data is supplied, the level of the two wires will both be 1.
/2Vcc, and high-speed read and write operations can be achieved.

[0005]

However, as mentioned above, conventional semiconductor memory devices have a problem in that when one data bus line is constructed from a wiring pair consisting of two wiring lines, the number of wiring lines increases. be. For example, a 4-bit input/output semiconductor memory device requires four data bus lines, or eight wires, and the area where these wires are placed becomes extremely large, making it difficult to integrate semiconductor memory devices. It becomes difficult.

On the other hand, if the data bus line is constructed from a single wire, the area can be reduced, but since the wiring level cannot be set to 1/2 Vcc, there is a problem in that high-speed operation is impaired. be.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device that can be highly integrated without impairing high-speed operation.

[0008]

[Means for Solving the Problems] A semiconductor memory device of the present invention includes a memory cell array consisting of a plurality of memory cells arranged in an array, a plurality of bit lines and word lines connected to the memory cells, and a selection circuit. An I/O line pair formed by two wires connected to multiple bit lines, and an I/O line pair connected to multiple bit lines.
A data bus line consisting of a data amplifier and a write amplifier connected to the /O line pair, an input/output buffer connected to the input/output pad, and one wiring provided between the data amplifier and write amplifier and the input/output buffer. an address change detection circuit that detects a change in the input address and generates an address change detection signal; and a control signal generation circuit that generates a control signal in response to a write control signal input from the outside. It has a balance circuit that sets the potential level of the data bus line to an intermediate level between the power supply potential and the ground potential in response to an address change detection signal or a control signal.

This balance circuit preferably has an inversion means for inverting the level of the data bus line, and a capacitance approximately equal to the parasitic capacitance of the data bus line, one end of which is connected to the output of the inversion means and the other end connected to a power supply. a capacitive element,
It includes a transfer gate connected between one end of the capacitive element and a data bus line.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the overall structure of a semiconductor memory device according to a first embodiment of the present invention will be described with reference to FIG. Here, a 4M bit DRAM will be explained as an example. FIG. 1 is a plan view of a DRAM semiconductor chip having a 1M word×4 bit configuration.

In the semiconductor chip 1, there are 512 rows×102
4-column, 512K-bit memory cell array 4a
, 4b, . . . , 4h are arranged in a row horizontally, forming a 4 Mbit memory cell array as a whole. This one
One set of row decoders 2 (hereinafter referred to as X decoders) and column decoders 3 for each memory cell array.
(hereinafter referred to as Y decoder) and sense amplifier circuit 5
is provided.

Furthermore, one memory cell array 4a, 4b
,...X-decoder 2 and Y-decoder 3 for 4h
As a data path for reading and writing data to a memory cell selected by It is arranged between the amplifiers 5 (not shown).

The I/O line pair is connected to the bit line pair of the memory cell array through a selection switch controlled by the Y-decoder 3, and is connected to the data amplifiers DA1, DA2, ...DA8 and the write amplifier WA1 outside the cell array area.
, WA2, . . . WA8. Four data bus lines RWD1, RWD2, RWD3, and RWD4 run along one long side 1-1 of the semiconductor chip 1. 4 data bus lines RWD1, RWD2, RWD3
, one end of RWD4 is data amplifier DA1 and DA5,
They are connected to DA2 and DA6, DA3 and DA7, DA4 and DA8, respectively, and are also connected to write amplifiers WA1 and WA5, WA2 and WA6, WA3 and WA7, WA4 and WA8, respectively, and the other end is connected to one short circuit of semiconductor chip 1. Input/output buffers BUF1, BUF2, BUF3, BUF in input/output pads Pad1, Pad2, Pad3, Pad4 arranged on side 1-2
4, respectively.

In this embodiment, memory cell arrays 4a, 4b, 4c, and 4d are operated, and memory cell arrays 4e, 4f, 4g, and
The selection of whether to operate the 4h memory cell array is made in accordance with the input X address. Four data bus lines RWD1 and RWD for the selected half of the memory cell arrays, that is, four memory cell arrays, respectively.
2, RWD3, and RWD4 to read or write data.

Furthermore, four data bus lines RWD1, R
Balance circuits BA1, BA2, BA3, and BA4 are connected to WD2, RWD3, and RWD4, respectively. These balance circuits BA1, BA2, BA3, BA4 are arranged on the short side 1-2 of the chip, and the Y-address buffer 1
This circuit sets the level of the data bus lines RWD1, RWD2, RWD3, and RWD4 to 1/2 Vcc in response to an address change detection signal ATD supplied from an address change detection circuit provided in the address change detection circuit 1.

With this configuration, data can be read and written using one data bus line instead of one pair for one bit of input/output data, without reducing operating speed. The area of the region where the data bus lines are arranged can be reduced. for example,
In the case of a semiconductor memory device with 4-bit input/output, conventionally it consisted of one pair of wires for each bit of data bus line, for a total of eight wires, but according to the present invention, only four wires are needed, which is half the number of wires required for semiconductor memory devices. It is possible to reduce a region having a length and width of approximately 16 μm in the short side direction of the chip.

Next, this embodiment will be explained in more detail with reference to FIG. FIG. 2 is a circuit diagram schematically showing a circuit configuration for explaining read and write operations for the memory cell array 4a of the semiconductor memory device shown in FIG. Components that are the same as those in FIG. 1 are given the same reference numerals.

The memory cell array 4a is formed by arranging so-called one-transistor-one-capacitor type cells MS in an array, each cell having one N-channel type MOS transistor and one capacitive element. The plurality of bit lines constituting one memory cell array 4a are each made up of a plurality of bit line pairs including two signal lines BLa and BLb in a complementary relationship. Sense amplifier SA is connected. Each bit line pair is connected to I via a selection switch 6.
It is connected to wiring I/Oa and I/Ob forming a /O line pair. Furthermore, these I/Oa and I/Ob are connected to a data amplifier DA1 and a write amplifier WA1.

The address signal Ai is applied to an address pad not shown in FIG. 1, and in a time-division manner, the X address XAi is sent to the X-decoder 2 via the X-address buffer 10, and the Y address YAi is sent to the Y-decoder 2 via the address buffer 11
Y-decoder 3 and address change detection circuit A
Each is input to DC. The X-decoder 2 selects one word line WL in the cell array 4a according to the X-address XAi, and the Y-decoder 3 controls the selection switch 6 according to the Y-address YAi to select a plurality of bit line pairs. One set of them is connected to wiring I/Oa and I/Ob. The selection switch 6 receives a selection signal C from the Y-decoder 3 at its gate.
SL is received, and the source/drain path is constituted by a group of transistors provided between the input/output terminal of the sense amplifier SA, I/Oa, and I/Ob.

The address change detection circuit ADC generates a control signal DE for the data amplifier DA1 during a read operation in accordance with the Y address YAi, and generates an address change detection signal ATD for the balance circuit BA during a write operation.

External signals RAS, CAS, and WE are applied to respective pads not shown in FIG. is input. Among the control signals from these control signal generation circuits, CAS
System control signal generation circuit 21 and WE system control signal generation circuit 22
In response to the signal from the data output circuit control signal circuit 23, the data output circuit control signal circuit 23 generates a control signal OE for the output buffer 25. Furthermore, the WE system control signal generation circuit 22 generates control signals W1 and W2.
, and controls the activation of balance circuit BA1, input buffer 26, and write amplifier WA1.

Data amplifier DA1 is activated in response to control signal DE, amplifies the levels of wirings I/Oa and I/Ob, and outputs one data to one data bus line RWD. Write amplifier WA1 is activated in response to control signal W2, amplifies write data on data bus line RWD as complementary data, and supplies the data to wirings I/Oa and I/Ob, respectively.

[0023] Input/output buffer BUF1 is output buffer 2
5 and an input buffer 26. The output buffer 25 is activated in response to the control signal OE, amplifies the data on the data bus line RWD, and outputs the data on the input/output pad Pad.
Output data to 1. The input buffer 26 receives the control signal W
1, is activated in response to W2, amplifies the write data input to the input/output pad Pad1, and outputs the data bus line RW.
Output data to D.

Balance circuit BA1 is activated in response to control signal W1 and address change detection signal ATD, and sets the level of data bus line RWD to 1/2Vcc.

With this configuration, high-speed operation is possible because the data bus line RWD is at 1/2 Vcc when reading and writing data to the memory cell array.

That is, in the case of a read operation, the input Y-
Since the address change detection circuit ADC sets the address change detection signal ATD to an active level in response to the address YAi, the balance circuit BA1 sets the level of the data bus line RWD to 1/2Vcc. Thereafter, the data of the memory cell in the memory cell array corresponding to the input address is supplied to the wirings I/Oa and I/Ob, and the data amplifier DA1 amplifies this data. At this time, since the level of the data bus line RWD is 1/2 Vcc, the level of the output data of the data amplifier DA1 (0 or Vcc
c) The data bus line RWD can be reached at high speed. After that, since the control signal OE becomes active level, the output buffer 25 becomes active and outputs the data on the data bus line RWD to the input/output pad Pad1. Note that since the external signal WE is not input during the read operation, the control signals W1 and W2 generated in response to this signal are
is at an inactive level, and the write amplifier WA1 and input buffer 26 are in an inactive state.

On the other hand, in the case of a write operation, since the external signal WE is input, W1 becomes active level first, and
The balance circuit BA1 sets the level of the data bus line RWD to 1/2Vcc. After that, since the control signal W2 becomes active level, the input buffer 26 amplifies the write data input to Pad1. At this time, since the level of the data bus line RWD is 1/2 Vcc, the level of the output data of the input buffer 26 (0 or Vcc
) can be reached at high speed by the data bus line RWD. Since the write amplifier WA1 is also activated by the control signal W2, the data on RWD is amplified as complementary data and supplied to the wirings I/Oa and I/Ob, respectively. The levels of the wirings I/Oa and I/Ob are stored in predetermined memory cells in the memory cell array, and the write operation is completed.

Next, an example of the configuration of the balance circuit BA1 shown in FIGS. 1 and 2 will be specifically explained with reference to FIG. This balance circuit BA1 has a NOR gate circuit NOR1 inputted with two control signals so as to operate on the data bus line RWD when either of the control signals ATD and W1 becomes active level. . This gate circuit NOR1 includes a P-channel transistor 302 and an N-channel transistor 304 whose gate receives ATD.
It is composed of a P-channel transistor 301 and an N-channel transistor 303 whose gate receives W1. N
The output of OR gate circuit NOR1 is CMOS inverter I
It is connected to the input terminal of N1, and further connected to the active control terminal of inverter IND together with the output of inverter IN1. The data bus line RW is connected to the input terminal of the inverter IN2.
D is connected. The inverter IN1 is composed of a P-channel transistor 305 and an N-channel transistor 306, whose gates are commonly connected to the input terminal, and whose source-drain path is connected in series between the power supply and ground. Inverter IN2 includes a P-channel transistor 307 and an N-channel transistor 308 whose gates are commonly connected to the input terminal.
are provided, and the drains of these transistors are connected in common and connected to node N as an output terminal of inverter IN2. This inverter IN2 is further provided between the power supply and the source of the P channel transistor 307, and has a gate connected to the active control terminal (output of the inverter IN1).
A channel transistor 309 and an N-channel transistor 310 are provided between the ground power supply and the source of the N-channel transistor 308 and have their gates connected to the active control terminal (output of the NOR gate circuit NOR1).
Activation is controlled by two transistors 309 and 310.

N-channel transistor 3 with a source-drain path connected between node N and data bus line RWD
11 is provided, and a CMOS inverter I is provided at its gate.
The output of N1 is applied. One end of the capacitive element C is connected to the node N, the other end is connected to the ground potential, and the capacitive element C is connected to the node N.
It holds the potential of The capacitance of this capacitive element C is approximately equal to the parasitic capacitance of the data bus line RWD, that is, the sum of the wiring capacitance of the wiring itself and the gate capacitance of multiple transistors connected to the wiring or the diffusion capacitance of the source and drain regions. have equal capacity. For example, in a 4 Mbit semiconductor memory device (chip size 5.5 mm x 14.5 mm) as in this embodiment, the parasitic capacitance of one data bus line RWD is approximately 5 to 6 pF (including gate capacitance and diffusion capacitance). (0.5 to 0.7 pF), the capacitance of the capacitive element C is also set to approximately 5 to 6 pF.

The balance circuit BA1 having such a configuration operates as follows. When the control signals ATD and W1 are both inactive level (low level), the output of the NOR gate circuit NOR1 is high level, so the output of inverter IN1 is low level, and the P-channel transistor 309 of inverter IN2 receiving both outputs is and N
All channel transistors 310 become conductive, activating CMOS inverter IN2. As a result, inverter IN2 inverts the potential of data bus line RWD and outputs it to node N. At this time, since a low level is applied to the gate of the N-channel transistor 311, it is in a non-conductive state. Therefore, the capacitive element C holds a potential level opposite to that of the data bus line RWD (for example, when the level of the data bus line RWD is the GND level, the capacitive element holds the potential of Vcc).

When either control signal ATD or W1 becomes active level (high level), the output of NOR gate circuit NOR1 becomes low level, so the output of inverter IN1 becomes high level, and P channel transistor 309 and N channel transistor 310 are both non-conductive. Therefore, inverter IN2 becomes inactive, N-channel transistor 311 becomes conductive, and node N and data bus line RWD are electrically connected. Capacitive element C connected to node N
Until then, the N-channel transistor 31 has held a potential opposite to that of the data bus line RWD, and its capacitance is approximately equal to the parasitic capacitance of the data bus line RWD.
1 conducts, capacitive element C or data bus line R
Half of the charge on WD moves to data bus line RWD or capacitive element C, and the potentials at contact N and data bus line RWD both become 1/2 Vcc.

Note that the capacitance of the capacitive element C does not have to be strictly equal to the parasitic capacitance of the data bus line RWD. That is,
The present invention speeds up read and write operations using a data bus line consisting of a single wire by operating a balance circuit to make the potential of the data bus line approximately half of the power supply potential and ground potential. There are characteristics. Therefore,
When the balance circuit operates, even if the potential of the data bus line becomes slightly higher or lower than 1/2 Vcc, there is no problem in terms of high-speed operation, so there is considerable flexibility in designing the capacitance of the capacitive element C. . .

Next, referring to FIGS. 4 to 7, FIGS.
The specific circuit configurations of the data amplifier DA1, write amplifier WA1, input buffer 25, and output buffer 26 shown in FIG. 1 will be explained.

FIG. 4 is a circuit diagram showing the circuit configuration of data amplifier DA1. Data amplifier DA1 has wiring I/Oa
, is a circuit that amplifies data on I/Ob and supplies one data to data bus line RWD, and two circuits with the same configuration
differential circuits 420 and 421, and a NAND gate circuit N.
AND1, a NOR gate circuit NOR2, and an output stage for the data bus line RWD. The first differential circuit 420 has a pair of wirings I/Oa and I/Ob connected to their gates, and transistors 403 and 4 forming a differential pair.
04, the load is a current mirror circuit constituted by transistors 401 and 402, and the activation is controlled by the conduction state of an N-channel transistor 405 whose gate receives a control signal DE supplied from an address change detection circuit ADC (FIG. 2). be done.

Another stage of a second differential circuit 421 having the same configuration is connected to the first differential circuit 420, and one output of the second differential circuit 421 is connected to a P-channel transistor 406,
407, NAND gate circuit NADN1 consisting of N-channel transistors 408 and 409, P-channel transistors 410 and 411, and N-channel transistor 412
, 413 is input to a NOR gate circuit NOR2. The NAND gate circuit NADN1 has the control signal DE as its other input, and the NOR gate circuit NOR2 has its other input as a signal inverted from the control signal DE by a CMOS inverter formed by a P-channel transistor 414 and an N-channel transistor 415. .

This NAND gate circuit NADN1 and NO
Each output of the R-gate circuit NOR2 is connected to the gate of a P-channel transistor 416 whose source-drain path is connected between the power supply and the output terminal, and to the N-channel transistor 41 whose source-train path is connected between the output terminal and ground potential.
7 and their output signals are supplied to the data bus line RWD.

FIG. 5 is a circuit diagram showing the circuit configuration of write amplifier WA1. The write amplifier WA1 is a circuit that amplifies the data on the data bus line RWD into two complementary data and applies it to a pair of I/O lines I/Oa and I/Ob.
Two NAND gate circuits NAND2 with the same configuration,
It includes NAND3 and two output stages for wiring I/Oa and I/Ob.

Data on the data bus line RWD is transferred to a NAND gate circuit NA consisting of P channel transistors 501, 502 and N channel transistors 503, 504.
A signal inputted to DN2 and inverted by a CMOS inverter composed of a P-channel transistor 505 and an N-channel transistor 506 from the data on the data bus line RWD is transmitted to P-channel transistors 507 and 508.
, N-channel transistors 509 and 510
It is input to the ND gate circuit NAND3.

NAND gate circuit NAND2 and NA
ND3 is the WE system control signal generation circuit 22 (Figure 2)
Its activation is controlled using the control signal W2 supplied from the other input.

[0040] The output of the NAND gate circuit NAND2;
A signal whose output is inverted by a CMOS inverter composed of a P-channel transistor 511 and an N-channel transistor 512 is sent to an N-channel transistor whose source-drain path is connected between the power supply and the output terminal, forming an output stage for the wiring I/Oa. The signals are applied to the gate of the transistor 515 and to the gate of an N-channel transistor 516 whose source train path is connected between the output terminal and the ground potential, and the output signal thereof is supplied to the wiring I/Oa.

Similarly, the output of the NAND gate circuit NAND3 and the output thereof are connected to the P channel transistor 513 and the NAND gate circuit NAND3.
CMOS composed of channel transistor 514
The signal inverted by the inverter is transmitted to the gate of the N-channel transistor 517, which constitutes the output stage for the wiring I/Ob, and whose source/drain path is connected between the power supply and the output terminal, and whose source/drain path is connected between the output terminal and the ground potential. are applied to the gates of N-channel transistors 518 connected to each other, and their output signals are supplied to wiring I/Ob.

Here, the transistor 5 constituting the output stage
The reason why 15 and 517 are N-channel transistors is that when reading, that is, when the control signal W2 is at an inactive level (low level), the level of the wirings I/Oa and I/Ob is set to Vc.
This is to make it close to c.

FIG. 6 is a circuit diagram showing the circuit configuration of the output buffer 25. The output buffer 25 is a circuit that amplifies the data on the data bus line RWD and supplies the data to the input/output pad Pad (FIG. 2).
OR3, NAND gate circuit NAND4 with the same configuration
, NAND5 and an output stage.

Data on the data bus line RWD is transferred to a NOR gate circuit NOR consisting of P channel transistors 605, 606 and N channel transistors 607, 608.
3 and P channel transistors 601, 602, N
NAND consisting of channel transistors 603 and 604
It is input to the gate circuit NADN4. The other input of the NOR gate circuit NOR3 is the control signal BRWD supplied from the balance circuit BA1 (FIG. 1). Furthermore,
The output of the NOR gate circuit NOR3 is P channel transistors 609, 610, N channel transistor 611,
612 is input to a NAND gate circuit NADN5. NAND gate circuit NADN4, NAND5
Both are data output circuit control signal generation circuit 23 (Figure 2)
Its activation is controlled using the control signal OE supplied from the other input.

[0045] NAND gate circuit NADN4, NAND
5 outputs are P channel transistors 613, N
CMOS composed of channel transistor 614
The gate of an N-channel transistor 617 whose source-drain path is connected between the power supply and the output terminal, forming an output stage for the output terminal DOUT, through a CMOS inverter composed of an inverter, a P-channel transistor 615, and an N-channel transistor 616. and the source-train path are respectively applied to the gate of an N-channel transistor 618 connected between the output and ground potential, and the output signal is provided to the output terminal DOUT. This output terminal DOUT is connected to the input/output pad Pad1 (FIG. 2).

FIG. 7 is a circuit diagram showing the circuit configuration of the input buffer 26. The input buffer 26 has an input/output pad Pa
This circuit amplifies the write data input from d1 and supplies it to the data bus line RWD, and the latch circuits 730 and N
It includes AND gate circuits NAND6, NAND7, a NOR gate circuit NOR4, and an output stage for the data bus line.

Write data input from input/output pad Pad1 is sent from input terminal DIN to P channel transistors 701, 702 and N channel transistors 703, 70.
The signal is input to a NAND gate circuit NADN6 consisting of 4 NAND gate circuits. The activation of this NAND gate circuit NADN6 is controlled by using the control signal W1 supplied from the WE system control signal generation circuit 22 (FIG. 2) as the other input. NA
The output of the ND gate circuit NADN6 is inverted by a CMOS inverter composed of a P-channel transistor 707 and an N-channel transistor 708, and the inverted signal is inverted by an N-channel transistor 709 and a P-channel transistor whose gates receive the control signal W1 and its inverted signal, respectively. A transfer gate consisting of transistor 710 is added.

The output signal of the transfer gate is transmitted through the P-channel transistor 711 and the N-channel transistor 71.
2, a CMOS inverter made up of a P channel transistor 713, an N channel transistor 714, and a CMOS inverter made up of a P channel transistor 715 and an N channel transistor 716.
Stored by 0. The output of the latch circuit 730 is a NAND gate circuit NAN consisting of P channel transistors 719, 720 and N channel transistors 721, 722.
D7 and P channel transistors 723, 724,
NOR consisting of N-channel transistors 725 and 726
It is input to the gate circuit NOR4. The NAND gate circuit NAND7 uses the control signal W2 supplied from the WE system control signal generation circuit 22 (FIG. 2) as the other input, and performs a NOR
The other input of the gate circuit NOR4 is a signal obtained by inverting the control signal W2 by a CMOS inverter constituted by a P-channel transistor 717 and an N-channel transistor 718, and the activation of each is controlled.

This NAND gate circuit NADN7 and NO
Each output of the R-gate circuit NOR4 connects to the gate of a P-channel transistor 727 whose source/drain path is connected between the power supply and the output terminal, and an N-channel transistor 72 whose source/drain path is connected between the output terminal and the ground potential.
8 gates, and their output signals are supplied to the data bus line RWD.

Next, referring to FIGS. 8 and 9, FIGS.
Data read and write operations in the semiconductor memory device shown in FIG.

FIG. 8 is a waveform diagram for explaining the operation when reading data. When the address Ai is input (see FIG. 8(a)), the address change detection circuit ADC (see FIG. 2)
raises the address change detection signal ATD to high level (see FIG. 8(c)). When ATD becomes high level, data bus line RWD in balance circuit BA1 and node N
Since the transistor 311 provided between them is conductive (see FIG. 3), the level of the node N and the data bus line RWD are both 1/2 Vcc (see FIGS. 8(e) and (f)).
.

A predetermined memory cell is selected according to the input address Ai, and the levels of the wirings I/Oa and I/Ob (FIG. 2) are set to Vcc and higher depending on the data stored in the memory cell. This results in two complementary data at a low level (see FIG. 8(b)).

Next, address change detection circuit ADC (FIG. 2)
When the control signal DE is raised to a high level (see FIG. 8(d)), the data amplifier DA1 is activated (see FIG. 4).
, amplifies the level of one of the wirings I/Oa and I/Ob, and outputs it to the data bus line RWD. At this time, the level of the data bus line RWD is set to 1/1 by the balance circuit BA1.
Since it is 2Vcc, it becomes 0 (GND level) at high speed.
or 1 (Vcc level) (Figure 8
(see (e)).

When the CAS signal among the RAS and CAS signals input to the address input terminal is input, the data output circuit control signal generation circuit 23 (FIG. 2) starts operating, and the control signal OE rises to a high level. Climb (Figure 8 (g)
)reference). The output buffer 25 (see FIG. 6) is activated by the signal OE, amplifies the data on the data bus line RWD, and outputs it to the output terminal DOUT (see FIG. 8(h)).

As mentioned above, the address change detection circuit ADC (FIG. 2) quickly responds to an address change, raises the address change detection signal ATD, and balances the memory cell array before it receives an address and starts a read operation. The circuit BA1 is operated to change the potential of the data bus line RWD to 1/2 Vcc, but the memory cell array performs a read operation and outputs the read data onto the data bus line RWD, and the potential of the data bus line RWD is determined. First, the address change detection signal ATD is caused to fall to a low level (see FIG. 8(c)). During the read operation, the control signal W1 maintains a low level, so the balance circuit B
The NOR gate circuit NOR1 of A1 (FIG. 3) outputs a high level due to the ATD signal becoming low level, activates the inverter IN2, turns off the transistor 311, and connects the node N to the data bus line RWD.
Isolate from. Activated inverter IN2
gives the inverted value to the node N in accordance with the data on the data bus run-in RWD. That is, if the read data is at a high level, the inverter IN2 discharges the remaining charge in the capacitor C and sets the node N to a low level, and if the read data is at a low level, the inverter IN2 charges the capacitor C and sets the node N to a high level. (See FIG. 8(f)).

At the timing after data output to the output terminal DOUT starts, the address change detection circuit ADC lowers the control signal DE to a low level (see FIG. 8(d)), deactivates the data amplifier DA1, and connects the data bus. Line RW
Isolate D from the I/O line.

FIG. 9 is a waveform diagram for explaining the operation when writing data. CAS and WE of external signals (Figure 2)
is input (see FIGS. 9(a) and 9(b)), the WE system control signal generation circuit 22 (see FIG. 2) raises the control signal W1 (see FIG. 9(d)), and the data output circuit control circuit 2
3 output (not shown). When W1 becomes high level, inverter I in balance circuit BA1 (Fig. 3)
The output of N1 rises and BRWD rises (Fig. 9(f)
), data bus line RW in balance circuit BA1
Since the transistor 311 provided between D and node N becomes conductive, the levels of node N and data bus line RWD both become 1/2 Vcc (see FIGS. 9(g) and (h)). When the signal BRWD from the balance circuit BA1 becomes high level, the NOR gate circuit NO which also receives the data bus line RWD of the output buffer 25 (FIG. 6)
The output of R3 is set to low level regardless of RWD, and since the control signal OE is set to low level, the outputs of the two NAND gate circuits NAND4 and NAND5 are set to high level. Therefore, the inputs of both output transistors 617 and 618 become low level and turn off, and the output terminal DOUT
is placed in a high impedance state to prevent the RWD potential at the level of 1/2 Vcc from being output.

On the other hand, in the input buffer 26 (FIG. 7), since W1 is at a high level, the write data input from the input terminal DIN (see FIG. 9(c)) is stored in the latch circuit 730. . Next, the WE system control signal generation circuit 22 (FIG. 2) raises the control signal W1 and raises W2 (see FIGS. 9(d) and (e)). input buffer 2
The latch circuit 730 of 6 (FIG. 7) is disconnected from the input terminal DIN, and the two gate circuits NAND7 and NOR4 whose output is input are allowed to operate, and the input data is amplified and output to the data bus line RWD. . At this time, since the level of the data bus line RWD is set to 1/2 Vcc by the balance circuit BA1, it can reach 0 (GND level) or 1 (Vcc level) at high speed (see FIG. 8(g)).

As W2 rises, the write amplifier WA1 is also activated, amplifies the data on the data bus line RWD as complementary data, and supplies it to the wirings I/Oa and I/Ob (FIG. 5, (See FIG. 9(i)).
The levels on wirings I/Oa and I/Ob are stored as complementary data in a predetermined memory cell, and the write operation is completed.

In the balance circuit BA1 (FIG. 3),
As the control signal W1 goes low, the output of the NOR gate circuit NOR1 goes high, activating the inverter IN2, which has been inactive, and turning off the transistor 311. As a result, the input data on the data bus line RWD becomes a high level, the capacitor C is discharged and the node N becomes a low level, and in the opposite case, the capacitor C is charged and the node N becomes a high level. That is, node N is held at a level opposite to that of data bus line RWD (see FIG. 9(h)).

Next, the control signal W2 falls, and the write amplifier WA1 becomes inactive.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 10 is a circuit diagram showing the circuit configuration of the balance circuit BA1. The difference in the circuit configuration of the balance circuit explained in FIG.
01 is also provided, and its conduction is controlled by the output signal of the NOR gate circuit NOR1. With such a configuration, it becomes possible to electrically connect node N and data bus line RWD more quickly in response to address change detection signal ATD.

Next, the arrangement position of the balance circuit BA on the semiconductor chip 1 will be explained with reference to FIGS. 11 and 12.

Balance circuit BA explained in FIGS. 3 and 10
Basically, there is no problem in placing it anywhere on the semiconductor chip. Therefore, in order to contribute to the area integration of semiconductor chips, areas with gaps in the layout of peripheral circuits,
It is desirable to place the balance circuit in a so-called dead space. As an example, as shown in FIG. 11, the capacitive element C, which has a particularly large area, is placed adjacent to the input/output buffer BUF1 at the outermost periphery of the semiconductor chip 1, thereby contributing to integration. be able to.

In this case, if the capacitive element C is formed with a normal capacitor structure, the size of this capacitor will be about 50 μm×50 μm if the capacitance is 5 to 7 pF, and it can be placed sufficiently at the outermost periphery.

Furthermore, as shown in FIG. 12, instead of arranging one balance circuit for each data bus line in a separate location, a number of balance circuits corresponding to the number of data bus lines (in this embodiment) are used. It is also possible to collect all four cases in one place.

Furthermore, as shown in FIG. 12, by forming the capacitor in the lower layer of the wiring layer, for example, a balance circuit can be formed without providing an extra area.

In the embodiment described above, the DRAM
Although the present invention has been explained using a data bus line as an example, the present invention is not limited to DRAM.
It is also applicable to data bus lines of RAM.

[0069]

[Effects of the Invention] As explained above, according to the present invention, data can be read and written using one data bus line for one bit of input/output data, without reducing operating speed. The area of the region where the data bus lines are arranged can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing the overall configuration of a semiconductor memory device in a first embodiment of the present invention.

FIG. 2 is a circuit diagram schematically showing a partial configuration of the semiconductor memory device shown in FIG. 1;

FIG. 3 is a circuit diagram showing a circuit configuration of a balance circuit of the semiconductor memory device shown in FIG. 2;

FIG. 4 is a circuit diagram showing a circuit configuration of a data amplifier of the semiconductor memory device shown in FIG. 2;

FIG. 5 is a circuit diagram showing a circuit configuration of a write amplifier of the semiconductor memory device shown in FIG. 2;

FIG. 6 is a circuit diagram showing a circuit configuration of an output buffer circuit of the semiconductor memory device shown in FIG. 2;

FIG. 7 is a circuit diagram showing a circuit configuration of an input buffer circuit of the semiconductor memory device shown in FIG. 2;

FIG. 8 is a waveform diagram for explaining a read operation of the semiconductor memory device shown in FIG. 2;

9 is a waveform diagram for explaining a write operation of the semiconductor memory device shown in FIG. 2. FIG.

FIG. 10 is a circuit diagram showing a circuit configuration of a balance circuit of a semiconductor memory device according to a second embodiment of the present invention.

11 is a plan view showing the arrangement of the balance circuit shown in FIGS. 3 and 10 on a semiconductor chip; FIG.

12 is a plan view showing another example of the arrangement of the balance circuit shown in FIGS. 3 and 10 on a semiconductor chip; FIG.

[Explanation of symbols]

1 Semiconductor chip 2 X decoder 3 Y decoder 4 Memory cell array 5 Sense amplifier DA data amplifier WA light amplifier RWD Data bus line BA Balance circuit

Claims (15)

[Claims] 1. At least one data terminal; a data buffer circuit connected to the data terminal; and a data bus line connected to the data buffer circuit and provided for each data terminal; A capacitive element having a capacitance approximately equal to the parasitic capacitance of the data bus line is provided for one data bus line, and the level of the data bus line is detected and the potential of the capacitive element is adjusted to the potential of the data bus line. 1. A semiconductor memory device comprising: means for setting a level to an inverted level; and means for connecting the capacitive element and the data bus line for a predetermined period. 2. The semiconductor according to claim 1, wherein the means for inverting the level is an inverting circuit having an input end connected to the data bus line and an output end connected to one end of the capacitive element. memory device. 3. The semiconductor memory device according to claim 2, wherein the other end of the capacitive element is grounded. 4. The connecting means is a transfer gate having one end connected to the data bus line, the other end to the capacitive element, and a control end to the means for generating the first control signal for the predetermined period. 2. The semiconductor memory device according to claim 1. 5. The means for generating the inverted level is an inverting circuit having an input end connected to the data bus line and an output end connected to the capacitive element and activated in response to a second control signal. 5. The semiconductor memory device according to claim 4. 6. The semiconductor memory device according to claim 5, wherein the second control signal is an inverted signal of the first control signal. 7. The means for generating the first control signal includes means for receiving an address, means for generating an address change detection signal when the address changes, and means for generating the first control signal in response to the address change detection signal. 5. The semiconductor memory device according to claim 4, further comprising means for generating a control signal. 8. The means for generating the first control signal includes means for receiving a write control signal input from the outside, means for generating a third control signal in response to the write control signal, and the third control signal. 5. The semiconductor memory device according to claim 4, further comprising means for generating said first control signal in response to a control signal of said first control signal. 9. The transfer gate has a source
5. The semiconductor memory device according to claim 4, wherein the drain path is a field effect transistor connected between the data bus line and the capacitive element and whose gate receives the first control signal. 10. The semiconductor memory device according to claim 4, wherein the transfer gate is composed of a field effect transistor of one conductivity type and a field effect transistor of opposite conductivity type. 11. The data buffer circuit includes an input buffer circuit and an output buffer circuit, and is connected to one end of the data bus line, and the other end of the data bus line is connected to a data amplifier and a write amplifier. 2. The semiconductor memory device according to claim 1. 12. The semiconductor memory device according to claim 1, wherein the capacitive element is arranged on the outer periphery of the semiconductor chip. 13. The semiconductor memory device according to claim 1, wherein the capacitive element is provided under a wiring layer arranged within a semiconductor chip. 14. A memory cell array having a plurality of memory cells arranged in an array and a plurality of bit lines and word lines respectively connected to the memory cells, and a wiring 2 connected to the plurality of bit lines via a selection circuit. A pair of I/O lines, a data amplifier and a write amplifier connected to the I/O line pair, an input/output pad, an input/output buffer connected to the input/output pad, and the data amplifier and a data bus line consisting of one wire for each input/output pad provided between the write amplifier and the input/output buffer, and a data bus line that detects a change in the input address and generates an address change detection signal. a control signal generation circuit that generates a control signal in response to an externally input write control signal; and a control signal generation circuit that generates a control signal in response to an externally input write control signal; A semiconductor memory device comprising: a balance circuit that sets a potential level to an intermediate level between a power supply potential and a ground potential. 15. The balance circuit includes inverting means for inverting the level of the data bus line, and a parasitic capacitance approximately equal to the parasitic capacitance of the data bus line, one end of which is connected to the output of the inversion means and the other end connected to a power supply. a capacitive element having a capacitance; a transfer gate connected between one end of the capacitive element and the data bus line and having a control terminal;
15. The semiconductor memory according to claim 14, further comprising means for generating a signal for making the transfer gate conductive in response to one of the control signal and the address change detection signal and applying the signal to the control terminal of the transfer gate. Device.