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JPH04225539A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
JPH04225539A
JPH04225539A JP40791990A JP40791990A JPH04225539A JP H04225539 A JPH04225539 A JP H04225539A JP 40791990 A JP40791990 A JP 40791990A JP 40791990 A JP40791990 A JP 40791990A JP H04225539 A JPH04225539 A JP H04225539A
Authority
JP
Japan
Prior art keywords
circuit board
semiconductor device
semiconductor element
silicon
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP40791990A
Other languages
Japanese (ja)
Inventor
Katsuyoshi Miyauchi
宮内 且好
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP40791990A priority Critical patent/JPH04225539A/en
Publication of JPH04225539A publication Critical patent/JPH04225539A/en
Pending legal-status Critical Current

Links

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To provide a manufacturing method by which the quality of a semiconductor device can be improved by a method wherein a bonding pattern is kept clean and a connecting defective of a fine wire is reduced in a wire bonding process of a COB semiconductor device. CONSTITUTION:A manufacturing method of a COB semiconductor device comprises the following steps: (1) a die attaching process, (2) a wire bonding process, (3) a silicon dam forming process, (4) a sealing process. Since the silicon dam forming process is prepared before the sealing process and after the wire bonding process, a thin film made of silicon is prevented from extending to a bonding pattern.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】この発明は、半導体素子を直接回
路基板に取付ける半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor element is directly attached to a circuit board.

【0002】0002

【従来の技術】回路基板に直接半導体素子を取付ける技
術はチップ・オン・ボード技術(以下、COBという)
と呼ばれ、軽薄短小の半導体装置として、腕時計に代表
される小型電子機器に多く使用されている半導体装置で
ある。従来このCOBの半導体装置の製造方法は、図2
に示す製造方法で行っていた。図3はCOBの半導体装
置の断面図と併せて従来例を説明する。第1の工程では
、回路基板1の所望の場所にシリコンダム2を形成する
工程、シリコンダム形成方法は、スタンピングと呼ばれ
る転写法、あるいは印刷法を持って形成される。
[Prior Art] Chip-on-board technology (hereinafter referred to as COB) is a technology for directly attaching semiconductor elements to a circuit board.
It is a light, thin, short, and small semiconductor device that is often used in small electronic devices such as wristwatches. The conventional manufacturing method for this COB semiconductor device is shown in Figure 2.
It was carried out using the manufacturing method shown in . FIG. 3 explains a conventional example together with a sectional view of a COB semiconductor device. In the first step, the silicon dam 2 is formed at a desired location on the circuit board 1. The silicon dam is formed using a transfer method called stamping or a printing method.

【0003】シリコンダムは、封止樹脂5の流れ出しを
防ぐために設けられる。シリコンは發水性を持っている
ため、封止樹脂をはじくため通常ダムとして使用されて
いる。シリコンダムは回路基板に形成後乾燥される第2
の工程では、回路基板上のシリコンダム内の所望の場所
に半導体素子3を接着する。通常ダイ・アタッチと呼称
する工程である。第3の工程では、回路基板上の配線パ
ターン6(以下、ボンディングパターンという)と、回
路基板上に接着された半導体素子上の電極とを細線6で
電気的に接続する。通常ワイヤボンドと呼称される工程
で、ワイヤボンディング機で、細線は通常Au線を用い
て、熱圧着、振動を用いて接続をはかっている。第4の
工程では、回路基板上の半導体素子と、細線の外部環境
からの保護を目的として、回路基板上のシリコンダムの
範囲内で半導体素子と細線を封止樹脂5で覆う工程で、
通常封止工程と呼称している。封止樹脂は通常エポキシ
系の樹脂が使用されている。
The silicon dam is provided to prevent the sealing resin 5 from flowing out. Because silicone has hydrophilic properties, it is commonly used as a dam to repel the sealing resin. The silicon dam is dried after being formed on the circuit board.
In the step, the semiconductor element 3 is bonded to a desired location within the silicon dam on the circuit board. This process is usually called die attach. In the third step, the wiring pattern 6 on the circuit board (hereinafter referred to as a bonding pattern) and the electrode on the semiconductor element bonded on the circuit board are electrically connected with the thin wire 6. In a process commonly called wire bonding, a wire bonding machine uses thin wires, usually Au wires, to connect them using thermocompression bonding and vibration. In the fourth step, in order to protect the semiconductor elements and thin wires on the circuit board from the external environment, the semiconductor elements and thin wires are covered with sealing resin 5 within the range of the silicon dam on the circuit board.
This is usually called the sealing process. Epoxy resin is usually used as the sealing resin.

【0004】以上の製造方法がCOBの半導体装置の製
造方法として知られていた。
The above manufacturing method has been known as a method for manufacturing COB semiconductor devices.

【0005】[0005]

【発明が解決しようとする課題】しかし、従来の製造方
法では、シリコンダム形成の際、毛細管現象によりシリ
コンが周囲に流れ出し、このためワイヤボンド工程で細
線が接続されるボンディングパターンがシリコンの薄い
被膜で覆われることがしばしば発生していた。ワイヤボ
ンドで細線を確実に接続するためには、ボンディングパ
ターン上を清浄に保つことが絶対的な条件で、ボンディ
ングパターン上にシリコンの薄い被膜が形成されると、
細線の接続不良がしばしば発生するという課題があった
[Problems to be Solved by the Invention] However, in the conventional manufacturing method, when forming a silicon dam, silicon flows out to the surrounding area due to capillary phenomenon, and as a result, the bonding pattern where thin wires are connected in the wire bonding process is a thin film of silicon. It was often covered with In order to reliably connect thin wires with wire bonding, it is absolutely necessary to keep the bonding pattern clean, and once a thin film of silicon is formed on the bonding pattern,
There was a problem in that connection failures of thin wires often occurred.

【0006】そこでこの発明は、従来のこのような課題
を解決するため、ワイヤボンド工程で細線を接続する際
、ボンディングパターンを清浄に保って、細線の接続不
良をなくすことが出来る製造方法を得ることを目的とし
ている。
In order to solve these conventional problems, the present invention provides a manufacturing method that can keep the bonding pattern clean and eliminate poor connection of thin wires when connecting thin wires in a wire bonding process. The purpose is to

【0007】[0007]

【課題を解決するための手段】上記の課題を解決するた
めに、この発明はシリコンダムを形成する工程を、ワイ
ヤボンド工程の後にすることにして、ワイヤボンド工程
で細線の接続の際、ボンディングパターンを清浄な状態
に保つことが出来るようにした。
[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention involves performing the step of forming a silicon dam after the wire bonding step, so that when connecting thin wires in the wire bonding step, the bonding The pattern can now be kept clean.

【0008】[0008]

【作用】上記のように構成されたCOBの半導体の製造
方法においては、ワイヤボンド工程で、ボンディングパ
ターンが清浄な状態に保たれているため、細線の接続不
良をなくすことが出来るようになった。
[Operation] In the COB semiconductor manufacturing method configured as described above, the bonding pattern is kept in a clean state during the wire bonding process, making it possible to eliminate connection failures of thin wires. .

【0009】[0009]

【実施例】以下に、この発明の実施例を図1、図3に基
づいて説明する。図1は、この発明のCOB半導体装置
の製造方法のフローを示す図であり、■のダイ・アタッ
チ工程で回路基板1の所望の場所に、半導体素子3を接
着する。■のワイヤボンド工程で、回路基板上の配線パ
ターン(ボンディングパターン)6と、回路基板上に接
着された半導体素子上の電極とを細線6で接続する。■
のシリコンダム形成工程で、回路基板上の所望の場所に
シリコンダム2を形成する。形成する方法は、転写法、
あるいはディスペンサ等を利用した描画法でシリコンダ
ムを形成することが出来る。■封止工程では、半導体素
子と細線の外部環境からの保護を目的として、回路基板
上のシリコンダムの範囲内で、半導体素子と、細線を封
止樹脂5で覆う、封止樹脂は通常エポキシ系樹脂が使用
されている。
[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 and 3. FIG. 1 is a diagram showing the flow of the method for manufacturing a COB semiconductor device according to the present invention, in which a semiconductor element 3 is bonded to a desired location on a circuit board 1 in the die attach step (2). In the wire bonding process (2), the wiring pattern (bonding pattern) 6 on the circuit board and the electrode on the semiconductor element bonded on the circuit board are connected with the thin wire 6. ■
In the silicon dam forming step, a silicon dam 2 is formed at a desired location on the circuit board. The forming method is a transfer method,
Alternatively, a silicon dam can be formed by a drawing method using a dispenser or the like. ■In the encapsulation process, the semiconductor element and thin wires are covered with a sealing resin 5 within the silicon dam on the circuit board in order to protect the semiconductor element and thin wires from the external environment.The sealing resin is usually epoxy. system resin is used.

【0010】この発明の製造方法では、シリコンダム形
成後、仮乾燥ですぐ連続的に封止工程で樹脂封止を行い
、シリコンダムと、封止樹脂を一緒に高温で乾燥するこ
ともできる。
[0010] In the manufacturing method of the present invention, after the silicon dam is formed, resin sealing is performed in a continuous sealing step immediately after temporary drying, and the silicon dam and the sealing resin can also be dried together at a high temperature.

【0011】[0011]

【発明の効果】この発明は、以上説明したように、シリ
コンダム形成工程をワイヤボンド工程の後で行うという
簡単な方法により、COB半導体装置の品質に重要な影
響を与える。ワイヤボンド工程での細線の接続を確実に
し、接続不良をなくすと同時に半導体装置の品質の向上
を図れるという効果がある。
As explained above, the present invention has a significant effect on the quality of COB semiconductor devices by using a simple method in which the silicon dam forming step is performed after the wire bonding step. This has the effect of ensuring the connection of thin wires in the wire bonding process, eliminating connection failures, and at the same time improving the quality of semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の半導体装置の製造方法の工程図である
FIG. 1 is a process diagram of a method for manufacturing a semiconductor device according to the present invention.

【図2】従来の半導体装置の製造方法の工程図である。FIG. 2 is a process diagram of a conventional method for manufacturing a semiconductor device.

【図3】COBの半導体装置の断面図である。FIG. 3 is a cross-sectional view of a COB semiconductor device.

【符号の説明】[Explanation of symbols]

1  回路基板 2  シリコンダム 3  半導体素子 4  細線 5  封止樹脂 6  配線パターン 1 Circuit board 2 Silicon dam 3 Semiconductor element 4 Thin line 5 Sealing resin 6 Wiring pattern

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  回路基板と、前記回路基板に直接半導
体素子を接着し、前記半導体素子と、前記回路基板の配
線パターンとを細線で電気的に接続し、前記細線を含む
範囲で前記半導体素子を樹脂で封止されている半導体装
置の製造方法において、前記回路基板に前記半導体素子
を接着する工程と、前記回路基板の配線パターンと、前
記半導体素子とを細線で電気的に接続する工程と、前記
半導体素子を囲んで、前記回路基板の所定の場所に前記
工程の後にシリコンダムを形成する工程と、前記シリコ
ンダムの範囲内で、前記細線および半導体素子を樹脂で
封止する工程と、からなることを特徴とする半導体装置
の製造方法。
1. A circuit board, a semiconductor element is directly bonded to the circuit board, the semiconductor element and a wiring pattern of the circuit board are electrically connected by a thin wire, and the semiconductor element is bonded in a range including the thin wire. A method for manufacturing a semiconductor device in which a semiconductor element is sealed with a resin includes the steps of: adhering the semiconductor element to the circuit board; and electrically connecting the wiring pattern of the circuit board and the semiconductor element with a thin wire. , forming a silicon dam surrounding the semiconductor element at a predetermined location on the circuit board after the step; sealing the thin wire and the semiconductor element with resin within the range of the silicon dam; A method of manufacturing a semiconductor device, comprising:
JP40791990A 1990-12-27 1990-12-27 Method of manufacturing semiconductor device Pending JPH04225539A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP40791990A JPH04225539A (en) 1990-12-27 1990-12-27 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP40791990A JPH04225539A (en) 1990-12-27 1990-12-27 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JPH04225539A true JPH04225539A (en) 1992-08-14

Family

ID=18517439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP40791990A Pending JPH04225539A (en) 1990-12-27 1990-12-27 Method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH04225539A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06132626A (en) * 1992-10-21 1994-05-13 Nec Corp Printed circuit board

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61216438A (en) * 1985-03-22 1986-09-26 Nippon Kogaku Kk <Nikon> Manufacture of sealed electronic part

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61216438A (en) * 1985-03-22 1986-09-26 Nippon Kogaku Kk <Nikon> Manufacture of sealed electronic part

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06132626A (en) * 1992-10-21 1994-05-13 Nec Corp Printed circuit board

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