JPH0422215A - Pulse width variable circuit - Google Patents

Abstract

PURPOSE:To set the variable quantity of a pulse width in accordance with a set time of a delay gate by taking AND of an input pulse signal and an output signal of the delay gate, and also, taking OR of both the signals. CONSTITUTION:When a changeover switch 4 is switched to a contact 4B side, AND of a pulse signal 100 and a pulse signal 101 is taken in an AND gate 5, and a pulse signal 103 is outputted from the gate 5. In such a case, in an OR gate 6, OR of the signal 100 and the signal 101 is taken and from the gate 6, a pulse signal 105 is outputted. Subsequently, when the contact of the switch 4 is switched to the 4A side, AND of a signal 102 and the signal 100 is taken in the gate 5, and a pulse signal 104 is outputted to an output terminal 9. On the other hand, in the gate 6, OR of the pulse signal 102 and the signal 100 is taken, and a pulse signal 106 is outputted to an output terminal 10. In such a way, a signal of pulse width conforming to a set time of delay gates 2, 3 can be generated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a variable pulse width circuit, and more particularly to a variable pulse width circuit suitable for arbitrarily varying the pulse width of an input pulse signal according to a set time.

2. Description of the Related Art Conventionally, as this type of variable pulse width circuit, one shown in FIG. 3 is known. This circuit is composed of a monostable multi-bi break 21, a capacitor 22, and a resistor 23, and converts a pulse signal input to an input terminal 24 into a signal with a pulse width determined by a time constant determined by the capacitor 22 and resistor 23. The signal can then be output from the output terminal 25.

Problems to be Solved by the Invention However, in the conventional variable pulse width circuit, if the values of the resistor 23 and capacitor 22 that determine the pulse width vary or the amplitude of the input pulse signal fluctuates, the pulse of the output pulse signal changes. There is a problem that the width cannot be determined accurately.

An object of the present invention is to provide a variable pulse width circuit that can arbitrarily set the pulse width of an input pulse signal.

Means for Solving the Problems In order to achieve the above object, the present invention provides a delay gate that delays an input pulse signal by a set time and outputs the delayed signal, and a logical product of the input pulse signal and the output signal of the delay gate. The variable pulse width circuit includes an AND gate that outputs a pulse signal according to the input pulse signal and an OR gate that outputs a pulse signal according to the logical sum of the input pulse signal and the output signal of the delay gate.

Therefore, according to the present invention, the pulse width of the input pulse signal can be converted into a narrow pulse width by taking the logical product of the input pulse signal and the output signal of the delay gate.

Furthermore, by logically ORing the input pulse signal and the output signal of the delay gate, it is possible to generate a pulse signal with a wider pulse width than the input pulse signal. Therefore, it is possible to set the variable amount of the pulse width according to the set time of the delay gate.

Embodiment A variable pulse width circuit according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, input pulse delay gates 2 and 3 are connected between input terminal 1 and output terminals 9 and 10.
A changeover switch 4, an AND gate 5, and an OR gate 6 are provided, and the input side of the gate 2 and one input side of the AND gate 5 and OR gate 6 are connected to the input end 1, and the output sides of the AND gate 5 and OR gate 6 are connected to the input terminal 1. Output @
Connected to 9.10. The output terminal 7 of the gate 2 is connected to the input side of the gate 3 and the contact 4B of the changeover switch 4. The output terminal 8 of the gate 3 is the contact 4 of the changeover switch 4
Connected to A.

A common contact 4C of the changeover switch 4 is connected to the other input side of the AND gate 5 and the OR gate 6.

The delay gates 2 and 3 are each configured to delay the input pulse signal by a set time, and when a pulse signal 100 as shown in FIG. 2(A) is input to the input terminal 1, the delay gates A pulse signal 101 as shown in (B) is output from the gate 2. Furthermore, the output terminal 8 of the delay gate 3 receives a pulse signal 1 as shown in (C).
02 is output. When the changeover switch 4 is switched to the contact 4B side, the AND gate 5 calculates the AND of the pulse signal 100 and the pulse signal 101.
A pulse signal 103 as shown in (D) is output from the AND gate 5 to output #19. On the other hand, at this time, in the OR gate 6, the pulse signal 100 and the pulse signal 10
1 and the OR gate 6 outputs a pulse signal 105 as shown in (F) to the output terminal 10.

That is, a pulse signal 103 whose pulse width is shortened by the delay time set by the delay gate 2 with respect to the input pulse signal 100 is output to the output terminal 9, and a pulse signal 103 of the input pulse signal 100 is output to the output terminal 1o. A pulse signal 105 having a pulse width expanded by the delay time set by the delay gate 2 is output.

Next, when the contact of the changeover switch 4 is switched to the 4A side,
The AND gate 5 performs a logical product of the pulse signal 102 and the pulse signal 100, and a pulse signal 104 as shown in (E) is outputted to the output terminal 9. On the other hand, in the OR gate 6, the pulse signal 102 and the pulse signal 10
It is logically summed with 0, and a pulse signal 106 as shown in (G) is outputted to the output terminal 10. In this case, a pulse signal 104 having a pulse width shorter than that of the pulse signal 103 by the delay time set by the delay gate 3 is output to the output terminal 9, and the output terminal 10
Then, a pulse signal 106 having a pulse width that is longer than the pulse signal 105 by the delay time set by the delay gate 3 is output.

In this manner, according to this embodiment, it is possible to generate a signal with a pulse width according to the set time of the delay gate 2.3.

Further, in the embodiment described above, the delay gate 2.degree.3 was described, but it is also possible to use a single delay gate, and in this case, the changeover switch 4 becomes unnecessary.

Effects of the Invention As is clear from the above embodiments, the present invention can generate a pulse signal with an arbitrary pulse width according to the set time of the delay gate. It is possible to generate a pulse signal with a wide width.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a variable pulse width circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing waveforms at various parts in FIG. 1, and FIG. 3 is a circuit diagram of a conventional example. 1... Input end, 2, 3... Input pulse delay gate, 4... Selector switch, 5... AND gate, 6...
...OR gate, 9.10...output end. Name of agent Patent attorney Shige Awano Takahaka 18th figure

Claims (1)

[Claims] A delay gate that delays the input pulse signal by a set time and outputs it, an AND gate that outputs a pulse signal according to the logical product of the input pulse signal and the output signal of the delay gate, and the input pulse signal and the delay gate. A variable pulse width circuit comprising an OR gate that outputs a pulse signal according to a logical sum with an output signal of the circuit.