JPH04220016A - Successive approximation a/d converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called successive approximation type AD converter among AD (analog-digital) converters.

0002

2. Description of the Related Art Conventionally, a successive approximation type AD converter, the main part of which is shown in FIG. 5, has been proposed. This successive approximation type AD converter is an example of the RC combination type, and is configured to obtain a 10-bit digital output. In the figure, 1 is an analog signal input terminal into which an analog signal to be converted into a digital signal is input; 2;
3 is an analog switch that controls the passage of the analog signal input to the analog signal input terminal 1 into the interior; SL is a signal that controls ON/OFF of the analog switch 2;
4 is an inverter for inverting the signal SL; AS is a signal for controlling ON/OFF of the analog switch 3; 5
is an inverter for inverting the signal AS. Note that the analog switch 2 is an analog switch used for channel selection.

Further, reference numeral 6 denotes a switch circuit section used for sampling operation and conversion operation, and this switch circuit section 6 is constructed by providing switches 77 to 71. Also, AVR is the reference voltage for analog signals, AVSS
is a ground dedicated to analog signals, 8 is a capacitor array section used for calculating the upper 6 bits, and capacitor array section 8 is a ground dedicated to analog signals.
Capacity 97 (32C) formed by radial weighting
~91(1C).

[0004] Also, 10 is a resistance voltage division type DA converter section used to calculate the lower 4 bits, and this DA converter section 10 includes resistors 1115 to 110 and a switch 1.
215 to 120. Also, 13 is DA
An analog switch CMPX that controls the supply of the analog output of the converter section 10 to the capacitor 91 is a signal that controls ON/OFF of the analog switch 13, and 14 is an inverter that inverts the signal CMPX.

Further, 15 is a comparator section that forms a digital signal as an output signal, and this comparator section 15 includes nMOS transistors 16 and 17, inverters 18 and 19 forming a comparator, an interstage capacitor 20,
nMOS used for compensation of nMOS transistor 16
A transistor 21, an nMOS transistor 22 used for compensation of the nMOS transistor 17, an nMOS transistor 23 for removing the charge from the capacitors 97 to 91 during non-AD conversion, and a charge from the interstage capacitor 20 during non-AD conversion. The structure includes an nMOS transistor 24 for extracting the voltage.

Further, SPL is a sampling signal, 25 is an inverter for inverting the sampling signal SPL, and ADMV is an nMOS transistor 2 for removing charge.
A signal for controlling ON/OFF of 3 and 24, and 26 is a digital signal input terminal to which a digital signal is output. In addition, in this FIG. 5, the switches 77 to 71 and 1215 to 120 are turned on by the control circuit and the signal from this control circuit.
, OFF is omitted from illustration.

FIG. 6 is a time chart showing the operation of such a conventional RC successive approximation AD converter. In this example, first, the signal ADMV becomes low level "L", and the n
Both the MOS transistor 23 and the nMOS transistor 24 for discharging the charge from the interstage capacitor 20 are turned off, and one cycle of AD conversion is started.

Then, the signals SL and AS become high level “H”.
”, analog switches 2 and 3 are turned on,
Input of an analog signal is permitted, and then the sampling signal SPL becomes high level "H" and sampling is started. Thereafter, when a predetermined period of time has elapsed, the sampling signal SL becomes low level "L" and sampling ends.

Then, the signals SL and AS become low level “L”.
”, analog switches 2 and 3 are turned OFF, and analog signal input is prohibited.Subsequently, signal CM
PX becomes low level “L” and analog switch 1
3 is turned ON and AD conversion operation starts. after that,
After a predetermined period of time has elapsed, the signal CMPX goes to high level “
The analog switch 13 is turned off and the AD conversion operation is completed. Then, the signal ADMV becomes high level "H" and the nMOS transistors 23 and 2
4 is turned on, the charges in the capacitors 97 to 91 and the interstage capacitor 20 are discharged, and one cycle of AD conversion is thus completed.

0010

[Problem to be Solved by the Invention] In such a conventional successive approximation type AD converter combined with RC, calculation of the upper 6 bits is performed by capacitors 97 to 91, but these capacitors 97 to 91 are subjected to binary weighting. Therefore, the combined capacitance value of these capacitors 97 to 91 becomes extremely large. For this reason, the time required to sample the analog input, that is, the capacitance 97~
It takes a very long time to charge the 91, and this is
This was preventing speeding up of D conversion.

One way to solve this problem is to increase the size of the analog switches 2 and 3 to reduce their on-resistance, and to reduce the on-resistance of the analog switches 2 and 3.
It is conceivable to reduce the time constant of the circuit consisting of circuits 7 to 91. However, there is a problem in that increasing the size of the analog switches 2 and 3 reduces noise resistance.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a successive approximation type AD converter capable of speeding up AD conversion and improving noise resistance.

[0013]

[Means for Solving the Problems] FIG. 1 is a diagram explaining the principle of a successive approximation type AD converter according to the present invention. The successive approximation type AD converter according to the present invention controls the input of an analog signal to be converted into a digital signal. Analog for
A switch 3, a switch circuit section 6 used for sampling analog signals, a capacitor array section 8 consisting of a plurality of binary weighted capacitors, and a comparator section 15 for forming a digital signal as an output signal. When configuring a successive approximation type AD converter comprising It is.

Note that 29 is a control circuit, and 30 is a control circuit 2.
This is a successive approximation register that controls the operation of the switch circuit section 6 based on a signal from the switch circuit section 9.

[0015]

[Operation] In the present invention, during sampling, the time for charging the capacitors constituting the capacitor array section 8 depends on the output impedance of the amplifier 27. Therefore, the time required to charge the capacitors constituting the capacitor array section 8 can be shortened.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 2 and 3, taking as an example the case where the present invention is applied to a successive approximation type AD converter with RC. In FIG. 2, parts corresponding to those in FIG. 5 are designated by the same reference numerals, and redundant explanation thereof will be omitted.

FIG. 2 is a circuit diagram showing a main part of an embodiment of the present invention. A voltage follower 32 consisting of an operational amplifier 31 is interposed between the analog switch 13 and the switch 71, and a voltage follower 34 consisting of an operational amplifier 33 is interposed between the analog switch 13 and the switch 71. It is configured similarly. Note that the operational amplifiers 31 and 33 can be configured as shown in FIG. 3, for example.

In this embodiment, since the voltage follower 32 is interposed between the analog switch 3 and the switch circuit section 6, the capacitors 97 to 91 constituting the capacitor array section 8 are charged during sampling. the time is,
Although it depends on the output impedance of the voltage follower 32, since the voltage follower has a low output impedance, the capacitors 97 to 91 are charged by the analog signal input to the analog signal input terminal 1. can be done in a shorter time than conventional methods.

Furthermore, in this embodiment, since the voltage follower 34 is interposed between the analog switch 13 and the switch 71, the time for charging the capacitor 91 with the analog output of the DA converter section 10 is equal to this voltage. Although it depends on the output impedance of the follower 34, since the voltage follower has a low output impedance as described above, charging of the capacitor 91 by the analog output of the DA converter section 10 is not conventional. It can be done in a comparatively short time.

Furthermore, in this embodiment, since the voltage follower 32 has a high input impedance, a low-pass filter consisting of the ON resistance and parasitic capacitance of the analog switches 2 and 3 is constructed before the voltage follower 32. Furthermore, since the voltage follower 34 has a high input impedance, a low-pass filter consisting of the ON resistance of the analog switch 13 and a parasitic capacitance is configured before the voltage follower 34.

Therefore, according to this embodiment, it is possible to speed up AD conversion and improve noise resistance.

In the above embodiment, the operational amplifier 3 is connected between the analog switch 3 and the switch circuit section 6.
1 and a voltage follower 34 consisting of an operational amplifier 33 is interposed between the analog switch 13 and the switch 71. However, instead of this, a source follower as shown in FIG. It is also possible to intervene.

Further, in the above-mentioned embodiments, the case where the present invention is applied to a successive approximation type AD converter combined with RC has been described, but the present invention can also be applied to the DA converter section 1.
It can also be applied to an AD converter using a charge comparison method that does not have 0.

[0024]

[Effect of the invention] According to the present invention, the analog switch 3
Since a configuration is adopted in which an amplifier 27 with a gain of 1, high input impedance, and low output impedance is interposed between the switch circuit section 8 and the switch circuit section 8, speeding up of AD conversion and improvement of noise resistance are achieved. can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of an operational amplifier used in an embodiment of the present invention.

FIG. 4 is a circuit diagram showing a source follower.

FIG. 5 is a circuit diagram showing a main part of an example of a conventional RC combination successive approximation type AD converter.

6 is a time chart showing the operation of the conventional RC combination successive approximation type AD converter shown in FIG. 5. FIG.

[Explanation of symbols]

3 Analog switch 6 Switch circuit section 8 Capacitor array section 15 Comparator section 27 Amplifier 29 with a gain of 1, high input impedance, and low output impedance Control circuit 30 Successive approximation register (SAR)

Claims (1)

[Claims] 1. An analog switch (3) for controlling the input of an analog signal to be converted into a digital signal, and a switch circuit section (3) used for sampling the analog signal.
6), a capacitor array section (8) consisting of a plurality of capacitors subjected to binary weighting, and a comparator section (15) for forming a digital signal as an output signal. A successive approximation device characterized in that an amplifier (27) with a gain of 1, high input impedance, and low output impedance is interposed between the analog switch (3) and the switch circuit section (6). type AD converter.