JPH04215314A - Pulse variable delay circuit - Google Patents

Abstract

PURPOSE:To delay an input pulse variably without almost changing an output pulse width. CONSTITUTION:A variable delay circuit in which an emitter follower comprising a constant current source and a transistor(TR), a capacitive load is connected to the emitter, a comparator is connected to the emitter follower and a reference voltage of the comparator is controlled by a D/A converter is connected in cascade. Thus, a pulse signal of almost the same pulse width as that of an input pulse is outputted independently of a threshold voltage.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to delay circuits, and more particularly to variable pulse delay circuits used for the purpose of variable pulse delay.

0003

2. Description of the Related Art FIG. 3 shows a conventional pulse variable delay circuit. In the figure, the pulse variable delay circuit includes transistors Q1 and Q2, constant current source I1, and resistors R1 and R2.
An emitter follower consisting of a transistor Q3 and a constant current source I2, a load capacitor CL, a working comparator CMP1, and a D/A converter (voltage output) DAC1. This circuit varies the amount of delay in the rise of the input pulse PULSE by controlling the data DATA input to the D/A converter DAC1.

Next, the detailed operating principle of this circuit will be explained based on the voltage waveform shown in FIG. Here, the same figure (1)
Consider the case where an input pulse PULSE (positive pulse) as shown in is input. At this time, the potential of the emitter of the transistor Q3 (point A in the figure) changes from the time of the fourth rising edge of the input pulse PULSE t=t0 to the potential {VCC-VBE(Q3)}, as shown in (2) of the figure. potential {VCC
−I1・R1−VBE(Q3)} to dV/dt=I2/
Descend at a slope of CL. Furthermore, when the input pulse PULSE falls at t=t2, the potential at point A becomes the potential {V
CC-I1・R1-VBE(Q3)}, the potential {VCC
-VBE(Q3)}. At this time, the output of the comparator CMP1 (Q-Q
▲Bar▼) voltage is t=t1(
It rises when the potential at point A when falling = time of voltage V0),
It becomes a positive pulse that falls at t=t3 (potential at point A at rise=time of voltage V0). That is, the rise of the output (Q-Q▲bar▼) pulse of the comparator CMP1 is delayed by the time Δt=t1-t0. Therefore, by changing the output voltage V0 of the D/A converter DAC1, , D/A converter DAC1
By changing the input data DATA, the delay time Δt can be made variable. However, the pulse width of the output (Q-Q▲bar▼) of the comparator CMP1 is Wt0-Wt1=t2-t0-(t3-t1)=t
1-t0-(t3-t2)▲approximately▼Δt. If this pulse width becomes too short, problems such as malfunction of subsequent circuits will occur.

[0005]

As described above, in conventional pulse variable delay circuits, the pulse width of the output pulse is determined by the threshold voltage, and in some cases, the pulse width becomes short, resulting in malfunction of the subsequent circuit. It had the disadvantage of being a trigger.

[0006] The present invention solves the above problems.
The purpose is to provide a variable pulse delay circuit that can variably delay an input pulse without substantially changing the pulse width of the output pulse.

[Configuration of the invention]

[0008]

[Means for Solving the Problems] In order to solve the above problems, the feature of the present invention is to provide a constant current source I2 as shown in FIG.
and a transistor Q3, a capacitive load CL connected to the emitter of the transistor Q3, a comparator CMP1 connected to the emitter of the transistor Q3, and the comparator CMP.
a D/A converter DAC1 that is connected to the comparator CMP1 and controls the comparator CMP1 by supplying a reference potential to the comparator CMP1;
and a second variable pulse delay circuit which has the same configuration as the first variable pulse delay circuit and is cascade-connected to the first variable pulse delay circuit.

The second feature of the present invention is that, as shown in FIG. 1, a constant current source I1 and two transistors Q1 and Q
2 and 1 of the differential amplifier.
An emitter follower configured with a constant current source I2 and a transistor Q3 with the output as input, a capacitive load CL connected to the emitter of the transistor Q3 of the emitter follower, and a comparator CMP1 connected to the emitter of the transistor Q3 of the emitter follower. and a D/A converter DAC1 connected to the comparator CMP1 and controlling the comparator CMP1 by supplying a reference potential thereof.
a second pulse variable delay circuit having the same configuration as the first pulse variable delay circuit and cascade-connected with the first pulse variable delay circuit, The polarity of the differential input of the second variable pulse delay circuit is opposite to the polarity of the differential input of the first variable pulse delay circuit.

0010

[Operation] The pulse variable delay circuit of the present invention has an input pulse P
When ULSE (positive pulse) is input, the emitter potential of transistor Q3 changes from the rising edge of input pulse PULSE to the potential {VCC-VBE(Q3)
} to the potential {VCC-I1·R1-VBE(Q3)} with a slope of dV/dt=I2/CL. Furthermore, when the input pulse PULSE falls, the rise of the emitter follower composed of the transistor Q3 and the constant current source I2 is steep, so the potential of the emitter of the transistor Q3 is lower than the potential {VCC-I1・R1-VBE(Q3)}. The potential quickly rises to {VCC-VBE(Q3)}. Therefore, the output of comparator CMP1 (Q1-
The Q1▲bar▼) voltage becomes a positive pulse that is delayed from the input pulse PULSE.

When the output voltage of this comparator CMP1 is input to the second pulse delay circuit, the potential of the emitter of the transistor Q6 becomes the potential {VCC-I
1・R3-VBE(Q6)} to potential {VCC-VBE
(Q6)}. Furthermore, the potential of the transistor Q6 drops at a slope of dV/dt=I2/CL from the falling edge of the input pulse of the second pulse delay circuit. Therefore, the output voltage of the comparator CMP2, which uses the output voltage of the D/A converter DAC1 as a threshold voltage, is a positive pulse with the same pulse width as the input pulse, which is obtained by delaying the input pulse of the second pulse delay circuit.

0012

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings.

FIG. 1 shows an embodiment of the present invention. This figure shows a circuit diagram of a pulse variable delay circuit according to an embodiment. In FIG. 1, parts that overlap with those in FIG. 3 (conventional example) are given the same reference numerals and explanations will be omitted.

In the figure, the pulse variable delay circuit includes transistors Q1 and Q2, a constant current source I1, and a resistor R1.
and R2, an emitter follower consisting of transistor Q3 and constant current source I2, and load capacitance CL.
, operating comparator CMP1, and D/A converter (
It consists of a first pulse delay circuit composed of a DAC 1 (voltage output) and a second pulse delay circuit cascade-connected to the first pulse delay circuit. Note that the second pulse delay circuit includes transistors Q4 and Q5, a constant current source I1, and a resistor R3.
and R4, an emitter follower consisting of a transistor Q6 and a constant current source I2, and a load capacitance CL.
, an operational comparator CMP2, and a D/A converter DAC1 common to the first pulse delay circuit.

Next, the detailed operating principle of this circuit will be explained based on the voltage waveform shown in FIG. Here, the same figure (1)
Consider the case where an input pulse PULSE (positive pulse) as shown in is input. At this time, the potential of the emitter of the transistor Q3 (point A in the figure) is lower than the potential {VCC-VBE(Q3)} from the rising edge t=t0 of the input pulse PULSE, as shown in (2) of the same figure. {VCC
−I1・R1−VBE(Q3)} to dV/dt=I2/
Descend at a slope of CL. Furthermore, when the input pulse PULSE falls at the time t=t3, the rise of the emitter follower composed of the transistor Q3 and the constant current source I2 is steep, so the potential at point A becomes the potential {VCC-I1・R1
-VBE(Q3)} to potential {VCC-VBE(Q3)
} stand up quickly. Therefore, D/A converter D
The output (Q1-Q1▲bar▼) voltage of the comparator CMP1 with the output voltage V0 of AC1 as the threshold voltage is as shown in the same figure (3).
It becomes a positive pulse with a pulse width Wt1 delayed by 1.

Output of this comparator CMP1 (Q1-
When the voltage Q1▲bar▼) is input to the second pulse delay circuit, the potential of the emitter of transistor Q6 (point B in the figure) changes as shown in (4) of the same figure. The potential {VCC-I1・R3-VBE(Q6)} changes from the rising time t=t1 of the output pulse
VCC-VBE(Q6)}. At this time, since the resistance R1=R3, the potential {VCC-I
1・R3−VBE(Q6)} is the potential {VCC−I1・R
1-VBE(Q3)}, and the potential {VCC-VBE
(Q6)} is equal to the potential {VCC-VBE(Q3)}. Furthermore, the potential at point B is dV/dt= from t=t4, that is, from the falling point of the input pulse of the second pulse delay circuit
Descend at a slope of I2/CL. Therefore, the output (Q2-Q2) voltage of the comparator CMP2, which has the output voltage V0 of the D/A converter DAC1 as the threshold voltage, has the input pulse of the second pulse delay circuit Δt2= It becomes a positive pulse with pulse width Wt2 delayed by Δt1+(t2-t1). Here, since t2-t1▲approximately ▼0, the output pulse of the pulse delay circuit according to this embodiment is the input pulse PULSE
is delayed by approximately Δt1, resulting in a pulse with the same pulse width as the input pulse.

[0017]

As described above, according to the present invention, the pulse variable delay circuit is a two-stage cascade connection of the first pulse variable delay circuit and the second pulse variable delay circuit. Since the polarity of the differential input of the first pulse variable delay circuit is opposite to that of the first pulse variable delay circuit, the pulse variable delay circuit can output a pulse with almost the same pulse width as the input pulse, regardless of the threshold voltage. realizable.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a pulse variable delay circuit according to an embodiment of the present invention.

FIG. 2 is a voltage waveform diagram of each part of the pulse variable delay circuit according to the embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional pulse variable delay circuit.

FIG. 4 is a diagram of voltage waveforms at various parts of a conventional pulse variable delay circuit.

[Explanation of symbols]

Q1~Q6 Transistor I1~I2 Constant current source CL Capacitive load R1~R4 Resistance CMP1, CMP2 comparator DAC1 D/A converter PULSE Input pulse

Claims (2)

[Claims] 1. An emitter follower composed of a constant current source and a transistor, a capacitive load connected to the emitter of the transistor, a comparator connected to the emitter of the transistor, and a reference for the comparator connected to the comparator. D/ that controls by supplying potential
a first pulse variable delay circuit comprising an A converter;
The first pulse variable delay circuit has the same configuration as the first pulse variable delay circuit.
What is claimed is: 1. A pulse variable delay circuit comprising: a second pulse variable delay circuit connected in cascade; 2. A differential amplifier composed of a constant current source and two transistors, an emitter follower composed of a constant current source and a transistor using one output of the differential amplifier as input, and a transistor of the emitter follower. A first pulse comprising a capacitive load connected to the emitter, a comparator connected to the emitter of the transistor of the emitter follower, and a D/A converter connected to the comparator and controlling by supplying a reference potential of the comparator. a variable delay circuit, and a second pulse variable delay circuit having the same configuration as the first pulse variable delay circuit and connected in cascade with the first pulse variable delay circuit, A pulse variable delay circuit characterized in that the polarity of the differential input of the circuit is opposite to the polarity of the differential input of the first pulse variable delay circuit.