JPH04212787A - Memory device - Google Patents

Abstract

PURPOSE:To improve soft error resistance by connecting an nMOS transistor of a low threshold voltage between the terminal part of a pair of bit lines and a power source in a static RAM. CONSTITUTION:A pair of the bit lines BL1, BL2 are connected to the plural memory cells 12 of the static RAM and the reading out and writing of data are executed via such bit lines. The nMOS TR 11 of the threshold voltage lower than the ordinary threshold voltage is connected as a bit line load between the terminal parts of the bit lines BL1, BL2 and the power source VCC. The level of the bit lines attains the intermediate value of the case a pMOS transistor and an ordinary nMOS transistor are used for the bit line load. Consequently, the subthreshold current on a high level node side at the time of selection in the selecting transistor decreases and, therefore, the soft error resistance improves.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device such as a static RAM, and more particularly to improvements in its bit line load, decoder, or readout from the bit line.

0002

2. Description of the Related Art A static RAM is a memory device whose memory cells are composed of flip-flops and access transistors, and there is a demand for higher integration and higher speed. Incidentally, in a static RAM, data is generally transferred using a pair of bit lines for writing and reading data from a memory cell, and a MOS is connected at the end of the bit line between it and the power supply voltage Vcc.
A load element consisting of a transistor is provided.

FIG. 11 shows an example of the load MOS transistor, which is an example of a PMOS transistor. In FIG. 11, the memory cell is a pair of drive transistors 1
01, 101, a pair of resistive loads 102, 102, and selection transistors 103, 10 whose gates are the word line WL.
A pair of bit lines BL1 and BL2 are provided to be connected to this memory cell. At the ends of each bit line BL1, BL2, normally-on type pMOS transistors 104, 104 are connected as bit line loads.
is provided. The gate of the pMOS transistor 104 is grounded, and the source is supplied with the power supply voltage Vcc. Therefore, the level of bit lines BL1 and BL2 can be raised to near power supply voltage Vcc.

As another example, a device in which the load MOS transistor is an nMOS transistor is also known. FIG. 12 shows an example in which the bit line load is formed by an nMOS transistor. As shown in FIG. 12, memory cells and bit lines BL1 and BL2 similar to those in the device shown in FIG. nMOS transistor 1
05,105 are provided. nMOS transistor 10
Power supply voltage Vcc is supplied to the gate and drain of 5. Therefore, the level of bit lines BL1 and BL2 is Vcc-
Vth.

[0005] By providing such a bit line load, data in the cell can be read without destroying it, but a decoder such as a row decoder or a column decoder is used to select a memory cell. FIG. 13 is a circuit diagram of a conventional decoder. n input signals IN1 to INn are supplied to the gates of series-connected nMOS transistors M1 to Mn, respectively, and the nMOS transistors M at the end
The source of n is grounded. The drain of the nMOS transistor M1 at the end is an output node 110, and the input terminal of an inverter 112 is connected to this output node 110, and the output of the inverter 112 is used as the output of the decoder. This decoder also has a normally-on type load M
OS transistor is used, pM with gate grounded
The drain of the OS transistor 111 is the output node 110
The power supply voltage Vcc is supplied to the source thereof. The decoder shown in FIG. 13 can improve delay compared to a CMOS-configured decoder with a relatively large gate capacitance.

[0006]

[Problem to be solved by the invention] First, static R
For the AM bit line load circuit, pMOS load, n
Both MOS loads have the following problems. That is, when a bit line load is formed by a pMOS transistor, the levels of bit lines BL1 and BL2 are pulled up to approximately the power supply voltage Vcc level. However, when the sense amplifier has a CMOS configuration, the maximum sensitivity of the sense amplifier is lower than the power supply voltage Vcc level, and therefore sufficient sensitivity cannot be obtained, making it difficult to increase the speed. Next, when a bit line load is formed by an nMOS transistor, the level of bit lines BL1 and BL2 is set to the power supply voltage Vc.
However, when the word line WL is selected, the level of the word line WL becomes the power supply voltage Vcc, so the bit line BL1, A subthreshold current flows toward BL2 through the selection transistor 103, resulting in a decrease in soft error resistance and data retention ability.

Next, in the decoder shown in FIG. 13, it is difficult to quickly charge and discharge the level of the output node 110. That is, when trying to raise the level of the output node 110 quickly, it is necessary to increase the current driving ability of the pMOS transistor 111, and when trying to bring down the level of the output node 110 quickly, it is necessary to increase the current driving ability of the pMOS transistor 111.
It is necessary to lower the current driving ability of 11. Generally M.O.
The current drive capability of an S transistor is determined by the channel size, etc., so both high and low current drive capabilities are set to the same M
An OS transistor cannot have this. Therefore, with conventional decoders, it has been difficult to achieve sufficient speed.

Therefore, in view of the above-mentioned technical problems, the present invention aims to provide a memory device having a circuit configuration for achieving high speed, and more specifically, it is an object of the present invention to provide a memory device having a circuit configuration to realize high speed. It is an object of the present invention to provide a memory device having a circuit configuration that can obtain a high bit line level, and to provide a memory device that can realize high-speed decoding.

[0009]

[Means for Solving the Problems] As an example of a memory device having a circuit configuration in which a suitable bit line level can be obtained from a readout surface, etc., the present invention provides a low threshold voltage of a load MOS transistor provided at the end of a bit line. It is characterized by using an nMOS transistor, or by providing a level conversion means in the middle of the bit line.

First, the memory device of the present invention, which uses an nMOS transistor with a low threshold voltage as a load MOS transistor, has a plurality of memory cells arranged and a bit line for transferring data to the memory cells. The low threshold voltage nMOS transistor is provided at the terminal end of the bit line. A power supply voltage is supplied to the drain of this low threshold voltage nMOS transistor. An nMOS transistor with a threshold voltage lower than that of a normal nMOS transistor can be a normally-on type, or an nMOS transistor with a low threshold voltage connected in parallel with an nMOS transistor with a higher threshold voltage. may be used selectively during reading and writing. In a memory device that selectively uses nMOS transistors with different threshold voltages as load MOS transistors, the nMOS transistor with a higher threshold voltage is used during writing, and the nMOS transistor with a lower threshold voltage is used during reading.
S transistors are used.

Next, the memory device of the present invention, in which a level conversion means is provided in the middle of a bit line, has a plurality of memory cells arranged, a bit line for transferring data to the memory cells, and a level converting means for the bit line. It has a load MOS transistor provided between the terminal end and the constant voltage line, and a sense amplifier that amplifies the potential of the bit line, and the level converting means converts the voltage from the potential side of the constant voltage line to the sense amplifier. The level of the bit line is converted toward the side where the sensitivity becomes higher.

Next, in the memory device of the present invention for realizing high-speed decoding, a load MOS transistor and a gate circuit to which a plurality of signals are input are connected in series between the first level and the second level. It has a decoder that is connected to the gate circuit and amplifies and outputs the level of a node between the gate circuit and the load MOS transistor, and the load MOS transistor has a normally-on type M
The device is characterized in that it is configured by connecting an OS transistor and a MOS transistor with a high current drive capability in parallel, and the MOS transistor with a high current drive capability is feedback-controlled based on the level of the node. Here, MOS transistors having different current drive capabilities can be configured by having different gate widths, gate lengths, threshold voltages, etc., for example. Further, as an example of the feedback control, the delayed signal may be formed, and the structure for forming the delayed signal may be, for example, a structure in which an inverter is connected to the node. .

[0013]

[Operation] First, in a memory device that uses a low threshold voltage nMOS transistor as a bit line load, the bit line can be charged to a level intermediate between a normally-on pMOS transistor and an nMOS transistor, and the pMOS
Higher sensitivity is achieved than when the transistor is used as the bit line load, and the subthreshold current on the high level node side when selecting the selection transistor is suppressed more than when the nMOS transistor is used as the bit line load. In addition, even in memory devices that have level conversion means in the middle of the bit line, the level conversion means amplifies the potential of the bit line in the sensitive area of the sense amplifier, resulting in higher speeds due to higher sensitivity. will also be realized. Next, in a memory device having a decoder in which one of parallel-connected load MOS transistors with different current drive capacities is feedback-controlled, a signal is sent to the combined node at the rise and fall of the node after a signal is input. The current drive capability can be changed significantly, and as a result, both high-speed rise and fall can be achieved.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the drawings.

[First Embodiment] FIG. 1 shows the main parts of a memory device according to this embodiment. This embodiment is a static RAM, and the plurality of memory cells 12 arranged in a matrix are composed of flip-flops and selection transistors (not shown), and the selection transistors are turned on or off by word lines. controlled. Each memory cell 12 has a pair of bit lines B
L1 and BL2 are connected, and these bit lines BL1 and BL
Reading and writing of data is performed via 2. Reading is performed by a sense amplifier (not shown) connected to the bit lines BL1 and BL2. An nMOS transistor 11 having a lower threshold voltage Vth (L) than usual is connected as a bit line load to the terminal ends of these bit lines BL1 and BL2, respectively. The drain and gate of this nMOS transistor 11 are connected to a power supply voltage V
cc is supplied, and the source is the bit line BL1.
, BL2 are connected.

With this structure, the level of the bit line can be adjusted by using pMOS as the bit line load, as shown in FIG.
It is possible to set the Vcc-Vth (L) level intermediate between the Vcc (power supply voltage) level when a transistor is used and the Vcc-Vth (normal threshold voltage) when an nMOS transistor is used as the bit line load. can. As a result, compared to the case where a pMOS transistor is used,
Since the bit line level can be set where the sense amplifier has high sensitivity, high sensitivity and high speed sensing can be achieved. Furthermore, since the level of the bit line is increased compared to the case where an nMOS transistor is employed at the same time, the subthreshold current on the high level node side during selection in the selection transistor can be reduced. Therefore, soft error resistance is improved.

[Second Embodiment] This embodiment is a modification of the first embodiment, and is an example in which the bit line load is formed by two nMOS transistors connected in parallel and having different threshold voltages. Note that the memory cell 12 and bit lines BL1 and BL2 are the same as those in the first embodiment, and for the sake of brevity, redundant explanation will be omitted. As shown in FIG. 2, the bit line load consists of a first nMOS transistor 13 and a second nMOS transistor connected in parallel.
It is composed of a transistor 14. The drains of the nMOS transistors 13 and 14 are both supplied with the power supply voltage Vcc, and their respective sources are commonly connected to the bit lines BL1 and BL2. The first nMOS transistor 13 has a threshold voltage Vth (L) lower than the normal threshold voltage Vth. For example, the threshold voltage Vth (L) is set to be about 0.2 to 0.4 V lower than the normal threshold voltage Vth. The second nMOS transistor 14 has a normal threshold voltage Vth, but is not limited to this, and may have a configuration having a threshold voltage higher than normal. Low threshold voltage Vt
h(L) first nMOS transistor 13 is CE/
A WE (chip enable/write enable) signal is supplied to the gate via an inverter 15. Therefore,
The nMOS transistor 13 is turned on when the CE/WE signal is at a low level, and the potentials of the bit lines BL1 and BL2 are raised to Vcc-Vth (L). Also, the second
The CE and WE signals are supplied to the gate of the nMOS transistor 14. Therefore, the nMOS transistor 14
When the E.WE signal is at a high level, it is turned on, and the potentials of the bit lines BL1 and BL2 are set to Vcc-Vth. C
The E/WE signal is set to low level when reading, and set to high level when writing. Therefore, when reading, nMOS
Transistor 13 is used as a bit line load, and nMOS transistor 14 is used as a bit line load during writing.

With this configuration, the device of this embodiment, like the circuit of the first embodiment, sets the level of the bit line at the point where the sensitivity of the sense amplifier is high during reading. High sensitivity and high speed sensing can be achieved. Furthermore, during reading, the subthreshold current on the high-level node side of the selection transistor at the time of selection is reduced, and soft error resistance is improved. Furthermore, in the memory device of this embodiment, since the nMOS transistor 14 with the normal threshold voltage Vth is used as a bit line load during writing, power consumption during writing can be reduced, speeding up write recovery, and bump problem. It becomes possible to eliminate the problem.

[Third Embodiment] This embodiment is an example of a memory device including a decoder having a feedback-controlled PMOS load transistor. Figure 4 shows the main parts. As shown in FIG. 4, the decoder according to this embodiment is a NAND gate type decoder arranged between a power supply voltage Vcc and a ground voltage GND, and a plurality of input signals IN1 to INn are connected in series. nMO of
It is input to the gates of S transistors Q1 to Qn, respectively. A ground voltage GND is supplied to the source of the nMOS transistor Qn at one end of the nMOS transistors Q1 to Qn connected in series, and the drain of the nMOS transistor Q1 at the other end is the output node 21. The output signal is determined by changing the level of this output node 21. Output node 21 has a pair of pMOS transistors 22 and 23 connected in parallel to power supply voltage Vcc. The pMOS transistor 23 is of normally-on type, its gate is grounded, and its source is connected to the power supply voltage Vc.
c is supplied. The pMOS transistor 22 has its source supplied with the power supply voltage Vcc, and its gate controlled by a signal from the delay circuit 24. The current driving capability of the pMOS transistor 22 is set higher than that of the pMOS transistor 23. These different current drive capacities are adjusted by the gate width, and in this example, the pMO
For example, the gate width of the S transistor 22 is 3 pM
The gate width of the OS transistor 23 is, for example, 1. Furthermore, different current drive capabilities may be adjusted by gate length, threshold voltage, or the like. The delay circuit 24 feeds back the level of the output node 21 with a delay, and
This is a circuit for controlling the transistor 22. The input terminal of an inverter 25 is connected to the output node 21, and its output terminal is used as the output terminal of the decoder.

The decoder according to this embodiment having such a structure changes the output level by NANDing the input signals IN1 to INn, and in particular, it is possible to shorten the rise time and fall time of the output node 21. can. That is, both the pMOS transistors 22 and 23 operate to pull up the level of the output node 21, but only the normally-on type pMOS transistor 23 is turned on after the level of the output node 21 is sufficiently raised and when the level falls. state and pMOS transistor 22
is in the off state. In particular, each nMOS transistor Q1
〜Qn turns on, the level of the output node 21 falls, but at this falling time, only the pMOS transistor 23 with low current driving ability is in the on state, so the current of the nMOS transistors Q1 to Qn decreases. Output node 21 is pulled down to the ground voltage side at high speed in view of the balance with driving capability. Furthermore, when the output node 21 rises, the PMOS transistor 22 is turned on by the feedback control by the delay circuit 24 while the level of the output node 21 is low, and even after the level of the output node 21 rises to a certain extent, the delay circuit 24 It is pulled up by the delayed and controlled pMOS transistor 22. At this time, in addition to the pMOS transistor 23, the pMOS transistor 22 having a high current driving ability participates in the pull-up operation, so that the level of the output node 21 is pulled up at high speed.

In this way, in the decoder according to this embodiment, the combined current driving capability of the pMOS transistors 22 and 23 increases when the output node 21 is pulled up, and when the output node 21 is pulled down, the combined current driving capability of the pMOS transistors 22 and 23 increases.
, 23 becomes lower. Therefore, high-speed level transition of the output node 21 is realized.

[Fourth Embodiment] This embodiment is a modification of the third embodiment, and is an example in which the delay circuit is configured with an inverter, as shown in FIG. Note that in FIG. 5, the gate circuit portion and the pMOS transistor are the same as those in the third embodiment, and the same reference numerals are used in the figure to omit redundant explanation. The decoder according to this embodiment uses an inverter 27 instead of a delay circuit, and the input terminal of the inverter 27 also connects to the inverter 26 which is the output terminal of the decoder.
is connected to the output terminal of The input terminal of the inverter 26 is connected to the output node 21, and the output terminal of the inverter 27 is connected to the pMOS transistor 2 with high current driving ability.
Connected to gate 2. With such a circuit configuration, similarly to the third embodiment, the rise and fall of the output node 21 can be made faster.

[Fifth Embodiment] This embodiment is a modification of the fourth embodiment, and is an example controlled by two input signals IN1 and in2. That is, in the fourth embodiment, n input signals IN1 to INn
However, in this embodiment, there are two inputs, and in particular, one signal in2 is directly connected to the source and drain of the nMOS transistor Qx.
Only one MOS transistor is required. Note that the signal in2 itself is supplied to the decoder in an inverted relationship compared to the signal IN2 of the third embodiment. Output node 2
The same applies to increasing the speed of the rise and fall of 1.

[Sixth Embodiment] This embodiment is an example of a memory device in which a level conversion circuit is provided in the middle of a bit line, and has the main part structure shown in FIG. The memory device of this embodiment has a pair of bit lines BL1 and B for transferring data to a plurality of memory cells 32 arranged in a matrix, only one of which is shown for simplicity.
It has L2. The memory cell 32 is composed of a flip-flop circuit and a selection transistor (not shown). A PMOS transistor 33 for load is provided between the terminal ends of the bit lines BL1 and BL2 and the power supply voltage line.
The potential of these bit lines BL1 and BL2 is set to the power supply voltage Vcc.
Pulled up to the side. Furthermore, bit lines BL1, BL
2 is provided with column selection transistors 35 and 36,
Column selection transistors 35 and 36 are controlled by column selection signal Y. The column selection transistors 35, 3
A level conversion circuit 31 for converting the level of the bit line is provided between the sense amplifier 6 and the sense amplifier 37 for amplifying the level of the bit line BL1, BL2. By using this level conversion circuit 31, bit lines BL1, BL2
The level of the bit line is shifted from the potential on the power supply voltage Vcc side to the Vcc/2 side, and therefore the sensitivity of the sense amplifier 37 increases.

FIG. 8 shows a specific example of the level conversion circuit 31. The level conversion circuit 31 includes a pair of bit lines BL1,
It consists of current mirror type amplifier circuits 46 and 47 provided for each bit line in the middle of BL2. The amplifier circuit 46 includes an nMOS transistor 4 serving as a current source on the power supply voltage Vcc side.
1 and 42, and these nMOS transistors 41 and 4
A pair of nMOS transistors 45, 45 are connected in series to the transistors 2 and 2, respectively, and are connected in a current mirror manner. n
The gate of MOS transistor 41 is connected to bit line BL1, and the gate of nMOS transistor 42 is connected to bit line BL2. Current mirror connected nMO
The sources of the S transistors 45, 45 are commonly grounded,
The output signal is taken out from the source of the nMOS transistor 41. Similarly, the amplifier circuit 47 also receives the power supply voltage Vcc.
A pair of nMOS transistors having nMOS transistors 43 and 44 serving as current sources on the side and connected in series and current mirror connected to these nMOS transistors 43 and 44, respectively.
It has OS transistors 45, 45. The gate of the nMOS transistor 43 is connected to the bit line BL1, and the nM
The gate of OS transistor 44 is connected to bit line BL2. The sources of the current mirror-connected nMOS transistors 45 and 45 are commonly grounded, and the output signal is n
It is taken out from the source of the MOS transistor 44.

By using such a level conversion circuit 31, level conversion as shown in FIG. 10 is performed. Figure 8
In the circuit, if the level of the bit lines BL1 and BL2 on the memory cell side of the level conversion circuit 31 is Φ1, and the level of the bit lines BL1 and BL2 on the sense amplifier side is Φ2, then the level Φ1 is close to the power supply voltage Vcc. However, it can be seen that the level Φ2 has a level close to the voltage Vcc/2. In the circuit of FIG. 8, the bit line BL1 on the memory cell side
, BL2 are received by the nMOS transistors 41 to 44, and are amplified separately by current mirror type amplifier circuits 46 and 47, so that such level conversion is performed. Since this level Φ2 close to Vcc/2 is a level to which the next sense amplifier 37 is highly sensitive, the sense amplifier 37 operates at high speed.

[Seventh Embodiment] This embodiment is an example of a memory device having a modification of the level conversion circuit 31 of FIG. 8, and has the configuration shown in FIG. 9. That is, the current mirror connected nMOS transistors 45, 45 in FIG. 8 are replaced with a pair of latch type cross-coupled nMOS transistors 48, 48. With such a configuration as well, level conversion can be achieved and the sense amplifier 37 can operate at high speed.

[0028]

Effects of the Invention As mentioned above, the low threshold voltage n of the present invention
In memory devices that use MOS transistors as bit line loads, normally-on pMOS transistors and nMOS
The bit line can be charged to an intermediate level of the transistor. Therefore, high sensitivity and high-speed operation are achieved, and the subthreshold current on the high-level node side when selecting the selection transistor is suppressed, improving soft error resistance. Furthermore, in the memory device of the present invention in which a level conversion means is provided in the middle of the bit line, the level conversion means
The potential of the bit line is amplified in the highly sensitive region of the sense amplifier, resulting in higher speeds due to higher sensitivity. In addition, in the memory device of the present invention having a decoder in which one of load MOS transistors having different current drive capacities and connected in parallel is feedback-controlled, the combined node is As a result, high-speed rise and fall can be achieved at the same time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an example of a memory device using a low threshold voltage nMOS transistor of the present invention as a bit line load.

[Figure 2]
A circuit diagram of another example of a memory device using a low threshold voltage nMOS transistor of the present invention as a bit line load

[Figure 3] Figure 1
A diagram comparing the bit line levels of a memory device with the bit line levels of a conventional memory device.

FIG. 4 is a circuit diagram of an example of a memory device having a feedback-controlled load transistor of the present invention.

FIG. 5 is a circuit diagram showing a modification of the decoder circuit of the memory device in FIG. 4;

FIG. 6 is a circuit diagram showing a modification of the decoder circuit of the memory device in FIG. 5;

FIG. 7 is a circuit diagram of an example of a memory device having level conversion means of the present invention.

FIG. 8 is a circuit diagram showing a level conversion circuit which is a main part of the memory device in FIG. 7;

FIG. 9 is a circuit diagram showing another example of a level conversion circuit which is a main part of the memory device in FIG. 7;

FIG. 10 is a waveform diagram for explaining the level conversion operation by the level conversion circuit in FIG. 8;

FIG. 11 is a circuit diagram showing an example of a bit line load circuit using pMOS transistors of a conventional memory device.

FIG. 12 is a circuit diagram showing an example of a bit line load circuit using nMOS transistors of a conventional memory device.

FIG. 13 is a circuit diagram showing an example of a decoder circuit of a conventional memory device.

[Explanation of symbols]

11, 13...NMOS transistor 12 with low threshold voltage
, 32...memory cell 14, Q1-Qn, Qx...nMOS transistor 21...
Output nodes 22, 23...pMOS transistor 24...delay circuit 26, 27...inverter 31...level conversion circuit 41-45...nMOS transistor 46, 47...amplifier circuit BL1, BL2...bit line

Claims (4)

[Claims] 1. A memory device comprising a plurality of memory cells arranged, a bit line for transferring data to the memory cells, and a load MOS transistor provided at the terminal end of the bit line, wherein the load MOS transistor A normally-on type nMOS transistor whose drain is supplied with a power supply voltage is used as the
A memory device characterized in that the threshold voltage of an S transistor is lower than that of a normal NMOS transistor. 2. A memory device comprising a plurality of memory cells arranged, a bit line for transferring data to the memory cells, and a load MOS transistor provided at the terminal end of the bit line, wherein the load MOS transistor As shown in FIG.
and a second nMOS transistor having a higher threshold voltage than the first nMOS transistor, the first nMOS transistor is turned on during reading, and the second nMOS transistor is turned on during writing.
A memory device characterized in that a transistor is turned on. 3. A load MOS transistor and a gate circuit to which a plurality of signals are input are connected in series between the first level and the second level, and the gate circuit and the load MOS transistor are connected in series.
In a memory device provided with a decoder that amplifies and outputs the level of a node between transistors, the load MOS transistor is composed of a normally-on type MOS transistor with a low current driving ability and an MOS transistor with a high current driving ability.
1. A memory device comprising an OS transistor connected in parallel, and wherein the MOS transistor having a high current driving ability is feedback-controlled based on the level of the node. 4. A plurality of memory cells arranged, a bit line for transferring data to the memory cells, and a load MO provided between the terminal end of the bit line and a constant voltage line.
In a memory device having an S transistor and a sense amplifier that amplifies the potential of the bit line, level conversion converts the level of the bit line from the potential side of the constant voltage line to the side where the sensitivity of the sense amplifier becomes higher. A memory device characterized in that a means is provided in the middle of each bit line.