JPH04211200A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent power switching devices and their control circuits mounted on a single metallic substrate as modules and connected in bridges from making malfunctions due to noise, etc. CONSTITUTION:The first and second control circuits 13 and 14 are formed on an aluminum substrate 31 respectively through the first insulating layer 32, first and second shield patterns 101 and 104, and second and third insulating layers 105 and 106 and, at the same time, the first and second shield patterns 101 and 104 are respectively fixed at potentials corresponding to the potentials of the output electrodes of the first and second power transistors 1 and 2. When noise is impressed upon the current routes of the first and second power switching elements with respect to the metallic substrate, the noise also appears in their control circuits with respect to the metallic substrate. As a result, the state becomes equivalent to such a state where no noise exists in the control circuits when the state is viewed from the output electrodes of the first and second power switching elements. Therefore, such an effect is obtained that no malfunction is caused by the noise.

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to semiconductor devices, and more particularly to prevention of malfunctions due to noise or the like in bridge-connected power switching devices and their control circuits that are modularized on a single metal substrate. [0002]

[Prior Art] Fig. 12 shows a three-dimensional
FIG. 1 is a circuit diagram showing a conventional inverter circuit with a phase bridge configuration. This inverter circuit includes six power NPN transistors 1-6. Transistors 1 and 2, 3 and 4, 5
and 6 are each connected to the totem pole, and the power terminal P. connected in parallel between N. A high voltage is applied between power supply terminals P and N, with the terminal P side being positive. The connection point between the emitter of transistor 1 and the collector of transistor 2 is U.
The connection point between the emitter of transistor 3 and the collector of transistor 4 is connected to the output terminal V of phase ■, and the connection point between the emitter of transistor 5 and the collector of transistor 6 is connected to the output terminal U of phase W. Connected to W. Flywheel diodes 7-12 are connected between the emitter and collector of each transistor 1-6, respectively.

Control circuits 13 to 18 for controlling on/off of the transistors 1 to 6 are connected to the bases of the transistors 1 to 6, respectively. Control circuit 13~
18 includes drivers 25 to 30, respectively, for receiving control signals applied to input terminals 19 to 24 and generating base drive signals for transistors 1 to 6. Transistors 1-6 are turned on/off in response to control signals input to input terminals 19-24. The control circuits 13 to 18 also
A protection circuit that detects overcurrent, overvoltage, overheating, etc. and takes appropriate protective action is included as necessary. Furthermore, the upper arm side control circuits 13, 15.17 have input terminals 19, 21
It also includes an interface circuit such as a photocoupler for level-shifting a low voltage level control signal applied to the power source 23 to a high voltage level. The control circuits 13 to 18 are IC
It consists of discrete transistors, resistors, capacitors, etc. Upper arm side control circuit 13. 15
．． 17 power supplies, each with an individual power supply VUP,
VVP and VWP are provided, and the control circuit 1 on the lower arm side
A common power supply VN is provided as a power supply for 4, 16, and 18. [0004] The circuit of FIG. 12 has power supplies Vup, Vvp,
Vwp. Except for VN, they are formed modularly on a single metal substrate. Upper arm side power supply VUP, VVP, Vl
IP can also be generated within the module by boosting the power supply VN on the lower arm side with a charge pump circuit formed on a metal substrate. [00051] FIG. 13 is a cross-sectional view showing the structure of the U-phase portion when the circuit of FIG. 12 is formed on a single metal substrate. An insulating layer 32 is formed on an aluminum substrate 31,
A copper pattern 33 similar to the wiring pattern of a printed wiring board is formed thereon. The power transistors 1, 2 and control circuits 13 and 14 are connected to the copper pattern 3 by soldering etc.
Fixed on 3. Aluminum wire 34.35 is the base wire and aluminum wire 36.37 is the emitter wire. The copper patterns 33 are connected appropriately outside the diagram, and some of the connections are connected to the connecting wire 38.
．． 39 isometrically shown. In this way, the U-phase circuit portion of FIG. 12 is formed on a single aluminum substrate 31,
External terminal U also formed on the aluminum substrate 31
, N, P, 19. It is connected to the outside via 20. [00061 FIG. 14 is a sectional view showing an enlarged portion of FIG. 13 on the upper arm side. Since the copper pattern 33 and the aluminum substrate 31 face each other with the insulating layer 32 in between, a capacitance is formed between them. That is, the copper pattern 33 is capacitively coupled to the aluminum substrate 31. In FIG. 14, CI is the capacitance between the aluminum substrate 31 and the copper pattern 33a to which the output terminal u (therefore, the emitter of the power transistor 1, the collector of the power transistor 2, and the negative side of the power supply VuP) is connected. The capacitance between the connected copper pattern 33b and the aluminum substrate 31 is shown as 02. Further, the pattern distance between the copper patterns 33a and 33b is shown as C3. The terminal S connected to the aluminum substrate 31 is for convenience of explanation. [0007]

[Problem to be Solved by the Invention] Now, in order to consider how the noise applied between terminals U and 8 affects terminal 19, we will focus only on the capacitances C1, C2, and C3, and consider the other capacitances. The capacity of is ignored. [0008] FIG. 15 is an equivalent circuit diagram showing capacitors C1, C2, and C3. The area of copper pattern 33a is copper pattern 3
3b, the capacitor CI is larger than the capacitor C2. Also, since the capacitance C3 is the inter-pattern capacitance,
It is extremely small compared to the capacitances C1 and C2. Therefore, the following relationship holds. [0009]

[Equation 1] C1>C2>>C3 [00101 Now, suppose that av/at (U) is applied to the terminal S as noise to the terminal U. At this time,
Noise dV/dt (
19) can be expressed by the following equation. [0011]

[Equation 2] dV dV C2-(
19) = −(U)・□ dt dt C2+C3[
0012] From the relationship of equation 1,

[Equation 3] dv dV - (one) 4- (U) dt dt [0013] Therefore, for terminal U, terminal 19 has
The same level of noise will appear on the terminal S as that applied to the terminal U. As is clear from FIG. 12, the terminal U is an output terminal connected to the output electrode (emitter) of the power transistor 1, and the terminal U is an output terminal connected to the output electrode (emitter) of the power transistor 1.
The reference potential of the control circuit 13 is provided. On the other hand, terminal 1
9 is an input terminal of the control circuit 13. There is a problem in that the circuit malfunctions due to noise appearing at the terminal 19, which provides the control input of the control circuit 13, with respect to the terminal U, which provides the reference potential of the control circuit 13. In addition, such noise appears not only in the input terminal 19 but also in various signal paths of the control circuit 13, and for example, protect functions (overcurrent,
This has the disadvantage that it may cause malfunctions such as activation of overvoltage protection (overvoltage protection, etc.). Furthermore, such inconvenience is caused not only by the terminal U but also by the terminals V and W with respect to the aluminum substrate 31.
. The same problem occurs when noise is applied to P and N (that is, the current paths of power transistors 1 to 6). [0014] The present invention was made to solve the above-mentioned problems, and provides a semiconductor comprising a bridge-connected power switching device and its control circuit arranged on a metal substrate, which does not malfunction due to noise. The purpose is to obtain equipment. [0015] Another object of the invention is to provide a semiconductor device that can achieve the above main object and also reduce leakage current to a metal substrate when a power switching device is operated at high speed. There is a particular thing. [0016]

[Means for Solving the Problems] A semiconductor device according to claim 1 includes a metal substrate, a first insulating layer formed on the metal substrate, and a totem pole connection formed on the first insulating layer. The first thing that was done was A first power switching element comprising a second power switching element and a conductor formed on the first insulating layer. a second shield pattern, a second insulating layer formed on the first shield pattern, a third insulating layer formed on the second shield pattern, and a third insulating layer formed on the second insulating layer. ,
a first control circuit for controlling on/off of the first power switching element; formed on a third insulating layer;
A second control circuit for controlling on/off of the second power switching element, and a first connection for connecting the first shield pattern to a potential corresponding to the potential of the output electrode of the first power switching element. and second connecting means for connecting the second shield pattern to a potential corresponding to the potential of the output electrode of the second power switching element. [0017] In the semiconductor device according to the second aspect of the invention, in the semiconductor device according to the first invention, at least the first. A third shield pattern formed on the first insulating layer and to which a constant reference voltage is applied is provided between the second shield pattern and the first insulating layer; A fourth shield pattern formed between the first or second shield pattern.
An insulating layer is interposed therebetween. [0018]

[Operation] 1. in the first invention. The second control circuit is
a first insulating layer; a first insulating layer on the metal substrate; a second shield pattern; and a third insulating layer, respectively. For this reason, 1. Direct capacitive coupling between the second control circuit and the metal substrate is eliminated. On the other hand, the first. Second
control circuit and the first control circuit. The capacitance between the second shield pattern and the second shield pattern is large. 1st. The second shield pattern is the first. They are each fixed at a potential corresponding to the potential of the output electrode of the second power switching element, and therefore the first... When noise is applied to the current path of the second power switching element, noise also appears in the control circuit with respect to the metal substrate. As a result, 1. When viewed from the output electrode of the second power switching element, it is equivalent to having no noise in the control circuit, and malfunctions of the control circuit can be avoided. [0019] In the semiconductor device according to the second invention, since the third shield pattern is fixed at a constant reference potential, the first. Direct capacitive coupling between the second shield pattern and the metal substrate is eliminated, and therefore leakage current flowing through the metal substrate as the power switching element is turned on and off is extremely reduced.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing an inverter circuit having a three-phase bridge configuration, which is an embodiment of a semiconductor device according to the present invention. Since the circuit configuration is the same as the conventional inverter circuit shown in FIG. 12 described above, the explanation will be omitted. [00211 In this embodiment, the upper arm side control circuit 1
3.15.17 are each individual shield pattern 1
01, 102, and 103. Further, the control circuits 14, 16, and 18 on the lower arm side are formed on a common shield pattern 104. shield pattern 1
01.102, 103 are output terminals U, V, respectively.
The potential of W (i.e. power transistor 1. 3. 5
The shield pattern 104 is fixed to the potential of the power supply terminal N (that is, the potential of the output electrodes (emitters) of the power transistors 2.4.6). Control circuits 13, 15.17 each include power transistors 1. 3. The control circuits 14, 16.18 operate based on the emitter potential of the power transistors 2, 4. 6, the potentials of the shield patterns 101, 102, and 103 are set to the control circuit 1, respectively.
3. 15. The potential of the shield pattern 104 is maintained at the same potential as the reference potential of the control circuit 14, 16, 18.
It will be kept at the same potential as the common reference potential of. [0022] FIG. 2 is a cross-sectional view showing the structure of the U-phase portion when the circuit of FIG. 1 is formed on a single metal substrate. An insulating layer 32 is formed on an aluminum substrate 31, and a copper pattern 33 and shield patterns 101 and 104 similar to the wiring pattern of a printed wiring board are formed thereon. Shield patterns 101 and 104 are copper patterns 3
Like 3, it has a copper pattern. The copper pattern 33 may have the same thickness as the shield patterns 101 and 104, or may be thicker than that. If they have the same thickness, both can be formed at the same time. [0023] Insulating layers 105 and 106 are formed on the shield patterns 101 and 104, respectively, and a copper pattern 41 similar to the copper pattern 33 is formed thereon. The power transistors 1 and 2 are fixed on the copper pattern 33 by soldering or the like as in the conventional case, and the power control circuits 13 and 1
4 is fixed on the copper pattern 41 by soldering or the like. [0024] A through hole 107 is provided in the insulation 105, and the power supply Vup is connected through the through hole 107.
The shield pattern 101 is connected to the copper pattern 41a connected to the negative side (ie, the output electrode (emitter) side of the power transistor 1). Further, a through hole 108 is provided in the insulating layer 106, and a copper pattern 41b and a shield pattern 104 are connected to the negative side of the power supply VN (that is, the output electrode (emitter) side of the power transistor 2) through the through hole 108.
are connected. [0025] Aluminum wires 34.35 are base wires and aluminum wires 36.37 are emitter wires. The copper patterns 33 or the copper patterns 41 are appropriately connected to each other outside the drawings, and the copper patterns 33 and 41 can also be appropriately connected by aluminum wire or the like. Connect some of the connections with line 4
2.43 isometrically shown. In this way, the U-phase circuit portion of FIG. 1 is formed on a single aluminum substrate 31, and the external terminals U, N, P, 19. also formed on the aluminum substrate 31. It is connected to the outside via 20. [0026] Note that the external terminals U, N, and P are connected to the insulating layer 3.
2, and external terminals 19.20 are formed on the insulating layers 101.104, respectively. [0027] FIG. 3 is an enlarged cross-sectional view of a portion of FIG. 2 on the upper arm side. Since the copper pattern 33 and the aluminum substrate 31 face each other with the insulating layer 32 in between, a capacitance is formed between them. Also, copper pattern 4
1 and the shield pattern 101 also face each other with the insulating layer 105 in between, so a capacitance is formed between them. In FIG. 3, the capacitance between the aluminum substrate 31 and the copper pattern 33a connected to the output terminal U (therefore, the emitter of the power transistor 1, the collector of the power transistor 2, and the negative side of the power supply Vup) is shown as 01. This capacitance CI includes the capacitance between the shield pattern 101 and the aluminum substrate 31 because the potential of the shield pattern 101 is the same as the potential of the output terminal U. Further, the capacitance between the copper pattern 41c to which the input terminal 19 is connected and the shield pattern 101 is indicated as 04. Furthermore, the capacitance for direct capacitive coupling between the copper pattern 41c and the aluminum substrate 31 is added to C5.
shall be. Terminal S connected to aluminum substrate 31
is for convenience of explanation. Now, terminals U and S
In order to consider how the noise applied between them affects the terminal 19, we will focus only on the capacitances CI, C4, and C5, and ignore the other capacitances. [00281 FIG. 4 is an equivalent circuit diagram showing capacitors C1, C4, and C5. Since the combined area of copper pattern 33a and shield pattern 101 is larger than the area of copper pattern 41c, capacitance C1 is larger than capacitance C4. The capacitance C5 is the capacitance of direct capacitive coupling between the copper pattern 41c and the aluminum substrate 31, but the shield pattern 101 is interposed between the copper pattern 41c and the aluminum substrate 31, preventing direct capacitive coupling between the two. Therefore, the capacitance C5 is substantially equal to zero. Therefore, the following relationship holds true. [0029]

[00301] Now, suppose that av/at (U) is applied to the terminal S as noise to the terminal U. At this time,
Noise dV/dt (
19) can be expressed by the following equation. [0031]

[Formula 5] dV dV C5-(19)
= −(U)・□ dt dt C4+C5[0032
] From the relationship of equation 4,

dV - (19) 40 dt [0033], and even if noise is applied to the terminal U compared to the terminal S, no noise will appear at the terminal 19 compared to the terminal U. That is, the shield pattern 10
1 is kept at the same potential as terminal U, so if noise is applied to terminal U with respect to terminal S (that is, aluminum substrate 31), the potential of shield pattern 101 will also change, and the shield pattern 101 and capacitance will change accordingly. The potential of the coupled copper pattern 41c (ie, terminal 19) will also vary. Therefore, when viewed from terminal U, terminal 19
is equivalent to having no noise. [0034] The terminal U is an output terminal connected to the output electrode (emitter) of the power transistor 1, and also provides a reference potential for the control circuit 13 of the power transistor 1. On the other hand, terminal 19 is an input terminal of control circuit 13. Even if noise is applied to the terminal U of the aluminum substrate 31, the terminal U provides the reference potential of the control circuit 13.
Since no noise appears at the terminal 19 that provides the control input of the control circuit 13 to the circuit, the circuit will not malfunction. [0035] Furthermore, since noise does not appear on the terminal U not only in the input terminal 19 but also in various signal paths of the control circuit 13 formed on the shield pattern 101, for example, the protective function Malfunctions such as activation of overcurrent and overvoltage protection can be avoided. Other control circuit 14
The same applies to 18. [0036] Furthermore, when noise is applied not only to the terminal U but also to the terminals V, W, P, and N of the aluminum substrate 31 (that is, the current paths of the power transistors 1 to 6), the same procedure as described above is applied. malfunctions can be avoided. Note that a large capacity capacitor is generally connected between terminals P and N, which are connected to a high voltage power supply, so
N noise will appear in exactly the same way. [0037] In the above embodiment, the shield patterns 101 to 104 are directly fixed to the potential of the output electrodes (emitters) of the corresponding power transistors 1 to 6;
It's not necessarily necessary. For example, as shown in FIG. 5, when a relatively large capacitor 44 is connected between the positive and negative terminals of the power supply VN, if noise appears at the emitter of the power transistor 2 (i.e., terminal N), Correspondingly, the potential on the positive side of the power supply VN also changes. Further, as shown in FIG. 6, in order to apply a reverse bias to the base when the power transistor 2 is off, a reverse bias circuit consisting of a resistor 45 and diodes 46 and 47 is connected to the emitter of the power transistor 2 to level shift the emitter potential. In this case, if noise appears on the emitter of power transistor 2, noise will similarly appear on the negative side of power supply VN. Note that diode 4
6.47 may be a Zener diode. If the shield pattern 104 is fixed at a potential corresponding to the potential of the output electrode (emitter) of the power transistor 2, it can exhibit the above-mentioned effect, so it can be used without being directly connected to the emitter of the power transistor 2. For example, in the case of FIG. 6, it may be connected to the positive side of the power source VN, or to the negative side of the power source VN in the case of FIG. This also applies to the other shield patterns 101 to 103. [0038] In the embodiment of FIG. 2, the arrangement of the shield patterns 101, 104 on the aluminum substrate 31 is as follows:
It is preferably carried out by one of the following methods. In the first method, a copper pattern 33 is first formed on the insulating layer 32. Then, a structure in which the copper pattern 41 and the shield pattern 101 are formed on the front and back surfaces of the insulating layer 105 and a laminate in which the copper pattern 41 and the shield pattern 104 are formed on the front and back surfaces of the insulating layer 106 are constructed on both sides. The laminate is formed from a printed circuit board or the like, and the laminate is placed at a predetermined position on the insulating layer 32. In the second method, a copper pattern 33 and shield patterns 101 and 104 are simultaneously formed on the insulating layer 32. Then, a laminated body in which a copper pattern 41 is formed on the surface of the insulating layers 105 and 106 is formed using a single-sided printed circuit board or the like, and these laminated bodies are arranged on the shield patterns 101 and 104, respectively. [0039] FIG. 7 is a sectional view showing another embodiment of the semiconductor device according to the present invention. Unlike the embodiment of FIG. 2, shield patterns 101 and 104 are disposed on relatively thick insulating layers 109 and 110 formed on insulating layer 32, respectively. Further, the copper patterns 33 for the power transistors 1 and 2 are formed relatively thick. Since a large current flows through the power transistors 1 and 2, the copper pattern 33
The thicker the better. [00401 Insulating layer 109. The stack of the shield pattern 101°, the insulating layer 105, and the copper pattern 41 may be formed from a two-layer printed circuit board or the like, and placed at a predetermined position on the insulating layer 32. According to this embodiment, there is an advantage that the laminate is placed over the copper pattern 33 and the area can be reduced.

[0041] In the above embodiment, electrical connection through through holes 107 and 108 was explained as a means of fixing the potential of shield patterns 101 and 104, but short circuits made of aluminum wire, soldering, or metal pieces were described. They may be connected by parts or the like. in this case,
Connection can be easily made by removing a portion of the insulating layers 105, 106 to expose a portion of the upper surface of the shield patterns 101, 104. [0042] By the way, in the semiconductor device of the embodiment shown in FIG. 2 or FIG. Since they face each other with the insulating layer 32 in between and are capacitively coupled, the following problems may occur. That is, in these semiconductor devices, the power transistor 1 on the upper arm side. 3. The potential of the output electrode (emitter) of No. 5 varies significantly depending on the on/off state of the power transistors on the upper arm side and the lower arm side of each phase. For example, U
In terms of phases, when power transistor 1 is on and power transistor 2 is off, the potential of shield pattern 101 is equal to the potential of terminal P, while when power transistor 1 is off and power transistor 2 is on, shield pattern 101 is equal to the potential of terminal P. The potential of becomes equal to the potential of terminal N. Therefore, power transistors 1, 2
For example, in the case of PWM control, when the carrier frequency of the pulse sent to the base is increased, the potential of the shield pattern 101 changes at high speed, and as a result, leakage current to the aluminum substrate 31 due to the capacitance between the shield pattern 101 and the aluminum substrate 31 increases. occurs. shield pattern 10
1 is relatively large, and therefore the capacitance between the shield pattern 101 and the aluminum substrate 31 is correspondingly large, and there is a possibility that the increased leakage current due to this capacitance may exceed the specifications of the device. Figure 8
The semiconductor device of the embodiment shown in FIG. 9 is intended to reduce such leakage current to the aluminum substrate 31. [0043] Similarly to FIG. 1, the three-phase bridge configuration inverter circuit shown in FIG. 8 has the same circuit configuration as the conventional inverter circuit shown in FIG. The semiconductor device of FIG. 8 also has shield patterns 101, 102, 103, . and a shield pattern 104 kept at the same potential as the common reference potential of the control circuits 14, 16, and 18.
These shield patterns 101 to 104 are formed in the same manner as in FIG. 1, so a detailed description thereof will be omitted here. [0044] In this example, the aluminum substrate 31
an insulating layer 32 formed on the shield pattern 1;
A shield pattern 111 and an insulating layer 112 are interposed between the layers 01 to 104. The shield pattern 111 is formed on the insulating layer 32, and the shield pattern 111 is formed on the insulating layer 32.
An insulating layer 112 is formed on top of 1. The shield pattern 111 connects the power transistors 1 and 2 (or the power transistors 3 and 4) connected to a totem pole.
, power transistors 5, 6), that is, the potential of the power supply terminal N. [0045] The shield pattern 111 is fixed to the potential of the power supply terminal N, for example, as shown in FIG. FIG. 9 is a sectional view showing the structure of the U-phase portion when the circuit of FIG. 8 is formed on a single metal substrate. An insulating layer 32 similar to that in FIG. 2 is formed on the aluminum substrate 31. A copper shield pattern 111 whose entire area overlaps with the insulating layer 32 is formed on the insulating layer 32 . An insulating layer 112 is formed on the shield pattern 111 so as to overlap the entire area of the shield pattern 111. On this insulating layer 112, there is a copper pattern 33 having exactly the same structure as on the insulating layer 32 in the embodiment of FIG.
, shield patterns 101, 104 are formed. These copper patterns 33, shield patterns 101°10
4 is exactly the same as that in FIG. 2, so its explanation will be omitted here. [0046] The insulating layer 112 has the copper pattern 33
A through hole 113 is formed in a portion corresponding to the copper pattern 33c, which is a part of the through hole 11.
The shield pattern 111 is connected to the copper pattern 3 through the copper pattern 3.
Connected to 3c. The copper pattern 33c is a terminal that relays the output electrode (emitter) of the power transistor 2 and the power supply terminal N. That is, the shield pattern 111 is connected to the power supply terminal N via the copper pattern 33c, thereby fixing it to a constant reference potential. [0047] By providing the shield pattern 111 and the insulating layer 112 fixed at a constant reference potential as described above between the shield patterns 101 and 104 and the insulating layer 32, the semiconductor device of this embodiment has the shield pattern 10
1 and the aluminum substrate 31 is a shield pattern 111
, and there is no direct capacitive coupling between them. Therefore, even if the potential of the shield pattern 101 changes at high speed as described above, the leakage current to the aluminum substrate 31 is significantly reduced in the case of the embodiment shown in FIG. [0048] The semiconductor device of the embodiment shown in FIG.
Similar to the semiconductor device, the insulating layer 32 and the shield pattern 1
A shield pattern 111A fixed to a constant reference potential and an insulating layer 112A are provided between 01 and 104. However, the shield pattern 111A and the insulating layer 112A of this embodiment are not formed in locations corresponding to power transistors 1-6. That is, the shield pattern 111A has a structure in which the portions of the power transistors 1 to 6 are not shielded. The semiconductor device shown in FIG. 10 differs from the semiconductor device shown in FIG. 8 only in this point, and the other parts have the same structure. [0049] FIG. 11 is a sectional view showing the structure of the U-phase portion of FIG. 10. A shield pattern 111A is formed on the insulating layer 32 except for the portions corresponding to the power transistors 1 and 2. This shield pattern 11
1A is connected to the power supply terminal N via an external wiring 114 using aluminum wire, soldering, shorting parts, etc., and a copper pattern 33c. Shield pattern 111
An insulating layer 112A is formed on A, and shield patterns 101 and 104 are formed on this insulating layer 112A. The configurations above these shield patterns 101 and 104 are the same as those in the previously described embodiments, so their explanation will be omitted here. [00501 On the other hand, a copper pattern 33 is formed on the insulating layer 32 at a portion corresponding to the power transistor 1.2. This copper pattern 33 is the shield pattern 111A
They may be formed simultaneously or independently. Power transistors 1 and 2 are connected to the copper pattern 33 by soldering or the like. [00511 Note that the shield pattern 111A may be formed by enlarging the copper pattern 33c of the copper pattern 33 that forms the output terminal of the power transistor 4. In this way, the external wiring connecting the shield pattern 111A and the power terminal N is simplified. [0052] According to the semiconductor device of the embodiment shown in FIGS. 10 and 11, leakage current to the aluminum substrate 31 can be reduced for the same reason as the semiconductor device of FIGS. 8 and 9. Moreover, in the case of this embodiment, since the insulating layer directly under the power transistors 1 to 6 is only the insulating layer 32,
Compared to the embodiments of FIGS. 8 and 9, in which the insulating layer 32 and the insulating layer 112 are formed in double layers directly under the power transistors 1 to 6, the thermal resistance of the power transistors 1 to 6 is reduced. be. [0053] In the embodiment shown in FIGS. 8 and 10, the shield pattern 1 formed on the insulating layer 32
Although the leakage current is reduced by connecting the shield pattern 111 or 111A to the power terminal N, the same effect can be obtained by connecting the shield pattern 111 or 111A to the power terminal P. In short, it is sufficient that the shield patterns 111 and IIIA are fixed at a constant reference potential. [0054] Furthermore, in each of the above embodiments, a bipolar transistor is used as the power switching device, but a power MO3FET, an insulated gate bipolar transistor (IGBT), or the like may be used. Further, the transistor is not limited to an NPN transistor, but may be a PNP transistor. [0055] According to claim 1, the first
a first insulating layer; the first through the second shield pattern and the second and third insulating layers, respectively. While forming the second control circuit, the first. The second shield pattern is connected to the first shield pattern. Since the potential of the output electrode of the second power switching element is fixed to the potential corresponding to the potential of the output electrode of the second power switching element, the first
, the direct capacitive coupling between the second control circuit and the metal substrate is eliminated, and the first. the second control circuit and the first control circuit; The capacitance between the second shield pattern and the second shield pattern increases, and the capacitance between the first shield pattern and the metal substrate increases. When noise is applied to the current path of the second power switching element, noise also appears in the control circuit with respect to the metal substrate. As a result, 1. When viewed from the output electrode of the second power switching element, it is equivalent to having no noise in the control circuit, and there is an effect that malfunctions due to noise can be avoided. [0056] According to claim 2, in addition to the effect of claim 1, there is an effect that leakage current generated due to switching of the power switching element can be reduced.

[Brief explanation of the drawing]

FIG. 1 is an example 3 of a semiconductor device according to the present invention.
FIG. 2 is a circuit diagram showing an inverter circuit having a phase bridge configuration.

FIG. 2 is a cross-sectional view showing the structure of a U-phase circuit portion when the circuit of FIG. 1 is formed on a metal substrate.

FIG. 3 is an enlarged cross-sectional view of a portion of FIG. 2 on the upper arm side.

FIG. 4 is an equivalent circuit diagram showing coupling capacitance.

FIG. 5 is a circuit diagram showing a modification of the embodiment of FIG. 1;

FIG. 6 is a circuit diagram showing another modification of the embodiment of FIG. 1;

FIG. 7 is a sectional view showing another semiconductor device according to the present invention.

FIG. 8 is a circuit diagram of another semiconductor device according to the invention.

FIG. 9 is a cross-sectional view showing the structure of a U-phase circuit portion when the circuit of FIG. 8 is formed on a metal substrate.

FIG. 10 is a circuit diagram of another semiconductor device according to the invention.

FIG. 11 is a cross-sectional view showing the structure of a U-phase circuit portion when the circuit of FIG. 10 is formed on a metal substrate.

FIG. 12 is a circuit diagram showing a conventional three-phase bridge configuration inverter circuit.

FIG. 13 is a cross-sectional view showing the structure of a U-phase circuit portion when the circuit of FIG. 12 is formed on a metal substrate.

FIG. 14 is an enlarged cross-sectional view of a portion of FIG. 13 on the upper arm side.

FIG. 15 is an equivalent circuit diagram showing coupling capacitance.

[Explanation of symbols]

1 to 6 Power NPN transistor 13-18 Control circuit 31 Aluminum substrate 32.105,106 Insulating layer 101-104 Shield pattern 107.108 Through hole 111, IIIA Shield pattern

[Figure 1]

[Figure 2]

[Figure 4]

[Figure 5]

[Figure 15]

[Figure 3]

[Figure 6]

[Figure 7]

[Figure 8]

[Figure 9]

[Figure 10]

[Figure 13]

[Figure 11]

[Figure 12]

[Figure 14]

Claims (2)

[Claims] 1. A metal substrate, a first insulating layer formed on the metal substrate, and a first insulating layer formed on the first insulating layer and connected by totem pole. a second power switching element, and a first power switching element comprising a conductor formed on the first insulating layer. a second shield pattern; a second insulating layer formed on the first shield pattern;
a third insulating layer formed on the shield pattern; a first control circuit formed on the second insulating layer for controlling on/off of the first power switching element; A second insulating layer formed on the third insulating layer for controlling on/off of the second power switching element.
a control circuit, and the first shield pattern is connected to the first shield pattern.
a first connecting means for connecting the second shield pattern to a potential corresponding to the potential of the output electrode of the power switching element; and a first connecting means for connecting the second shield pattern to a potential corresponding to the potential of the output electrode of the second power switching element. 2. A semiconductor device comprising: 2 connection means. 2. The semiconductor device according to claim 1, wherein at least the first. A third shield pattern formed on the first insulating layer and fixed to a constant reference potential is provided between the second shield pattern and the first insulating layer; A semiconductor device characterized in that a fourth insulating layer formed between the first or second shield pattern is interposed.