JPH04209522A - Substrate for epitaxial growth and its manufacture - Google Patents
Substrate for epitaxial growth and its manufactureInfo
- Publication number
- JPH04209522A JPH04209522A JP40041690A JP40041690A JPH04209522A JP H04209522 A JPH04209522 A JP H04209522A JP 40041690 A JP40041690 A JP 40041690A JP 40041690 A JP40041690 A JP 40041690A JP H04209522 A JPH04209522 A JP H04209522A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- crystal layer
- epitaxial
- layer
- epitaxial growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000758 substrate Substances 0.000 title claims description 145
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000013078 crystal Substances 0.000 claims description 77
- 239000004065 semiconductor Substances 0.000 claims description 45
- 230000002265 prevention Effects 0.000 claims description 33
- RPPBZEBXAAZZJH-UHFFFAOYSA-N cadmium telluride Chemical compound [Te]=[Cd] RPPBZEBXAAZZJH-UHFFFAOYSA-N 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 23
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 11
- 238000009434 installation Methods 0.000 claims description 5
- SKJCKYVIQGBWTN-UHFFFAOYSA-N (4-hydroxyphenyl) methanesulfonate Chemical compound CS(=O)(=O)OC1=CC=C(O)C=C1 SKJCKYVIQGBWTN-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052714 tellurium Inorganic materials 0.000 claims description 3
- 229910052793 cadmium Inorganic materials 0.000 claims description 2
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 claims description 2
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 claims description 2
- 229910052753 mercury Inorganic materials 0.000 claims description 2
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 claims description 2
- 229910007709 ZnTe Inorganic materials 0.000 description 8
- 239000007789 gas Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000007791 liquid phase Substances 0.000 description 2
- MARUHZGHZWCEQU-UHFFFAOYSA-N 5-phenyl-2h-tetrazole Chemical compound C1=CC=CC=C1C1=NNN=N1 MARUHZGHZWCEQU-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- VQNPSCRXHSIJTH-UHFFFAOYSA-N cadmium(2+);carbanide Chemical compound [CH3-].[CH3-].[Cd+2] VQNPSCRXHSIJTH-UHFFFAOYSA-N 0.000 description 1
- -1 diisopropyl tellurium Chemical compound 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 210000000056 organ Anatomy 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Recrystallisation Techniques (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
［０００１１ [00011
【産業上の利用分野］本発明はへテロエピタキシャル成
長用基板に係り、特に半導体基板上に、該基板と熱膨張
率の異なる異種半導体層を、ペテロ構造にエピタキシャ
ル成長する際にそりが生じないようにしたエピタキシャ
ル成長用基板、およびその製造方法に関する。
［０００２］近年、良質な大面積のエピタキシャル成長
用基板が入手し難いカドミウムテルル（ＣｄＴｅ）のよ
うな半導体結晶を、大面積の基板の入手が容易なガリウ
ム砒素（ＧａＡｓ）の半導体基板上にヘテロエピタキシ
ャル成長によって形成し、実質的に大面積のＣｄＴｅの
エピタキシャル成長用基板を得る方法が注目されている
。然し、一般に半導体基板上に該基板と異種の半導体結
晶をヘテロエピタキシャル成長する際、熱膨張率が異な
るため、エピタキシャル成長温度と、エピタキシャル成
長後、該基板を室温に冷却する際の温度差によって基板
にそりを発生するようになり、このそりが生じると該基
板を用いて半導体素子を製造する際に、その後のマスク
合わせの工程に於いて支障をきたす問題がある。
［０００３］
【従来の技術】上記したヘテロエピタキシャル成長に使
用するエピタキシャル成長用基板は、従来、この基板の
そりを防止するために、例えば（１）充分厚い半導体基
板を用いる。（２）ヤング率が大きく硬度の大きい基板
を用いる。（３）エピタキシャル成長後の基板を半導体
素子に加工し、この素子の使用する温度とエピタキシャ
ル成長温度との温度差を少なくして使用する。（４）基
板のそりが問題とならない程度の微細な寸法にエピタキ
シャル成長後の基板を加工して半導体素子に使用する等
の方法が採られている。
［０００４］[Industrial Application Field] The present invention relates to a substrate for heteroepitaxial growth, and in particular, to prevent warping from occurring when a semiconductor layer of a different type having a coefficient of thermal expansion different from that of the substrate is epitaxially grown into a petrostructure on a semiconductor substrate. The present invention relates to an epitaxial growth substrate and a manufacturing method thereof. [0002] In recent years, semiconductor crystals such as cadmium tellurium (CdTe), for which high-quality large-area substrates for epitaxial growth are difficult to obtain, have been heteroepitaxially grown on gallium arsenide (GaAs) semiconductor substrates, for which large-area substrates are easily available. A method for obtaining a substantially large-area CdTe epitaxial growth substrate is attracting attention. However, when a semiconductor crystal of a different type than the substrate is generally grown heteroepitaxially on a semiconductor substrate, the thermal expansion coefficients are different, so the substrate may warp due to the difference in epitaxial growth temperature and the temperature when cooling the substrate to room temperature after epitaxial growth. When this warpage occurs, there is a problem in that it interferes with the subsequent mask alignment process when semiconductor devices are manufactured using the substrate. [0003] Conventionally, the epitaxial growth substrate used for the above-mentioned heteroepitaxial growth uses, for example (1) a sufficiently thick semiconductor substrate, in order to prevent the substrate from warping. (2) A substrate with a large Young's modulus and high hardness is used. (3) The substrate after epitaxial growth is processed into a semiconductor element, and the temperature difference between the temperature at which this element is used and the epitaxial growth temperature is reduced. (4) A method has been adopted in which a substrate after epitaxial growth is processed to a fine size such that warping of the substrate does not become a problem and then used for a semiconductor device. [0004]
【発明が解決しようとする課題】然し、上記した（１）
の方法では厚い基板は高価であり、素子製造工程に於い
て加工するのが困難である。また基板のそりを充分小さ
く保つには、エピタキシャル結晶層の１００〜５００倍
の厚さが必要となる等問題が多い。また（２）の方法で
は、例えば硬い基板としてはシリコン、或いはサファイ
ア基板があるが、その上にＣｄＴｅの結晶をエピタキシ
ャル成長するとＣｄＴｅ結晶との熱膨張率差が大である
ため、硬度が大である利点も失われる問題がある。
［０００５］また（３）の方法は、エピタキシャル成長
した後、基板を光検知素子に加工する場合が多く、この
光検知素子は一２００℃の低温で使用するので、エピタ
キシャル成長温度と素子に基板を形成した後の使用温度
差を少なくするのは困難である。 また（４）の方法で
は大面積の半導体素子を製造する際に問題となり、実用
的でない等の問題点を生じる。
［０００６１本発明は上記した問題点を解決し、そりの
発生を防止したエピタキシャル成長用基板、およびその
製造方法の提供を目的とする。
［０００７］[Problem to be solved by the invention] However, the above (1)
In this method, a thick substrate is expensive and difficult to process in the device manufacturing process. Further, in order to keep the warpage of the substrate sufficiently small, there are many problems such as the need for a thickness 100 to 500 times that of the epitaxial crystal layer. In addition, in method (2), for example, a silicon or sapphire substrate is used as a hard substrate, but if a CdTe crystal is epitaxially grown on it, the hardness will be large because the difference in thermal expansion coefficient with the CdTe crystal is large. There is a problem that the advantages are also lost. [0005] In addition, in method (3), after epitaxial growth, the substrate is often processed into a photodetector element, and since this photodetector element is used at a low temperature of -200°C, the epitaxial growth temperature and the formation of the substrate on the element are It is difficult to reduce the difference in operating temperature after Furthermore, the method (4) poses problems when manufacturing large-area semiconductor devices, resulting in problems such as being impractical. [00061] An object of the present invention is to solve the above-mentioned problems and provide an epitaxial growth substrate that prevents the occurrence of warpage, and a method for manufacturing the same. [0007]
【課題を解決するための手段】上記目的を達成する本発
明のエピタキシャル成長用基板は、半導体基板の裏面側
、或いは該半導体基板と該基板上に形成予定のエピタキ
シャル結晶層との間に、該基板のそり防止用の半導体結
晶層を設けたことを特徴とする。また半導体基板の表面
に形成するエピタキシャル結晶層の形成材料と同一材料
を用いた半導体結晶層を、前記半導体基板の裏面側に格
子状、或いは網目状に設けたことを特徴とする。
［０００８］更に半導体基板を設置する基板設置台に格
子状の溝を形成し、該基板設置台上にエピタキシャル成
長用基板を設置して反応容器内に収容し、該反応容器内
にエピタキシャル成長用ガスを導入して、該ガスを熱分
解して基板表面にエピタキシャル結晶層を成長すると共
に、該基板の裏面側に格子状、或いは網目状に半導体結
晶を形成することを特徴とする。
［０００９］また熱膨張率がα３の半導体基板上に熱膨
張率がα。のエピタキシャル結晶層を成長する場合、α
。くα５の時、αＢ〉α５成る熱膨張率αＢを有する半
導体結晶層を、α８〉α５の時、αＢくα３成る半導体
結晶層を、前記半導体基板とエピタキシャル結晶層の間
にそり防止層として形成することを特徴とする。また格
子定数がａ５ の半導体基板上に格子定数がａ。のエピ
タキシャル結晶層を成長する場合、格ギ定数ａｍがａｅ
＞ａＢ ＞ ａｓ 、或いはａ。＜ａｓ ＜ａｓの関係
を有する半導体結晶層を、前記半導体基板とエピタキシ
ャル結晶層の間にそり防止層として形成することを特徴
とする。
［００１０１また半導体基板にガリウム砒素、エピタキ
シャル結晶にカドミウムテルル、或いは水銀・カドミウ
ム・テルルを用い、該半導体基板とエピタキシャル結晶
層の間にテルル化亜鉛の結晶層を所定の厚さにそり防止
層として形成したことを特徴とするものである。
［００１１］[Means for Solving the Problems] The epitaxial growth substrate of the present invention which achieves the above object is provided with a substrate for epitaxial growth on the back side of a semiconductor substrate or between the semiconductor substrate and an epitaxial crystal layer to be formed on the substrate. It is characterized by providing a semiconductor crystal layer for preventing warpage. The present invention is also characterized in that a semiconductor crystal layer made of the same material as the epitaxial crystal layer formed on the front surface of the semiconductor substrate is provided in a lattice or mesh pattern on the back surface of the semiconductor substrate. [0008] Further, a lattice-shaped groove is formed in a substrate setting table on which a semiconductor substrate is placed, a substrate for epitaxial growth is placed on the substrate setting table and housed in a reaction vessel, and a gas for epitaxial growth is supplied into the reaction vessel. The method is characterized in that an epitaxial crystal layer is grown on the surface of the substrate by thermally decomposing the gas, and a semiconductor crystal is formed in a lattice or mesh shape on the back surface of the substrate. [0009] Further, a semiconductor substrate having a thermal expansion coefficient of α3 is placed on a semiconductor substrate having a thermal expansion coefficient of α3. When growing an epitaxial crystal layer of α
. When α5, a semiconductor crystal layer having a thermal expansion coefficient αB such that αB>α5 is formed, and when α8>α5, a semiconductor crystal layer having a coefficient of thermal expansion αB α3 is formed as a warpage prevention layer between the semiconductor substrate and the epitaxial crystal layer. It is characterized by Further, a semiconductor substrate with a lattice constant of a5 has a lattice constant of a. When growing an epitaxial crystal layer of
>aB>as, or a. A semiconductor crystal layer having a relationship of <as <as is formed as a warpage prevention layer between the semiconductor substrate and the epitaxial crystal layer. [00101 In addition, gallium arsenide is used for the semiconductor substrate, cadmium telluride is used for the epitaxial crystal, or mercury/cadmium/tellurium is used for the epitaxial crystal, and a crystal layer of zinc telluride is placed between the semiconductor substrate and the epitaxial crystal layer to a predetermined thickness as a warpage prevention layer. It is characterized by the fact that it has been formed. [0011]
【作用】図１および図２に示すように、エピタキシャル
結晶層２を形成する基板１の裏面側に、該エピタキシャ
ル結晶層２の形成材料と同一材料を用いて格子状、或い
は網目状に基板の半導体結晶層より成るそり防止層３を
形成する。この場合、格子、或いは網目の間隔を充分狭
くし、またその厚さを基板１上に形成するエピタキシャ
ル結晶層２の厚さと路間−の厚さ、或いは該エピタキシ
ャル結晶層２よりやや厚くすることで、基板１の表面と
裏面に同様のストレスが掛かるので基板１に発生するそ
りの量が低減される。このように基板１の裏面側に格子
状、或いは網目状のそり防止層３を形成すると赤外光の
入射角を制限するアバ−チアとしても利用できる。
［００１２］また図５に示すように、熱膨張率α３の基
板１上に熱膨張率α。のエピタキシャル結晶層２を形成
する際に、αｅ〈α、の時、α８〉α、で、α８〉α５
の時、αＢ〈α５の熱膨張率α８を有する半導体結晶を
そり防止層３として設ける。このような場合、例えばエ
ピタキシャル成長後、基板１を冷却する際に基板１とそ
り防止層３の間には、基板１がそり防止層３に向かって
凹、或いは凸と成るような応力が掛かり、また基板１と
エピタキシャル結晶層２との間にはエピタキシャル結晶
層２に向かって基板１が凸、或いは凹になるような応力
が働く。そこでそり防止層の厚さを適当な値に設定する
ことで基板のそりを殆ど防止することができる。
［００１３］また図５に示すように基板１、そり防止層
３、エピタキシャル結晶層２の各々の格子定数をａ３、
ａｎ、ａｓとし、ａｓ ＜ａｍ ＜ａｅ の関係を有す
るように、或いはａｔ ＞ａａ ＞ａｅ の関係を有す
るようにすると、上記そり防止層３は基板１とエピタキ
シャル結晶層２との格子不整を緩和する格子不整緩和層
としても働く。
［００１４１図６に基板にＧａＡｓ、そり防止層にテル
ル化亜鉛（’２ｎＴｅ） 、エピタキシャル結晶層にＣ
ｄＴｅを形成し、基板の温度をエピタキシャル成長温度
より室温迄低下させて温度差を３００℃にした場合の基
板のそりの曲率半径Ｒの逆数と、ＣｄＴｅのエピタキシ
ャル結晶層の厚さと２ｎＴｅのそり防止層の厚さとの関
係を示す。 図で縦軸は曲率半径（Ｒ）の逆数を示し、
該左側の縦軸は基板がエピタキシャル結晶層の方向に向
かって凸の場合を示し、右側の縦軸は基板がエピタキシ
ャル結晶層の方向に向かって凹の場合を示す。また横軸
はＺｎＴｅの厚さ（μｍ）を示す。
［００１５］ 図で例えばＧａＡｓ基板上にＣｄＴｅ
のエピタキシャル結晶層を４μｍの厚さに形成する場合
、そり防止層のＺｎＴｅ層の厚さを２．５μｍとすると
、基板のそり１／Ｒが零に成るのが判る。また上記Ｇａ
Ａｓの格子定数は５．６５Ａ、 １ｎＴｅの格子定数は
６．Ｌ Ａ、 ＣｄＴｅの格子定数は６．４８人である
ので２ｎＴｅのそり防止層は、格子不整緩和層として機
能する。
［００１６］また図３（ａ）および図３（ｂ）に示すよ
うに上記基板上にエピタキシャル結晶を形成する際に、
該基板を載置する基板設置台４に格子状の溝５を付けて
基板上にエピタキシャル結晶を成長すると、基板の裏面
側にエピタキシャル結晶と路間−厚さの半導体結晶のそ
り防止層が形成できる。
［００１７］[Operation] As shown in FIGS. 1 and 2, the same material as that for forming the epitaxial crystal layer 2 is used on the back side of the substrate 1 on which the epitaxial crystal layer 2 is formed in a lattice or mesh pattern. A warpage prevention layer 3 made of a semiconductor crystal layer is formed. In this case, the interval between the lattices or meshes should be made sufficiently narrow, and the thickness should be the same as the thickness of the epitaxial crystal layer 2 formed on the substrate 1 and the thickness between the lines, or slightly thicker than the epitaxial crystal layer 2. Since the same stress is applied to the front and back surfaces of the substrate 1, the amount of warping that occurs on the substrate 1 is reduced. If the warp prevention layer 3 in a grid or mesh shape is formed on the back side of the substrate 1 in this manner, it can also be used as an avertia for limiting the incident angle of infrared light. [0012] Furthermore, as shown in FIG. 5, a substrate 1 having a coefficient of thermal expansion α of α3 is formed on the substrate 1 having a coefficient of thermal expansion α of α3. When forming the epitaxial crystal layer 2 of , when αe〈α, α8〉α, and α8〉α5
In this case, a semiconductor crystal having a thermal expansion coefficient α8 of αB<α5 is provided as the warpage prevention layer 3. In such a case, for example, when cooling the substrate 1 after epitaxial growth, stress is applied between the substrate 1 and the anti-warpage layer 3 so that the substrate 1 becomes concave or convex toward the anti-warpage layer 3. Further, stress acts between the substrate 1 and the epitaxial crystal layer 2 so that the substrate 1 becomes convex or concave toward the epitaxial crystal layer 2. Therefore, by setting the thickness of the warpage prevention layer to an appropriate value, warping of the substrate can be almost prevented. [0013] Also, as shown in FIG. 5, the lattice constants of the substrate 1, warpage prevention layer 3, and epitaxial crystal layer 2 are a3,
an, as, and the relationship as <am <ae or at >aa >ae, the warpage prevention layer 3 alleviates the lattice misalignment between the substrate 1 and the epitaxial crystal layer 2. It also acts as a lattice misalignment relaxation layer. [00141 In Figure 6, the substrate is GaAs, the warpage prevention layer is zinc telluride ('2nTe), and the epitaxial crystal layer is C.
The reciprocal of the radius of curvature R of the substrate warp when dTe is formed and the temperature of the substrate is lowered to room temperature from the epitaxial growth temperature to a temperature difference of 300°C, the thickness of the CdTe epitaxial crystal layer, and the 2nTe warp prevention layer. The relationship between the thickness of In the figure, the vertical axis indicates the reciprocal of the radius of curvature (R),
The left vertical axis indicates the case where the substrate is convex toward the epitaxial crystal layer, and the right vertical axis indicates the case where the substrate is concave toward the epitaxial crystal layer. Further, the horizontal axis indicates the thickness (μm) of ZnTe. [0015] In the figure, for example, CdTe is deposited on a GaAs substrate.
It can be seen that when the epitaxial crystal layer is formed to have a thickness of 4 μm, and the thickness of the ZnTe layer of the anti-warpage layer is 2.5 μm, the warp 1/R of the substrate becomes zero. In addition, the above Ga
The lattice constant of As is 5.65A, and the lattice constant of 1nTe is 6. Since the lattice constant of LA, CdTe is 6.48, the 2nTe warpage prevention layer functions as a lattice misalignment alleviation layer. [0016] Also, when forming an epitaxial crystal on the substrate as shown in FIGS. 3(a) and 3(b),
When epitaxial crystals are grown on the substrate by forming lattice-shaped grooves 5 on the substrate mounting table 4 on which the substrate is placed, a warpage prevention layer of semiconductor crystal with a thickness equal to that between the epitaxial crystal and the groove is formed on the back side of the substrate. can. [0017]
【実施例】以下、図面を用いて本発明の実施例につき詳
細に説明する。図１は本発明のエピタキシャル成長用基
板の第１実施例の斜視図で、図２は前記第１実施例の断
面図である。図１、および図２に示すにＧａＡｓの基板
１の裏面には、該基板の表面に形成するＣｄＴｅのエピ
タキシャル結晶層２と路間−厚さのＣｄＴｅ結晶層より
成るそり防止層３が格子状、或いは網目状に形成されて
いる。このそり防止層３によって基板１上にエピタキシ
ャル結晶層２を形成した後、室温に冷却した場合に基板
に働く応力と反対側の応力が該基板に働いて基板にそり
を生じなくなる。
［００１８］このようなエピタキシャル成長用基板を形
成する場合、図３（ａ）および図３（ａ）のＡ−Ａ−線
断面図の図３（ｂ）に示すように、カーボンよりなる基
板設置台４に格子状の溝５を例えば５ｍｍのピッチにて
形成する。そして図４に示すような気相成長装置の反応
管６内に前記した基板設置台４を挿入し、その上にＧａ
Ａｓのエピタキシャル成長用の基板１を載置する。そし
て反応管６内に水素ガスに担持されたジメチルカドミウ
ムガス、およびジイソプロピルテルルガスの原料ガスを
矢印Ａのように導入し、該基板設置台４を矢印Ｂのよう
に回転し、反応管の周囲に設けた高周波誘導加熱用のコ
イル７にて約３８０℃の温度に加熱することで、基ｖｊ
、１の表面上にエピタキシャル結晶＠２を成長すると共
に、該基板の裏面側にもエピタキシャル結晶と路間−厚
さの半導体結晶のそり防止層３を形成することができる
。このようにすると基板に掛かる応力が互いに相殺され
てそりが基板に発生しなくなる。
［００１９１図５は本発明のエピタキシャル成長基板の
第２実施例で、図６は基板上に形成するエピタキシャル
結晶層の厚さと、そり防止層の厚さとの関係図である。
図５、および図６に示すように、厚さが４５０７ｚｍの
ＧａＡｓの基板１上に、厚さ５μｍのＣｄＴｅのエピタ
キシャル結晶層２を形成する場合には、ＧａＡｓ基板１
上にＺｎＴｅのそり防止層３を厚さ３．１μｍで形成し
、エピタキシャル成長温度と室温との温度差を３００℃
に保つと基板にそりを発生しないことが判る。
［００２０１ここでＧａＡｓ基板の熱膨張率ａｓ ””
５．６ Ｘｌ０６／℃、その上に形成するＣｄＴｅのエ
ピタキシャル結晶の熱膨張率α、 ＝４．７ ｘｌＯ−
’／ ℃であり、該基板とエピタキシャル結晶の間に形
成するＺｎＴｅのそり防止層の熱膨張率αＢ ＝８．９
Ｘｌ０−’／ ℃で、前記した熱膨張率α３の基板上
に熱膨張率αｅのエピタキシャル結晶を形成する際に、
α６くα、の時、α８〉α、の熱膨張率力を有する半導
体結晶をそり防止層として設けると基板に掛かる応力が
互いに相殺されて基板にそりを生じることが無くなる。
［００２１１このようなエピタキシャル成長用基板を製
造する場合、図７に示すようにＺｎＴｅのソース坩堝９
と、ＣｄＴｅのソース坩堝１１とを有する反応容器８内
の基板設置台４上にＧａＡｓの基板１を設置し、該反応
容器内を１Ｏ−７ｔ。
ｒｒの高真空に排気した後、基板１の温度を３８０℃に
保ち、ＣｄＴｅのソース坩堝１１の温度を５２０℃、２
ｎＴｅのソース坩堝９の温度を５７０℃に保ってＧａＡ
ｓの基板１を１ｎＴｅのソース坩堝９上に所定時間設置
し、更に該基板をＣｄＴｅのソース坩堝１１上に所定時
間保つことで基板上に２ｎＴｅ層をそり防止層とて設け
、その上にＣｄＴｅのエピタキシャル結晶を形成し、か
つ基板にそりを発生しなくなる。
［００２２］また上記ＧａＡｓの格子定数は５．６５人
、１ｎＴｅの格子定数は６．１人、ＣｄＴｅの格子定数
は６，４８八であるのでＺｎＴｅのそり防止層は、格子
不整緩和層として機能する。
また本実施例ではＣｄＴｅのエピタキシャル結晶層を１
層形成したが、更にこのＣｄＴｅのエピタキシャル結晶
層の上に液相エピタキシャル成長方法を用いてＨｇ１−
ｘ Ｃｄｘ Ｔｅ結晶を液相エピタキシャル成長し、エ
ピタキシャル結晶層を２層構造に形成することもできる
。この場合はＨｇ１−ＣｄＫ 丁ｅ結晶層とＣｄＴｅ結
晶層の厚さを考慮してＺｎＴｅの結晶層の厚さを決定す
ると良い。
［００２３］また上記したＧａＡｓ基板の上にそり防止
層のＺｎＴｅ層、 ＣｄＴｅのエピタキシャル結晶層を
分子線エピタキシャル成長方法、或いは有機金属気相成
長方法（Ｎ、Ｉ○ＣＶＤ方法：Ｍｅｌａｌ Ｏｒｇａｎ
ｉｃ Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔ
ｉｏｎ方法）を用いて形成することも無論可能である。
［００２４］Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings. FIG. 1 is a perspective view of a first embodiment of the epitaxial growth substrate of the present invention, and FIG. 2 is a sectional view of the first embodiment. As shown in FIGS. 1 and 2, on the back surface of a GaAs substrate 1, there is a CdTe epitaxial crystal layer 2 formed on the surface of the substrate and a warpage prevention layer 3 made of a CdTe crystal layer with a thickness equal to that of a lattice. , or formed in a mesh shape. After the epitaxial crystal layer 2 is formed on the substrate 1 by means of the warpage prevention layer 3, when the substrate is cooled to room temperature, a stress opposite to the stress acting on the substrate acts on the substrate, so that no warpage occurs in the substrate. [0018] When forming such a substrate for epitaxial growth, as shown in FIG. 3(a) and FIG. 3(b), which is a cross-sectional view taken along the line A-A in FIG. 4 are formed with grid-like grooves 5 at a pitch of, for example, 5 mm. Then, the substrate mounting table 4 described above is inserted into the reaction tube 6 of the vapor phase growth apparatus as shown in FIG.
A substrate 1 for epitaxial growth of As is placed. Then, raw material gases such as dimethyl cadmium gas supported by hydrogen gas and diisopropyl tellurium gas are introduced into the reaction tube 6 as shown by arrow A, and the substrate mounting table 4 is rotated as shown by arrow B, and the surroundings of the reaction tube are By heating the base vj to a temperature of about 380°C with the high frequency induction heating coil 7 installed
, 1 can be grown on the surface of the substrate 1, and at the same time, an anti-warpage layer 3 of semiconductor crystal can be formed on the back side of the substrate with a thickness equal to that between the epitaxial crystal and the substrate. In this way, the stresses applied to the substrate cancel each other out, and warpage does not occur on the substrate. [00191 FIG. 5 shows a second embodiment of the epitaxial growth substrate of the present invention, and FIG. 6 is a diagram showing the relationship between the thickness of the epitaxial crystal layer formed on the substrate and the thickness of the warpage prevention layer. As shown in FIGS. 5 and 6, when forming a CdTe epitaxial crystal layer 2 with a thickness of 5 μm on a GaAs substrate 1 with a thickness of 4507 zm, the GaAs substrate 1
A ZnTe warpage prevention layer 3 is formed on top with a thickness of 3.1 μm, and the temperature difference between the epitaxial growth temperature and room temperature is set to 300°C.
It can be seen that warping does not occur on the board if it is kept at a constant temperature. [00201 Here, the thermal expansion coefficient of GaAs substrate as ””
5.6 Xl06/°C, coefficient of thermal expansion α of CdTe epitaxial crystal formed thereon, =4.7 xlO-
' / ℃, and the coefficient of thermal expansion αB of the ZnTe warpage prevention layer formed between the substrate and the epitaxial crystal is 8.9.
When forming an epitaxial crystal with a coefficient of thermal expansion αe on a substrate with a coefficient of thermal expansion α3 described above at
If a semiconductor crystal having a coefficient of thermal expansion of α8>α, where α6×α, is provided as a warpage prevention layer, the stresses applied to the substrate will cancel each other out, and no warpage will occur in the substrate. [00211 When manufacturing such a substrate for epitaxial growth, a ZnTe source crucible 9 is used as shown in FIG.
A GaAs substrate 1 was placed on a substrate installation stand 4 in a reaction vessel 8 having a CdTe source crucible 11 and a CdTe source crucible 11, and the inside of the reaction vessel was heated at 10-7t. After evacuation to a high vacuum of
The temperature of the nTe source crucible 9 was kept at 570°C and the GaA
s substrate 1 is placed on a 1nTe source crucible 9 for a predetermined period of time, and the substrate is further kept on a CdTe source crucible 11 for a predetermined period of time to provide a 2nTe layer on the substrate as a warpage prevention layer. epitaxial crystals are formed, and warpage does not occur on the substrate. [0022] Also, since the lattice constant of GaAs is 5.65, the lattice constant of 1nTe is 6.1, and the lattice constant of CdTe is 6,488, the ZnTe warpage prevention layer functions as a lattice misalignment mitigation layer. do. In addition, in this example, the epitaxial crystal layer of CdTe is
A layer of Hg1− was formed using a liquid phase epitaxial growth method on this CdTe epitaxial crystal layer.
It is also possible to grow the x Cdx Te crystal by liquid phase epitaxial growth and form the epitaxial crystal layer into a two-layer structure. In this case, it is preferable to determine the thickness of the ZnTe crystal layer by considering the thicknesses of the Hg1-CdK crystal layer and the CdTe crystal layer. [0023] Furthermore, a ZnTe layer as a warpage prevention layer and a CdTe epitaxial crystal layer are formed on the GaAs substrate by molecular beam epitaxial growth method or metal organic chemical vapor deposition method (N, I○ CVD method: Melal Organ).
ic Chemical Vapor Deposit
Of course, it is also possible to form using the ion method). [0024]
【発明の効果】以上述べたように、本発明によればエピ
タキシャルの構造によってそりを低減しているため、厚
い基板や、硬い基板を使用する必要も無く、また平坦な
大面積のへテロエピタキシャル成長用基板が得られる効
果がある。また第１の実施例の方法によれば、エピタキ
シャル結晶の成長とともに基板の裏面側にもそり防止層
が同時に形成されるので特別にそり防止層の形成工程を
設ける必要がなくなり、簡単な工程でそり防止層が形成
できる効果がある。
［００２５］また第２の実施例の方法によれば、そり防
止層の厚みを制御することで基板のそり量、およびそり
の方向が制御でき、かつそり防止層が格子不整を緩和す
る働きも同時にすることができるので、素子形成に対し
て高品質なエピタキシャル結晶が得られる効果がある。[Effects of the Invention] As described above, according to the present invention, since warpage is reduced by the epitaxial structure, there is no need to use a thick or hard substrate, and flat large-area heteroepitaxial growth is possible. This has the effect that a substrate for use can be obtained. Furthermore, according to the method of the first embodiment, since the warpage prevention layer is simultaneously formed on the back side of the substrate as the epitaxial crystal grows, there is no need to provide a special process for forming the warpage prevention layer, and the process is simple. This has the effect of forming a warpage prevention layer. [0025] Furthermore, according to the method of the second embodiment, by controlling the thickness of the warpage prevention layer, the amount of warpage of the substrate and the direction of warpage can be controlled, and the warpage prevention layer also functions to alleviate lattice misalignment. Since these steps can be performed simultaneously, there is an effect that high-quality epitaxial crystals can be obtained for device formation.
【図１】本発明のエピタキシャル成長用基板の第１実施
例を示す斜視図である。FIG. 1 is a perspective view showing a first embodiment of an epitaxial growth substrate of the present invention.
【図２】本発明のエピタキシャル成長用基板の第１実施
例を示す断面図である。FIG. 2 is a cross-sectional view showing a first embodiment of the epitaxial growth substrate of the present invention.
【図３】本発明の基板設置台の平面図および断面図で（
ａ）は平面図、（ｂ ）は（ａ）のＡ−Ａ−線断面図で
ある。FIG. 3 is a plan view and a sectional view of the board installation stand of the present invention (
(a) is a plan view, and (b) is a sectional view taken along the line AA in (a).
【図４】第１実施例のエピタキシャル成長用基板の製造
方法の説明図である。FIG. 4 is an explanatory diagram of a method for manufacturing an epitaxial growth substrate according to the first embodiment.
【図５】本発明のエピタキシャル成長用基板の第２実施
例を示す断面図である。FIG. 5 is a cross-sectional view showing a second embodiment of the epitaxial growth substrate of the present invention.
【図６】エピタキシャル結晶層の厚さとそり防止層の厚
さの関係を示す図である。FIG. 6 is a diagram showing the relationship between the thickness of an epitaxial crystal layer and the thickness of an anti-warpage layer.
【図７】第２実施例のエピタキシャル成長用基板の製造
方法の説明図である。FIG. 7 is an explanatory diagram of a method for manufacturing an epitaxial growth substrate according to a second embodiment.
１ 基板 ２ エピタキシャル結晶層 ３ そり防止層 ４ 基板設置台 ５溝 ６ 反応管 ７ コイル ８ 反応容器 ９ ２ｎＴｅのソース坩堝 １１ ＣｄＴｅのソース坩堝 1 Board 2 Epitaxial crystal layer 3. Warpage prevention layer 4 Board installation stand 5 grooves 6 Reaction tube 7 Coil 8 Reaction container 9 2nTe source crucible 11 CdTe source crucible
【図１】[Figure 1]
【図６】[Figure 6]
Claims (6)
（１）と、該基板（１）上に形成予定のエピタキシャル
結晶層（２）との間に、該基板（１）のそりを防止する
そり防止層（３）を設けたことを特徴とするエピタキシ
ャル成長用基板。1. A method for preventing warpage of the substrate (1) on the back side of the semiconductor substrate (1) or between the substrate (1) and an epitaxial crystal layer (2) to be formed on the substrate (1). A substrate for epitaxial growth, characterized in that it is provided with an anti-warpage layer (3) for preventing warpage.
キシャル結晶層（２）の形成材料と同一材料を用いたそ
り防止層（３）を前記基板（１）の裏面側に格子状、或
いは網目状に設けたことを特徴とする請求項１記載のエ
ピタキシャル成長用基板。2. A warpage prevention layer (3) made of the same material as the epitaxial crystal layer (2) formed on the surface of the semiconductor substrate (1) is provided on the back side of the substrate (1) in a lattice pattern or 2. The epitaxial growth substrate according to claim 1, wherein the epitaxial growth substrate is provided in a mesh shape.
４）に格子状の溝を形成し、該基板設置台（４）上にエ
ピタキシャル成長用の基板を設置して反応管（６）内に
収容し、該反応管（６）にエピタキシャル成長用ガスを
導入して、該ガスを熱分解して前記基板（１）の表面に
エピタキシャル結晶層（２）を成長すると共に、該基板
（１）の裏面側に格子状、或いは網目状にそり防止層（
３）を形成することを特徴とする請求項１、或いは請求
項２に記載のエピタキシャル成長用基板の製造方法。Claim 3: A substrate installation stand on which the semiconductor substrate (1) is installed (
A lattice-shaped groove is formed in 4), a substrate for epitaxial growth is placed on the substrate installation table (4), and the substrate is housed in a reaction tube (6), and a gas for epitaxial growth is introduced into the reaction tube (6). Then, the gas is thermally decomposed to grow an epitaxial crystal layer (2) on the surface of the substrate (1), and a warpage prevention layer (2) is formed on the back side of the substrate (1) in a lattice or mesh pattern.
3). The method for manufacturing an epitaxial growth substrate according to claim 1 or 2, characterized in that: 3) is formed.
熱膨張率がα＿ｅのエピタキシャル結晶層（２）を成長
する場合において、α＿ｅ＜α＿ｓの時、α＿Ｂ＞α＿
ｓ成る熱膨張率α＿Ｂを有する半導体結晶層をそり防止
層（３）として、α＿ｅ＞α＿ｓの時、α＿Ｂ＜α＿ｓ
成る半導体結晶層をそり防止層（３）として、前記半導
体基板（１）とエピタキシャル結晶層（２）の間に形成
することを特徴とする請求項１記載のエピタキシャル成
長用基板の製造方法。4. When growing an epitaxial crystal layer (2) with a coefficient of thermal expansion α_e on a semiconductor substrate (1) with a coefficient of thermal expansion α_s, when α_e<α_s, α_B>α_
When α_e>α_s, α_B<α_s
2. The method of manufacturing a substrate for epitaxial growth according to claim 1, wherein the semiconductor crystal layer consisting of the above is formed as a warpage prevention layer (3) between the semiconductor substrate (1) and the epitaxial crystal layer (2).
半導体基板（１）上に格子定数がａ＿ｅのエピタキシャ
ル結晶層（２）を成長する場合において、格子定数ａ＿
Ｂがａ＿ｅ＞ａ＿Ｂ＞ａ＿ｓ、或いはａ＿ｅ＜ａ＿Ｂ＜
ａ＿ｓの関係を有する半導体結晶層をそり防止層（３）
として前記半導体基板（１）とエピタキシヤル結晶層（
２）の間に形成したことを特徴とする請求項４記載のエ
ピタキシャル成長用基板の製造方法。5. In the case where an epitaxial crystal layer (2) with a lattice constant a_e is grown on a semiconductor substrate (1) with a lattice constant a_s, the lattice constant a_
B is a_e>a_B>a_s, or a_e<a_B<
A semiconductor crystal layer having a relationship of a_s is used as a warpage prevention layer (3)
The semiconductor substrate (1) and the epitaxial crystal layer (
5. The method of manufacturing an epitaxial growth substrate according to claim 4, wherein the substrate is formed during step 2).
リウム砒素、エピタキシャル結晶層（２）にカドミウム
テルル、或いは水銀・カドミウム・テルルを用い、該半
導体基板（１）とエピタキシャル結晶層（２）の間にテ
ルル化亜鉛の結晶層をそり防止層（３）として所定の厚
さに形成したことを特徴とするエピタキシャル成長用基
板の製造方法。6. In claim 5, the semiconductor substrate (1) is made of gallium arsenide, the epitaxial crystal layer (2) is made of cadmium tellurium, or mercury/cadmium/tellurium, and the semiconductor substrate (1) and the epitaxial crystal layer (2) are made of cadmium tellurium. A method for manufacturing a substrate for epitaxial growth, characterized in that during step (2), a crystalline layer of zinc telluride is formed to a predetermined thickness as a warpage prevention layer (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40041690A JPH04209522A (en) | 1990-12-05 | 1990-12-05 | Substrate for epitaxial growth and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40041690A JPH04209522A (en) | 1990-12-05 | 1990-12-05 | Substrate for epitaxial growth and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04209522A true JPH04209522A (en) | 1992-07-30 |
Family
ID=18510329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP40041690A Withdrawn JPH04209522A (en) | 1990-12-05 | 1990-12-05 | Substrate for epitaxial growth and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04209522A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5952679A (en) * | 1996-10-17 | 1999-09-14 | Denso Corporation | Semiconductor substrate and method for straightening warp of semiconductor substrate |
| DE19848298A1 (en) * | 1998-10-12 | 2000-04-13 | Inst Halbleiterphysik Gmbh | Large diameter, high temperature stable, single crystal semiconductor substrate wafer, for IC production, has an anti-stress layer outside the active region to counteract gravity-induced forces |
-
1990
- 1990-12-05 JP JP40041690A patent/JPH04209522A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5952679A (en) * | 1996-10-17 | 1999-09-14 | Denso Corporation | Semiconductor substrate and method for straightening warp of semiconductor substrate |
| DE19848298A1 (en) * | 1998-10-12 | 2000-04-13 | Inst Halbleiterphysik Gmbh | Large diameter, high temperature stable, single crystal semiconductor substrate wafer, for IC production, has an anti-stress layer outside the active region to counteract gravity-induced forces |
| DE19848298B4 (en) * | 1998-10-12 | 2008-08-07 | IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik | High temperature stable large diameter semiconductor substrate wafer and method of making same |
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