JPH04207734A - Cell transmitting/receiving equipment - Google Patents

Abstract

PURPOSE:To gradually decrease the delay time required for encoding and decoding by detecting a cell rejection by comparing receiving cell discriminating information and transmitting cell discriminating information, specifying a position in which a cell is rejected, based on a cell rejection detecting cell and an inspection bit cell, and compensating the rejection. CONSTITUTION:In a transmitting side equipment, transmitting cell discriminating information (CRPs) is generated from (N-q) pieces of data cells, and inserted into (q) pieces of cell rejection detection cells (CLD). In the case information recorded extending from an s1-th bit to an s2-th bit of the data cell of the CRPs is not contained, saving information of each data cell is also inserted into the CLD cell. In a receiving side equipment, in the case the CLD cell is received, the added sequence number is inspected, continuity to the sequence number of the CLD cell received immediately before is confirmed and a rejection of the CLD cell is detected, and in the case it is rejected, the processing is suspended until a CLD cell compensation/inspection bit cell is received, and after the CLD cell compensation/inspection bit cell is received, decoding of an (M, p) code is executed, and the CLD cell. is restored.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a cell transmitting/receiving device for communication in units of cells or packets. In particular, the present invention relates to a cell transmitting/receiving device having cell discard detection and cell discard compensation functions.

[Conventional technology]

FIG. 23 is a block diagram of a conventional cell transmitting/receiving device.

Conventionally, in order to compensate for cell discard, cell transmitting and receiving equipment
As shown in FIG. 23, the discard compensation encoding circuit 21 on the transmitting side
A method has been used in which cell discard is detected and compensated for by adding a sequence number to the cell at 3A and checking the continuity of the sequence number of the received cell at the discard compensation decoding circuit 223A on the receiving side. This method enables cell discard compensation on a channel-by-channel basis.

[Problem to be solved by the invention]

However, in a cell transmitting/receiving device with such a configuration, a discard compensation encoding circuit for encoding and a discard compensation decoding circuit for decoding are required for each channel, which increases the device scale. Since this is performed at a low transmission rate, there is a drawback that the delay time associated with encoding and decoding becomes large.

The present invention solves the above-mentioned drawbacks. It is possible to perform cell discard compensation even if consecutive sequence numbers are not added to cells to be processed, and the delay time required for encoding and decoding is It is an object of the present invention to provide a cell transmitting/receiving device that can be used for cell transmission/reception.

[Means to solve the problem]

The present invention includes a transmitting device and a receiving device, and the transmitting device includes a plurality of transmitting terminals and a multiplex conversion device that multiplexes and transmits cells or packets from the transmitting terminals. , the receiving side device is a cell transmitting/receiving device including a demultiplexing/converting device that separates the output signal of the multiplexing/converting device, and a plurality of receiving side terminals each receiving the output signal of the demultiplexing/converting device. The side device includes a discard compensation encoding means that performs processing for cell discard detection and cell discard compensation on the output signal of the multiplex converter, encodes it, and transmits it to the receiving side, and the receiving side device includes a discard compensation encoding means for processing the output signal of the multiplex converter and transmitting the encoded signal to the receiving side. The present invention is characterized in that it includes a discard compensation encoding means that performs cell discard detection and cell discard compensation on a signal obtained by receiving and decoding an output signal at a stage before the demultiplexing device, and supplies the signal to the demultiplexing and converting device.

Further, in the present invention, the discard compensation encoding means outputs the output of the multiplex conversion device (an integer q of 2 or more and N−1 or more)
) transmitting cell identification information extracting means for extracting transmitting cell identification information from the transmitting cell identifying information extracting means, and cell discarding for generating q cell discard detection cells to which sequence numbers are added based on the output information of the transmitting cell identifying information extracting means. detection cell generation means;
The output signal of this cell discard detection cell generation circuit is
A cell discard detection cell addition means that is added to N-Q) data cells and output as a small block, and a set of (integer p that is an integer greater than or equal to M1 that is an integer greater than or equal to 2) outputted by the data cell discard detection cell addition means. is input, and for (N-q) sets of data cells and q sets of cell discard detection cells consisting of (M-T),
p) Perform systematic encoding of information bits (M-p) bits and check bits p bits for part or all of the information of a set of integers of 1 or more consisting of bits, and check bits generated by this systematic encoding. The cells are inserted into N sets of p cells to generate N sets of p test bit cells per set, and the 52nd bit from the Sl bit of this test bit cell is
The test bit cell adding means inserts a sequence number into the bit, adds the test bit cell to (M-p) sets of small blocks, and transmits the test bit cells as a large block.

In addition, the above-mentioned discard compensation decoding means detects the discard of the cell discard detection cell based on the sequence number added to the received cell discard detection cell, and performs a cell compensation check on the received cell discard detection cell. Cell discard detection cell restoring means for restoring a cell discard detected cell based on the bit; receiving cell identification information generating means for generating receiving cell identification information for each of the (M-p) received small blocks; Included in the q cell discard detection cells of each received small block (N-q
) data cell discard detection means for detecting data cell discard within a small block by comparing the transmitting cell identification information of the transmitting cell identification information with the receiving cell identification information of the receiving cell identification information generating means; and a sequence number added to the test bit cell. A check bit detecting means for detecting discard by inspecting the data cells in the small block, and (M-p
) data cells and p check bit cells, with M bits of information recorded in the same bit position as a unit, and the information bits (M-p) bits and check bits are decoded and discarded. The part other than the s2th bit from the 51st bit of the data cell is restored, and the 81st bit of the data cell is restored.
The discarded cell restoring means extracts the information recorded in the 52nd bit from the 81st bit from the cell discard detection cell and inserts it into the 81st bit to the 52nd bit of the data cell to restore the original information. can.

[Effect]

The transmitting side device performs processing for cell discard detection and cell discard compensation on the output signal of the multiplex converter using a discard compensation encoding means, encodes the signal, and transmits the encoded signal to the receiving side. The receiving side device receives the output signal of the transmitting side device using a discard compensation decoding means, performs cell discard detection and cell discard compensation on the decoded signal at a stage before the multiplexing/demultiplexing device, and provides the decoded signal to the multiplexing/demultiplexing device.

Further, the discard compensation encoding means uses the transmission cell identification information extraction means to extract the transmission cell identification information from (an integer N of 2 or more - an integer q of 1 or more) data cells output from the multiplex converter. The cell discard detection cell generation means generates q cell discard detection cells to which sequence numbers are added based on the output information of the transmission cell identification information extraction means. The cell discard detection cell adding means adds the output signal of the cell discard detection cell generation circuit to the corresponding (
N-q) data cells and output as a small block. The check bit adding means outputs the data cell discard detection cell adding means (an integer M of 2 or more - an integer p of 1 or more).
) sets of small blocks are input, and (N
- Information bits for part or all of the information of one or more integer sets consisting of (M-p) bits recorded in the same bit position for Q) set of data cells and q sets of cell discard detection cells. (M-p) bits and check bits p bits are systematically encoded, and the check bits generated by this systematic encoding are inserted into N sets of p cells, each set being N sets of p cells. A set of check bit cells is generated, a sequence number is inserted into the s1th bit to the 52nd bit of the check bit cell, and the check bit cell is added to the (M-p) set of small blocks and transmitted as a large block.

Further, the discard compensation decoding means detects the discard of the cell discard detection cell based on the sequence number added to the cell discard pressure detection cell received by the cell discard detection cell restoration means, and detects the discard of the cell discard detection cell compensation check bit. The cell discard detected cell is restored based on the cell discard detection. received by the receiving cell identification information generating means (
Receiving cell identification information is generated for each of M-p) small blocks. Included in the q cell discard detection cells of each small block received by the data cell discard detection means (
N-q) pieces of transmitting cell identification information and receiving cell identification information of the receiving identification information generating means are compared to detect data cell discard within the small block. The check bit detection means checks the sequence number added to the check bit cell to detect its discard. The discarded cell restoring means generates a set of cells (N
-q), the cell position in the small block is recorded at the same bit position of (M-p) data cells and p check bit cells using p check bit cells whose cell position is the same as that of the data cell. The information bit (M-p) bit and the check bit are decoded using the M-bit information as a unit, and the 51st to 82nd bits of the discarded data cell are decoded.
The part other than the bit is restored, the information recorded in the Sl bit to the 52nd bit of the data cell is extracted from the cell discard detection cell, and is inserted into the 51st to 52nd bits of the data cell to restore the original information. Restore information.

That is, the transmitting side device collects transmitting cell identification information (hereinafter referred to as CRP) from (N-q) data cells.

That's what it means. ) is generated and inserted into q cells for cell discard detection (hereinafter referred to as CLD cells). When writing a sequence number from bit S1 to bit S2 in a test bit cell, a test bit cannot be inserted at that position. Therefore, the information from the 81st bit to the 52nd bit of the data cell cannot be restored by error correction. Therefore, in CRP s, 5 bits from Sl bit of the data cell are added.
If the information recorded in the second bit (hereinafter referred to as save information) is not included, the save information of each data cell is also inserted into the CLD cell. The above (N-Q) data cells and q CLD cells constitute a small block. Each CLD cell is assigned a sequential order number among CLD cells.

Next, p small blocks constituted by test bit cells are generated from the (M-p) small blocks. Among the N sets of (M-p) cells with the same cell position in the small block, for the (N-q) set of cells made up of data cells, the area where the VPI in the header is written. Encoding is performed on areas other than the area where the CRC (HEC area) of the header and the sequence number of the check bit cell are written.

For encoding, each information bit (including the header area) of a data cell is recorded at the same bit position (M-
p) Perform systematic encoding (hereinafter referred to as M,p) encoding of information bits (M-p) bits and check bits p bits on the information of p) bits, and generate p check bits of the generated p bits. Insert into the same bit position of the test bit cell.

Furthermore, a set of p data cells is generated (
N-q) consecutive order numbers are added between the sets of test bit cells. In addition, for q cell groups composed of CLD cells, only the CRP generated from each data cell and the area in which evacuation information is written in the information area of the CLD cell are subject to encoding, and the data 1 like cell
Q sets of p test bit cells for CLD cell compensation are generated. The test bit cells generated here include C
A sequence number consecutive to the sequence number added to the LD cell is added.

Above, there are (M-p) sets of small blocks, each set consisting of p pieces (
N-q) sets of data cells Compensation test pit senopes q sets of CLD cells Compensation test bit cells consisting of p sets of data cells Total N
A large block is made up of XM cells, and the transmitting side uses this large block as a unit of transmission.

The receiving device first checks whether the received cell is a data cell or not.
Distinguish whether it is a test bit cell or a CLD cell. When a CLD cell is received, the attached sequence number is checked to confirm continuity with the sequence number of the CLD cell received immediately before, and the discard of the CLD cell is detected. C.L.
If the D cell has been discarded, the CLD cell is restored by the following procedure, and then data cell discard detection and compensation are performed. When discarding a CLD cell is detected, processing is interrupted until a CLD cell compensation check bit cell is received, and the received cells are buffered in the meantime.

CLD cell compensation test via) After cell reception, (M, p)
The code is decoded to restore the CLD cell. If the CLD cell cannot be restored normally, processing of the large block being processed is stopped, the received data cells belonging to the large block are output as they are, and the CLD cells and check bit cells are removed.

After normally receiving a CLD cell and after successfully restoring it, a CRP is generated from the received data cell.

A CRPS in the CLD cell that matches the CRP generated from the data cell is searched, and the position in the CLD cell is determined.

CRP in CLD cells.

Since the position corresponds to the cell position in the small block of data cells, this checks the continuity of the cell position in the small block of received data cells and detects the discard of the data cell. If no cell discard is detected in the small block under inspection, and no cell discard is detected in the large block to which the small block belongs before the small block under inspection, When the data cell discard detection is completed, the small block of cells is output. If a data cell is detected to have been discarded, a dummy cell is inserted in that position. In this case, cells are not output even after discard detection is completed, and cells for which discard detection and dummy cell insertion have been completed are buffered until the end of the large block. Thereafter, the (M,p) code is decoded using the check bit cell to restore the data cell. However, the saved information written from the S1th bit to the 52nd bit is not restored by M, p) decoding. Evacuation information is C
Since it is in the LD cell, the saved information is extracted from there and inserted into the restored cell. This restores the discarded data cells.

As described above, cell discard compensation can be performed even if consecutive sequence numbers are not added to the cells to be processed, and the delay time required for encoding and decoding can be gradually reduced.

[Example] An example of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of a cell transmitting/receiving device according to a first embodiment of the present invention. FIG. 2 is a block diagram of the cell discard detection cell addition circuit of the cell transmitting/receiving apparatus according to the first embodiment of the present invention. Third
The figure is a block diagram of a test bit cell adding circuit of the cell transmitting/receiving device according to the first embodiment of the present invention. FIG. 4 is a block diagram of the cell discard detection and dummy cell insertion circuit of the cell transmitting/receiving apparatus according to the first embodiment of the present invention. FIG. 5 is a block diagram of the discarded cell restoration circuit of the cell transmitting/receiving apparatus according to the first embodiment of the present invention.

In FIGS. 1 to 5, the cell transmitting/receiving device includes a transmitting device 210 and a receiving device 220.
10 includes a terminal 211 and a terminal 2 as a plurality of transmitting terminals.
The receiving side device 220 includes a multiplex converter 212 that multiplexes and transmits cells or packets from the multiplex converter 212, and a multiplex converter 222 that separates the output signal of the multiplex converter 212, and an output signal of the multiplex converter 222. The terminal 221 is included as a plurality of receiving side terminals each inputting a signal.

Here, the feature of the present invention is that the transmitting side device 210
includes a discard compensation encoding circuit 213 as a discard compensation encoding means that performs processing for cell discard detection and cell discard compensation on the output signal of the multiplex converter 212, encodes it, and transmits it to the receiving side; Sending side device 21
A discard compensation decoding circuit 223 is included as a discard compensation decoding means that performs cell discard detection and cell discard compensation on a signal obtained by receiving and decoding an output signal of 0 at a stage before the demultiplexing device and supplies the signal to the demultiplexing/demultiplexing device 222. It is in.

The discard compensation encoding circuit 213 includes a transmitting cell identification information extracting means for extracting the transmitting cell identification information from the (N-q) data cells output from the multiplex converter 212, and output information of the transmitting cell identifying information extracting means. cell discard detection cell generation means for generating q cell discard detection cells to which sequence numbers are added based on the cell discard detection cell generation circuit; Input a set of small blocks (integer M of 2 or more - integer p of 1 or more) output by the cell discard detection cell addition means and the data cell discard detection cell addition means, which are output as small blocks, and (M
- information of an integer set of 1 or more consisting of (M-p) bits recorded in the same bit position for (N-Q> sets of data cells and q sets of cell discard detection cells consisting of (p) bits) systematic encoding of information bits (M-p) bits and p check bits is performed for part or all of , and the check bits generated by this systematic encoding are inserted into N sets of p cells. N sets of test bit cells each consisting of p test bit cells are generated, and 51 of these test bit cells are
Insert a sequence number from the bit to the S2 bit, and (M-
p) test bit cell adding means for adding the test bit cell to a set of small blocks and transmitting the test bit cell as a large block;

Further, the discard compensation decoding circuit 223 detects the discard of the cell discard detection cell based on the sequence number added to the received cell discard detection cell, and detects the discard of the cell discard detection cell based on the received cell discard detection cell compensation check bit. a cell discard detection cell restoring means for restoring the cell discard detection cell restoring means; a receiving cell identification information generating means for generating receiving cell identification information for each of the (M-p) received small blocks; data cell discard detection for detecting data cell discard in a small block by comparing (N-q) pieces of transmitting cell identification information included in the cell discard detection cells with the receiving cell identification information of the receiving identification information generating means; a check bit detection means for checking the sequence number added to the check bit cell to detect its discard;
For a set (N-q) of cells consisting of M-p) data cells, use p test bit cells whose cell positions in the small block are the same as the data cells. The S1 bit of the data cell is discarded after decoding the information bit (M-p) bit and the check bit using M bits of information recorded in the same bit position of the data cell and p check bit cells as a unit. Restoring the parts other than the 52nd bit from the 51st bit to the 8th bit of the data cell
The discarded cell restoring means extracts the information recorded in the second bit from the cell discard detection cell and inserts it into the 51st to 62nd bits of the data cell to restore the original information.

That is, the discard compensation encoding circuit 213 includes a cell discard detection cell addition circuit and a check bit cell addition circuit. The cell discard detection cell addition circuit includes a buffer 3 for input waiting.
1, CRP, extraction circuit 32, (N-1) base counter 33
, a switch 34, a sequence number addition counter 35, a CLD cell generation circuit 36, and a CRC24 generation circuit.

Further, the test bit cell addition circuit includes an adder circuit 22, NX (M-1
) includes an advance counter 23, a switch 24, a sequence number addition counter 25, a check bit cell storage memory 26, and a data cell CLD cell identification circuit.

Furthermore, the discard compensation decoding circuit 23 includes a cell discard detection and dummy cell insertion circuit and a discarded cell restoration circuit.

The cell discard detection and dummy cell insertion circuit includes the components shown below.

41 CLD cell data cell distribution circuit.

42 Buffer for waiting for data cells.

Memory for 431 cells.

44 CRPr generation circuit.

45 Dummy cell generation circuit.

46-48.52 Switch.

49 Cell disposal circuit.

50 Dummy cell generation circuit.

51 Output cell number counter. The number of cells output for each small block is counted and the number J is output.

Addition circuit modulo 532.

54 Memory for storing restored CLD cells (for 1 cell).

55 Buffer for CLD cell waiting.

56 Sequence number inspection circuit.

57 CLD cell holding memory. Holds two CLD cells. One holds the CLD cell corresponding to the small block currently undergoing discard detection, and the other holds the CLD cell corresponding to the next small block.

58 Cell position detection circuit for detecting the cell position within a small block of data cells (CR in CLD cell
Of Ps, CRP extracted from the received data cell,
, but find the position in the CLD cell. The position of the obtained CRP is set to 1. If the CRP of the data cell matches the CRP of the CLD cell of the second lock, a small block end signal is output, a new CLD cell is written to the memory 57, and the CLD corresponding to the inspected small block is The cell is output from the CLD cell output terminal 62.

).

59 Switching control circuit. Position signal 1 and small block end signal output by cell position detection circuit 58 and counter 51
The switches 47 and 48 are controlled based on the output j of , and dummy cells are inserted and misplaced cells are discarded.

60 Sequence number checking circuit. When the cell to be added is a test bit cell, the continuity of the sequence number is checked, and if discontinuity of the sequence number is detected, the switch 52 is controlled to insert a dummy cell.

61　Data cell output terminal.

62 CLD cell output terminal.

63(N-1)xM-ary counter.

Further, the discarded cell restoration circuit includes the following components.

71 Buffer for waiting for input.

72 Inspection bit cell discard circuit.

73 Buffer for output waiting.

74 Switch.

75 CLD cell holding memory.

76VCI area restoration circuit.

Addition circuit modulo 772.

78 Discarded cell restoration circuit.

79 (N-1) base counter.

80 Dummy cell detection circuit.

81 CLD cell input terminal.

82 Data cell input terminal.

83 (N-1)X (M-1) base counter.

84 (N-1) XM-ary counter.

The operation of the cell transmitting/receiving device having such a configuration will be explained. FIG. 6 is a block diagram of a small block of a cell transmitting/receiving apparatus according to a first embodiment of the present invention. FIG. 7 is a block diagram of a large block of a cell transmitting/receiving apparatus according to a first embodiment of the present invention. FIG. 8 is a configuration diagram of a cell discard detection cell of the cell transmitting/receiving apparatus according to the first embodiment of the present invention. FIG. 9 is a configuration diagram of a data cell compensation test bit cell of the cell transmitting/receiving apparatus according to the first embodiment of the present invention. FIG. 10 is a configuration diagram of a cell discard detection cell compensation inspection bit cell of the cell transmitting/receiving apparatus according to the first embodiment of the present invention. FIG. 22 is a configuration diagram of an asynchronous transfer mode network of cell transmitting/receiving equipment.

ATM (Asynchronous Transfer)
r Mode, asynchronous transfer mode) network VP (Vir
tual Path)
Illustrate. In an ATM network, information is transmitted in fixed-length cells. The transmission path of a cell is determined by information in the header portion of each cell. In the embodiment shown here, the present invention is applied to VP, so that all cells passing through each device have a common VP I (Vi
(orual Path Identifier). FIG. 22 is a diagram showing the structure of cells on relay transmission paths currently recommended by CCITT. cell is 53
It consists of byte information, the first 5 bytes are a header, and the remaining 48 bytes are an information area. For the header, the first 12 bits are VP I, the next 16 bits are VCI
(Virtual channel 1 dentifi
er), the next two bits indicate the type of information (PT:P
ayload Type), the next 2 bits are a reserved area, the last 8 bits are a bit error control in the header, and a CRC (Cycle Redundancy [h
eck). This is the first 40 pieces of information in the header.
Generate by encoding the bit part.

In this embodiment, the first 6 bits of the VCI and information area of the header of each data cell are used as transmitting cell identification information (CRP, ) and receiving cell identification information (CRP, ).

Since the VCI of each data cell is 16 bits, CRP, ,C
The length of RP is 22 bits. Currently, in the cell configuration method recommended by CCITT, five types of information area configurations (adduction layer configurations) are recommended.In four of these methods, the first 4 bits of the information area or the information A sequence number added between terminals is inserted into the third to sixth bits of the area.

Under the communication form using any one of these four configurations, CRPrSCRP as described above.

When using CRPs, CRPs generated from a plurality of different data cells do not match within the period of the sequence number (the sequence number is 4 bits, so the period is 16). Therefore, such CRP.

By using CRP, it is possible to reliably detect cell discard and identify the location where the cell is discarded. Also,
In this embodiment, the sequence number inserted into the test bit cell is inserted into the VCI area of the test bit cell. Therefore, the VCI area of the data cell is not restored by error correction. Since the VCI of each data cell is included in the CRP,
There is no need to insert evacuation information into the CLD cell separately from the CRP. In this embodiment, the number of cells in a small block is N, of which (N-1) are data cells and one is a CLD cell. FIG. 8 shows the configuration of a CLD cell.

The CRP extracted from the (N-1) data cells of each small block is inserted into the information area of the CLD cell. Each CL
The information area of the D cell contains the CRP, consecutive sequence numbers between CLD cells, and 24-bit CRC (hereinafter referred to as C
It's called RC24. ). CLD by sequence number
It is possible to detect cell discard, and C
Bit errors in LD cells can be corrected and CLD cells can be recognized.

In this embodiment, (M, p
) This is an example in which a parity check code is used as a systematic code. As shown in FIGS. 9 and 10, for data cells, the objects of encoding are VP I in the header area,
This is the entire information area and the parts other than the VCI and CRC, and for the CLD cell, it is only the area where the information area CRP is recorded. A large block is made up of M small blocks, of which (M-1) are data cells and one is a test bit cell. Here, a set of cells having the same cell position within each small block will be referred to as cells belonging to the same column of the large block.

In FIG. 2, as an initial state, first, the switch 34
is set on the buffer 31 side. The input cells pass through the buffer 31 and the switch 34 before being output. When the data cell passes, the CRP, extraction circuit 32
Copies 16 bits of information in the VCI area and the first 6 bits of the information area from the passing data cell as CRP. The CLD cell generation circuit 36 inserts the CRP, the CRP extracted by the extraction circuit 32, into the information area of the CLD cell. At this time, the number generated by the sequence number addition counter 35 is inserted as the sequence number of the CLD cell, and the CRC24 generated by the CRC24 generation circuit 37 is also inserted.

A CLD cell is completed when (N-1) data cells have passed through. The (N-1) base counter 33 counts the number of passing data cells, controls the switch 34 when (N-1) data cells have passed, and controls the CLD cells generated by the CLD cell generation circuit 36. Outputs one.

Thereafter, the switch 34 is returned to its original position, and the next small block is processed in the same manner. In this circuit, there is no need to wait for the input data cell except during the period when the CLD cell is being output, so the delay time caused by this circuit is extremely small.

In FIG. 3, CLD cells and data cells are input from input terminals, and the input cells pass through a buffer 21, a switch 24, and are output.

At this time, the adder circuit 22 performs addition modulo 2 for each cell position within the small block and for each bit at the same bit position within the cell for the passing cells, and the cumulative value is checked by the bit cell storage memory 26. Accumulate in. Since the area to be encoded differs depending on whether the passing cell is a data cell or a CLD cell, the area to be encoded (added) is switched based on the output of the data cell CLD cell identification circuit 27. Data cell CLD cell identification circuit 27 is CL
The data cell CLD cell is identified by calculating the CRC24 added to the D cell. data cell is N
N test bit cells are completed after X(M-1) passes. At that point, counter 23 controls switch 24 to output the N test bit cells stored in test bit cell storage memory 26. At this time, a sequence number is generated by the sequence number addition counter 25 and sequentially inserted into the test bit cells to be output. After outputting N check bit cells, the switch 24 is returned to its original position and the next large block is processed in the same manner. In this circuit, there is no need to wait for the input data cell except for the time when the test bit cell is being output, so the delay time due to this circuit is extremely small.

In FIG. 4, as an initial state, first, the output cell number counter 51 and the CLD cell restoration circuit 54 are initialized. The switch 46 is set to the memory 43 side.

A cell input from an input terminal is divided into a data cell and a CLD cell by a distribution circuit 41, and each cell is divided into a data cell and a CLD cell by a buffer 4.
2 and input to buffer 55. When the CLD cell output from the distribution circuit 41 is input to the buffer 55, the adder circuit 53 adds 2 bits for each bit position of the CLD cell.
Addition is performed modulo , and the cumulative value is stored in the CLD cell restoration circuit 54.

If no CLD cells are discarded within the large block, the CLD cell restoration circuit 54 receives the header, sequence number,
A cell with all bits "0" except for the CRC24 area is generated. If one CLD cell is discarded in a large block, the CLD cell restoration circuit 5 after receiving the large block
4, a CLD cell with the same CRP as the discarded CLD cell is restored. If two or more CLD cells are discarded, meaningless data is generated in the CLD cell restoration circuit 54. After passing through the buffer 55, the CLD cell is temporarily stored in the memory 43, and a sequence number checking circuit 56 checks the sequence number added to the CLD cell. If the sequence number is consecutive to the previous CLD cell, it passes through the changeover switch 46 and is input to the CLD cell holding memory 57. CLD if the sequence numbers are discontinuous
This means that cell discard has been detected. Abandoned CLD
The number of cells can be determined from the sequence number. If the number of discarded CLD cells in a large block is one, the discarded CLD cell is correctly restored by the CLD cell restoration circuit 54 after receiving the large block, so the switch 46 is switched to the CLD cell restoration circuit 54 side, and the CLD cell is restored. A CLD cell is taken out from the cell restoration circuit 54 and input into a CLD cell holding memory 57. In addition, if there are two or more CLD cells discarded in a large block, the CLD cells are not correctly restored by the CLD cell restoration circuit 54, so that cell discard detection, dummy cell insertion, and discarded cell restoration are performed for that large block. All processing is stopped, CLD cells and check bit cells are removed from the input cells, and the data cells are output as they are.

When the CLD cell is normally input to the CLD cell holding memory 57, the data cell is output from the buffer 42 and passes through the switches 47 and 48. At that time, CRP,
The generation circuit 44 extracts the CRP of the passing data cell, the cell position detection circuit 58 detects the position of the data cell within the small block, and outputs the data cell position [1] within the small block. The cell position detection circuit 58 outputs 1=0 when the CRPr generated from the data cell does not match all the CRPs of the CLD cell being processed. Further, the cell position detection circuit 58 detects all the CRPs of the CLD cells being processed by the CRP generated from the data cells.
RP, and C in the CLD cell of the next small block.
If it matches the RPS, it outputs the detected cell position (iE as well as an end signal indicating that the processing of the small block has ended. After the data cell passes through the switch 48,
The number of processed data cells in the small block is counted by the output cell number counter 51, and the output cell number counter 51 outputs the counting result ['']. The counter is initialized to '0' at the beginning of each small block. The control circuit 59 controls the switches 47 and 48 using the output [1] of the position detection circuit 58, the termination signal, and the output [J] of the counter 51, and discards the abnormal cell and inserts a dummy cell.

The processing procedure is as follows.

When the end signal is not output from the position detection circuit 58: 1=J: No cell is discarded before the data cell under test in the small block under test. Switch 47 is on the buffer 42 side, switch 48 is on the switch 52 side
side and transfer the data cells to switch 52.

1>”: There are (i−j) cells discarded before the data cell under examination in the small block under examination. The switch 48 is set to the switch 52 side, the switch 47 is set to the dummy cell generation circuit 45 side, and the dummy cell is set to (
Insert ii-j) pieces. Thereafter, the switch 47 is turned to the buffer 42 side to transfer the data cells.

]〈J or 1=0: The data cell under inspection is a cell that arrived due to misdelivery. Switch 47 to buffer 42 side,
The switch 48 is set to the cell discard circuit 49 side to discard the data cell.

When the end signal is output: The data cell under inspection is processed as a cell of the next small block. In this case, since the data cell processed immediately before is the last cell in the small block under inspection, the following processing is performed before starting processing of the next small block. However, the number of cells in the small block is N, of which (N-1) are data cells.

j=N-1: No cells are discarded after the data cell processed immediately before. In this case, processing immediately proceeds to the next small block.

j<N-1: (N-1
−j) cells are discarded. The switch 47 is set to the dummy cell generation circuit 45 side, the switch 48 is set to the switch 52 side, and (N-1-j) dummy cells are inserted.

When the passing cell is a test bit cell, the sequence number checking circuit 60 checks the continuity of the sequence number added thereto to detect the discard of the test bit cell. (N-1)
The xM-ary counter 63 indicates the position of the output cell within the large block, so the counter value is C(N-1)
If the value is between X(M-1)+13 and C(N-1)xM), it can be determined that the cell being output is a test bit cell. If the sequence numbers are discontinuous, that is, discard is detected, switch 52 is switched to the dummy cell generation circuit 50 side,
Dummy cells equal to the number of discarded test bit cells are inserted.

The above operations provide the following effects.

(2) By using CLD cells, it is possible to detect the discard of data cells to which no sequence number has been added, and it is possible to insert a dummy cell at the position where discard is detected. Since discard detection is performed in units of small blocks, the delay time required to perform discard detection is approximately N cell time.

■ Detection can be performed if a CLD cell is discarded. Furthermore, if only one CLD cell is discarded within a large block, it can be compensated for, and discard detection can be performed using the compensated CLD cell.

■ If a test bit cell is discarded, the discard can be detected and a dummy cell can be inserted in the discarded position.

In FIG. 5, as an initial state, first, the switch 74
is set on the buffer 73 side, the discarded cell restoration circuit 78 is initialized, and the (N 1) base counter 79 and (N-1)
The (M-1) base counter 83 and the (N-1)XM base counter 84 are initialized to "0". The CLD cells of each large block are inputted from the CLD cell input terminal 81 and held in the CLD cell holding memory 75.

A data cell is input from a data cell input terminal 82, passes through a buffer 71, and reaches a test bit cell discard circuit 72. At this time, regarding the passing data cells, addition modulo 2 is performed for each bit position between cells belonging to the same column within the small block, and the result is held in the discarded cell restoration circuit 78. The cell position within the small block of passing data cells is indicated by an (N-1)-ary counter 79. If the number of discarded cells among the cells in each column is one or less, after large block reception is completed, the discarded cell restoration circuit 78 restores the information in the part of the discarded cell header excluding the VP I, VCI, and CRC areas. Ru. If the passing cell is a test bit cell, the test bit cell discard circuit 72 discards it within the circuit, and outputs the normal data cell as it is. If the CLD cell is input normally, the value of the (Nl)xM-ary counter 84 indicates the position of the data cell within the large block, so the value is C(N-1)x(M
-1) +IE to C(N-1)XM], it can be determined that the cell input to the test bit cell discard circuit 72 is a test bit cell, and in that case, the input test bit cell is discarded. The data cell output from the test bit cell discard circuit 72 passes through a buffer 73 and reaches a switch 74. The dummy cell detection circuit 80 is a buffer 73
The cell output from the cell is monitored, and if the cell to be output is not a dummy cell, the switch 74 is set to the buffer 73 side, and the cell is output as is.

When the dummy cell detection circuit 80 detects the first dummy cell in the large block, the switch 74 is set to the neutral position, cell output is stopped until the end of the large block, and data cells are buffered in the buffer 73. Thereafter, when the last cell of the large block is input to the buffer 73, the switch 74 is switched to the buffer 73 side and output is resumed. At this time, the dummy cell detection circuit 80 also checks whether the output cell is a dummy cell, and if it is a dummy cell, the switch 74 is set to the discarded cell restoration circuit 78 side.
The restored cells are output to the restoration circuit 78. At that time, the corresponding dummy cell is discarded. (N-1)X (
M-1) The base counter 84 counts the number of output cells. The discarded cell restoration circuit 78 is (N-1)X (M-1
) The cell position within the small block of the dummy cell detected from the output of the advance counter 83 and the position of the small block within the large block are detected.

In addition, the CL held in the CLD cell holding memory 75
VC from D cells corresponding to the restored cell
The I area restoration circuit 76 takes out the VCI of the cell to be restored and inserts it into the restored cell.

At the same time, the restoration circuit 78 inserts the VPI that is common to the cells being processed by that circuit, and recalculates the CRC of the header. However, if the cell is not restored correctly because there are two or more discarded cells in the column, the discarded cell restoration circuit 78 sends a cell discard compensation prohibition signal to the switch 74.
Cell discard compensation is not performed by transferring to

The above operations provide the following effects.

■ A dummy cell inserted in the position of a discarded cell can be restored.

(2) If a cell cannot be correctly restored because there are two or more discarded cells in a column, discard compensation is not performed, so other correctly received data cells are not affected.

■ If no cells are discarded within a large block, the delay time required for decoding is extremely small.

■ The time order of cells can be preserved even when cell discard compensation is performed.

- Since one cell can be compensated for each column of the large block, it is possible to compensate for the discard of up to N consecutive cells.

FIG. 11 is a block diagram of a cell discard detection cell generation circuit of a cell transmitting/receiving apparatus according to a second embodiment of the present invention.

FIG. 12 is a block diagram of a test bit cell adding circuit of a cell transmitting/receiving apparatus according to a second embodiment of the present invention. FIG. 13 is a block diagram of a cell discard detection and dummy cell insertion circuit of a cell transmitting/receiving apparatus according to a second embodiment of the present invention. FIG. 14 is a block diagram of the discarded cell restoration circuit of the cell transmitting/receiving apparatus according to the second embodiment of the present invention.

FIG. 15 is a block diagram of a cell transmitting/receiving apparatus according to a second embodiment of the present invention. FIG. 16 is a configuration diagram of a cell discard detection cell of a cell transmitting/receiving apparatus according to a second embodiment of the present invention. FIG. 17 is a configuration diagram of a test bit cell for data cell compensation in a cell transmitting/receiving apparatus according to a second embodiment of the present invention. FIG. 18 is a configuration diagram of a test bit cell for cell discard detection and cell compensation in the cell transmitting/receiving apparatus according to the second embodiment of the present invention.

In this embodiment, the procedure for generating CRP for each cell is as follows. Systematic encoding of upper information bits and r check bits is performed on L bits constituting a cell. As a result, the obtained r-bit check bits are used as the CRPS of that cell. In this case, the probability that the CRPs of two different cells match is 2-'. By increasing the bit number r of CRPs, the reliability of cell discard detection can be increased. As in the first embodiment, a sequence number is inserted into the VCI area of the test bit cell.

Therefore, the VCI area of the data cell is not restored by error correction. Therefore, the information that should be saved in the CLD cell as save information is the VCI of each cell. C
The configuration of the LD cell is as shown in FIG.

In this embodiment, the number of cells in a small block is N, of which (N-1) are data cells and one is a CLD cell.

The CRP extracted from the (N-1) data cells of each small block and the VCI as save information are inserted into the information area of the CLD cell. The information area of each CLD cell contains C
Along with the RP and SVC, consecutive sequence numbers and CRC24 are inserted between the CLD cells as in the first embodiment.

The discarded CLD cell can be detected using the sequence number, and the CRC 24 allows correction of bit errors in the CLD cell and recognition of the CLD cell.

In this embodiment, a code with (M-p) bits in the information area and p bits in the check bit is used to restore a discarded cell. The code may be any systematic code, such as Hamming code, BCH code, Reed-Solomon code (R3 code), etc. A large block consists of M small blocks, of which (M-p) small blocks are data cells and p are check bit cells.

FIG. 11 shows a CLD cell addition circuit, in which 181 is a buffer for input waiting, 182 is a CRP, and a VCI.
An extraction circuit, 183 is a (N-1> base counter, 184 is a switch, 185 is a counter for adding sequence numbers, 186 is a C
The LD cell generation circuit 187 is a CRC24 generation circuit.

As an initial setting, the switch 184 is set to the buffer 181 side, and data cells are input from the input terminal.

The input cells pass through the buffer 181 and switch 1
It is output after passing through 84. When the data cell passes, the CRP, VCI extraction circuit 182 systematically encodes the information area L bit and the check bit R bit for the entire data cell, and inserts the generated check bit into the CLD cell. The code used in this case may be any systematic code, such as a BCH code or CRC. Additionally, 16 bits of information in the VCr area are inserted into the CLD cell as save information for each data cell.

The CLD cell generation circuit 186 outputs the CRP, the CRP extracted by the VCI extraction circuit 182, and the saved information to the CL.
Insert into the information area of the D cell. At this time, the number generated by the sequence number addition counter 185 is inserted as the sequence number of the CLD cell, and the CRC24 generation circuit 187
Insert the CRC24 generated by A CLD cell is completed when (N-1) data cells have passed through.

The (N-1) base counter 183 counts the number of passing data cells, controls the switch 184 when (N-1) data cells have passed, and controls the CLD cell generation circuit 18.
One CLD cell generated by step 6 is output. Thereafter, the switch 184 is returned to its original position, and the next small block is processed in the same manner.

In this circuit, there is no need to wait for the input data cell except for the time when the CLD cell is being output.
The delay time caused by this circuit is extremely small.

FIG. 12 shows a test bit cell adding circuit, the components of which are as follows.

101 input terminal.

102 input waiting buffer.

103Denita cell holding memory.

104 (M, p) encoder (performs systematic encoding of M bits of information bits and p bits of check bits).

105 Nx (M-p) base counter.

106 Switch.

107 Sequence number addition counter.

108 test bit cell holding memory.

109CLD cell data cell identification circuit.

As an initial state, first, the NX (M-p) base counter 10
5 and set the switch 106 to the buffer 102 side. The CLD cell and data cell input from the input terminal 101 pass through the buffer 102, reach the switch 106, and are output. At this time, the passing Nx (M-p) cells are copied and stored in the memory 103. After Nx (M-p) data cells have passed, the (M-p) cells in the same column of the large block are organized into information bits (M-p) bits and check bits p bits for each bit position. Encoding is performed, and the generated check bits are inserted into N sets of p check bit cells.

At this time, since the area to be encoded differs depending on whether the cell is a data cell or a CLD cell, the area to be encoded is switched based on the output of the CLD cell data cell identification circuit 109. CLD cell data cell identification circuit 10
9 identifies data cells and CLD cells by calculating the CRC24 inserted in the CLD cells.

Furthermore, the sequence number generated by the sequence number addition counter 107 is inserted into the VCI area of the generated check bit cell. After the test bit cells are generated, the switch 10G is switched to the test bit cell holding memory 108 side, and nine sets of small blocks constituted by the test bit cells are output.

FIG. 13 shows a cell discard detection and dummy cell insertion circuit. Each component is as follows.

141 distribution circuit (distributes CLD cells, data cells, and detection bit cells).

142 data cell waiting buffer.

Memory for 1431 cells.

144CRP, generation circuit (performs systematic encoding with p information bits and p check bits, and converts the check bits into CRP)
, output as ).

145.150 dummy cell generation circuit.

146-148.152 Switch.

149 cell discard circuit.

151 Output cell number counter (counts the number of output cells among the cells in the large block being processed and outputs the number).

153 (M, p) decoder (information bits (M-p
) bit, a circuit that decodes the systematic code of p check bits). , 15154CLD cell restoration circuit.

Buffer for 155 discard detection cells.

156 sequence number inspection circuit (detects discard of a CLD cell from the sequence number added to the CLD cell, and switches 17
Controls 0.

Memory for holding 157 CLD cells, holding two CLD cells. One holds the CLD cell corresponding to the small block currently undergoing discard detection, and the other holds the CLD cell corresponding to the next small block.

A circuit for detecting the cell position within a small block of 158 data cells (CLD, which matches the CRP extracted from the received data cell among the CRPS in the cell,
Find the position in the CLD cell. The position of the obtained CRP is set to 1. If the CRP of the data cell matches the CRP of the discard detection cell of the second block, a small block end signal is output, a new CLD cell is written to the CLD cell holding memory 157, and the inspected small block is The CLD cell corresponding to is discarded. ).

159 switching control circuit. Position signal 1 of cell position detection circuit 158, small block end signal, and output cell number counter 1
Switches 147 and 148 are controlled from the output J of 51 to insert dummy cells and discard cells.

160 sequence number check circuit (detects discard of a test bit cell from the sequence number added to the test bit cell).

161 data cell output terminal.

162CLD cell output terminal.

163 (N-1) XM counter 164 (N-1) XM counter The cells are input to the distribution circuit 141 via input terminals.

If the input cell is an image data cell or a check bit cell, the distribution circuit 141 inputs it to a buffer 142, and if it is a CLD cell, it inputs it to a buffer 155. When a CLD cell is input to buffer 155, a copy thereof is held in CLD cell holding memory 161. When input to the CLD cell holding memory 161, the sequence number inspection circuit 165
The continuity of sequence numbers added to CLD cells is checked, and discarded CLD cells are detected. If the order number of the CLD cell input to the CLD cell holding memory 161 and the order number of the CLD cell input immediately before are not consecutive, the CLD cell has been discarded. In this case, a dummy cell is inserted in the position of the discarded CLD cell.

The first one of the CLD cells input to the buffer 155 is input to the memory 143, and the sequence number checking circuit 156 detects the continuity of the sequence numbers added to the CLD cells. The sequence number of the CLD cell stored in the memory 143 and the CLD cell stored in the memory 143 immediately before.
If the order numbers of the cells are consecutive, the CLD cells pass through the switch 146 and are input to the CLD cell holding memory 157. If the order numbers are not consecutive, after the CLD cells are restored, the switch 146 is turned to the CLD cell restoration circuit 154 side, and the CLD cells restored by the CLD cell restoration circuit 154 are input to the CLD cell holding memory 157.

The CLD cell restoration procedure is as follows.

After all CL, ) cells included in the large block are input to the CLD cell holding memory 161, the (M, p) decoder 153 decodes the CLD cells stored in the CLD cell holding memory 161 for each bit position. and restore the discarded CLD cells. discarded C
If the LD cell can be restored, the restored CLD cell passes through the switch 146 and is stored in the CLD cell holding memory 157.
is input. If a CLD cell cannot be restored, all processes of cell discard detection, dummy cell insertion, and discarded cell recovery are stopped for this large block, CLD cells and inspection bit cells are removed from the input cells, and data cells are Output as is.

If the CLD cell is normally input to CLD cell holding memory 157, the data cell is output from buffer 142 and passes through switches 147 and 148.

At that time, CRP is generated from the passing data cell by the CRP generation circuit 144, and the cell position detection circuit 15
8, the position of the data cell within the small block is detected, and the detected data cell position [1] is output.

The cell position detection circuit 158 detects C generated from the data cell.
If RP does not match the CRP of the CLD cell being processed, i=Q is output. In addition, the cell position detection circuit 158
is the CLD being processed by the CRP generated from the data cell.
The CRP in the CLD cell of the next small block does not match the CRP of the cell, ! (2) If they match, a termination signal indicating that the processing of the small block has been completed is output together with the detected cell position Ci). Data cell is switch 148
After passing through, the counter 151 counts the number of processed data cells in the small block, and the counter 151 outputs the counting result [j]. The counter is initialized to '0' at the beginning of each small block.

The switching control circuit 159 uses the output [l] of the position detection circuit 158.
and the end signal and the output of the output cell number counter 151 [j
], the switches 147 and 148 are controlled to discard abnormal cells and insert dummy cells.

The processing procedure is as follows.

When the end signal is not output from the position detection circuit 158: i=j: There is no cell discard before the data cell under test in the small block under test. The switch 147 is placed on the buffer 142 side, and the switch 148 is placed on the switch 152 side to transfer the data cell to the switch 152.

1>": There are (i-J) cells discarded before the data cell under test in the small block under test. The switch 148 is set to the switch 152 side, the switch 147 is set to the dummy cell generation circuit 145 side, and (l-J) dummy cells are inserted. Thereafter, the switch 147 is turned to the buffer 142 side to transfer the data cells.

i<j or 1=0: The data cell under test is a cell that arrived due to misdelivery. The data cell is discarded by setting the switch 147 to the hacker 142 side and the switch 148 to the cell discard circuit 149 side.

When the end signal is output: The data cell under inspection is counted as 8 cells of the next small block. In this case, since the data cell processed immediately before is the last cell in the small block under inspection, the following processing is performed before starting processing of the next small block. However, the number of cells in the small block is N1, of which (N-1) are data cells.

J=N-1: No cells are discarded after the data cell processed immediately before. In this case, processing immediately proceeds to the next small block.

j<N-1: (N-1
−j) side is discarded. The switch 147 is connected to the dummy cell generation circuit 145 side, and the switch 148 is connected to the switch 152 side.
N-1-j) dummy cells are inserted.

After being used for position detection, the CLD cell is output from the CLD cell output terminal 163.

When the cell passing through the sequence number checking circuit 160 is a test bit cell, the continuity of the sequence number added thereto is checked to detect discard of the test bit cell. counter 1
64 indicates the position of the output cell within the large block, and the counter value is C(N-1)x (M-p
)+1] to [(N-1)XM), it can be determined that the cell being output is a check bit. If discard is detected, the switch 152 is switched to the dummy cell generation circuit 150 side, and dummy cells equal to the number of discarded test bit cells are inserted.

The above operations provide the following effects.

(2) By using CLD cells, it is possible to detect the discard of data cells to which no sequence number has been added, and a dummy cell can be inserted at the position where discard is detected.

Since discard detection is performed in units of small blocks, the delay time required to perform discard detection is approximately N cell time.

■ Detection can be performed if a CLD cell is discarded. Also, the CLD cells discarded within the large block are (M, p) Ifl! A discarded CLD cell can be compensated for within the correction capability of the code, and discard detection can be performed using the compensated CLD cell.

■ If a test bit cell is discarded, the discard can be detected and a dummy cell can be inserted in the discarded position.

FIG. 14 shows a discarded cell restoration circuit, and each component is as follows.

121 data cell input terminal.

122 buffer for waiting for input.

123 check bit cell discard circuit.

Buffer for waiting for 124 output.

125 switch.

126CLD cell input terminal.

127CLD cell retention memory.

128 save information (in this embodiment, VCI>restoration circuit).

129 data cell holding memory C(N-1)XM cells)
.

130 (M, p) Systematic code decoder (a circuit that decodes the systematic code used to generate check bit cells, including information bits (M-p) bits and check bit p bits).

131 discarded cell restoration circuit.

132 (N-1) XM-based counter.

133 dummy cell detection circuit.

As an initial setting, the switch 125 is set to the buffer 124 side, and the (N-1)XM base counter 132 is initialized. The data cell receives data from the input terminal 121, passes through the buffer 122, and then passes through the inspection bit cell discard circuit 1.
23, buffer 124, switch 12
5 and is output. Further, the CLD cell is input from the CLD cell input terminal 126, and the CLD cell holding memory 1
It is held at 27. When passing through the test bit cell discard circuit 123, normal data cells pass through as is, and test bit cells are discarded. (N-1) XM-ary counter 1
If the CLD cell is input normally, the value of 32 indicates the position of the data cell within the large block.
1) XM], it can be detected that the cell input to the test bit cell discard circuit 123 is a test bit cell.

When the data cell is output from the buffer 124 and reaches the switch 125, the dummy cell detection circuit 133 checks whether the passing data cell is a dummy cell, and if it is a dummy cell, switches the switch 125 to the neutral position to detect the data cell. Output is temporarily interrupted and data cells are buffered in the buffer 124 until reception of the large block is completed. After the reception of the large block is completed, (M, p) decoder 1
30, M at the same cell position within each small block
For each (N-1) set of cells, the systematic code of information bits (M-p) bits (, check bits p bits) is decoded for each bit position, and cells that have been discarded and replaced with dummy cells are also included. and restore it to the data cell.

Since a sequence number is written in the vCI area of the test bit cell, the VC area of the data cell cannot be restored by this decoding.

Since the VCI of each data cell is saved as save information in the corresponding CLD cell, the CLD cell holding memory 12
The VCI is restored by the VCI restoration circuit using the CLD cell held in 7, and the VCI is inserted into the cell whose discard is generated by the restoration circuit 131.

Thereafter, the CRC of the header of the restored data cell is recalculated and its value is inserted. After the discarded cells are restored by the discarded cell restoration circuit 131, the switch 125 is switched to the buffer 124 side and data cell output is resumed.

At this time, the dummy cell detection circuit 133 checks whether the output data cell is a dummy cell or not, and if it is a dummy cell and the data cell has been correctly restored in the discarded cell restoration circuit 131, the switch 125 is switched to the discarded cell. It switches to the restoration circuit 131 side and outputs the restored data cells. At this time, the corresponding dummy cell is discarded. If the data cell is not correctly restored by the discarded cell restoration circuit 131, only the dummy cell is discarded and no data cell is output in its place.

The above operations provide the following effects.

■ A dummy cell inserted in the position of a discarded cell can be restored.

■ If cells in a column of a large block are discarded beyond the code's correction ability and cannot be restored correctly,
Since no discard compensation is performed, other correctly received data cells are not affected.

■ If no cells are discarded within a large block, the delay time required for decoding is extremely small.

■ The time order of cells can be preserved even when cell discard compensation is performed.

- Since discard compensation is performed for each column of large blocks, it is possible to compensate for discards of N or more consecutive cells.

FIG. 19 is a block diagram of a small block of a cell transmitting/receiving apparatus according to a third embodiment of the present invention. FIG. 20 is a block diagram of a cell transmitting/receiving apparatus according to a third embodiment of the present invention.

FIG. 21 is a configuration diagram of a cell for cell discard detection in a cell transmitting/receiving apparatus according to a third embodiment of the present invention.

In this embodiment, CRP, , and CRPr are the same as in the first embodiment. The number of cells in the small block is N, of which (N-2) are CLD cells and 112 cells are CLD cells. As shown in Figure 19, the small block is located at the beginning (
N/2-1) Cell is data Senope Next cell is first C
The next (N/2-1) cells in the LD Cenope are data cells, and the next one cell in the LD Cenope is the 20th CLD cell.

FIG. 21 shows the configuration of a CLD cell. Of the CRP extracted from the data cells of each small block, the first half (N/2
-1) CRP extracted from each cell.

is inserted into the first CLD cell, and the CRP extracted from the latter (N/2-1) cells is inserted into the information area of the 20th CLD cell. In the information area of each CLD cell, a CRPS, consecutive sequence numbers between CLD cells, and a CRC24 similar to the first embodiment are inserted. CLD by sequence number
Cell discard detection can be performed, and C
Bit errors in LD cells can be corrected and CLD cells can be recognized.

The (M, p) systematic code and encoding method for restoring discarded cells are the same as in the first embodiment. The configuration of the large block is shown in FIG. In addition, in this embodiment, two CLDs are used per small block as shown in FIG.
Although we have explained the case where cells are used, the case where q CLD cells are generally used per small block is also explained.
It goes without saying that the present invention can be similarly applied and similar effects can be obtained.

FIG. 2 shows a CLD cell addition circuit, and each component and operating procedure are the same as in the first embodiment of the present invention.

However, in this embodiment, instead of the (N-1)-base counter 3, an (N/2-1)-base counter is used.

The 10th CLD cell is generated when the first (N/2-1) data cells among the (N-2) data cells in the small block are output, and the next (N/2-1) data cells are generated. 1) A 20th CLD cell is generated at the time when 1) data cells are output.

Figure 3 shows the test bit cell addition circuit, with each component,
The operating procedure is the same as the first embodiment of the present invention.

FIG. 4 shows a cell discard detection and dummy cell insertion circuit, and each component and operating procedure are the same as in the first embodiment of the present invention. However, in this embodiment, instead of the (N-1)XM-ary counter 63, a (N-2)×M-ary counter is used.

Further, in this embodiment, the value of the counter 63 is ((N-2)x
If it is between (M-1)+11 and C(N-2)XMI, it is determined that the cell being output is a test bit cell.

FIG. 5 shows a discarded cell restoration circuit, and each component and operating procedure are the same as in the first embodiment of the present invention. 7 [Effects of the Invention] As explained above, in the present invention, the transmitting side device generates transmitting cell identification information from data cells, collects this transmitting cell identifying information, configures a cell discard detection cell, and performs cell discard detection. The cell is transmitted together with a check bit cell for restoring the data cell, the receiving device generates receiving cell identification information from the received data cell, and combines this receiving cell identification information with the sending cell identification information included in the cell discard detection cell. detecting cell discard by comparing the cell discard detection cell and the inspection bit cell;
By performing discard compensation, cell discard compensation can be performed even if consecutive sequence numbers are not added to the cells to be processed, and the excellent effect is that the delay time required for encoding and decoding can be gradually reduced. There is.

Furthermore, there is the advantage that a set of cell discard compensation circuits can be shared by a plurality of terminals, resulting in economical savings.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a cell transmitting/receiving device according to a first embodiment of the present invention. FIG. 2 is a block configuration diagram of a cell addition circuit for detecting cell discard in the cell transmitting/receiving apparatus according to the first embodiment of the present invention. FIG. 3 is a block configuration diagram of a test bit cell addition circuit for a cell transmitting/receiving lid according to the first embodiment of the present invention. FIG. 4 is a block diagram of the cell discard detection and dummy cell insertion circuit of the cell transmitting/receiving apparatus according to the first embodiment of the present invention. FIG. 5 is a block diagram of the discarded cell restoration circuit of the cell transmitting/receiving apparatus according to the first embodiment of the present invention. FIG. 6 is a configuration diagram of a small block of a cell transmitting/receiving device according to a first embodiment of the present invention. FIG. 7 is a configuration diagram of a large block of a cell transmitting/receiving apparatus according to a first embodiment of the present invention. FIG. 8 is a configuration diagram of a cell for cell discard detection in the cell transmitting/receiving apparatus according to the first embodiment of the present invention. FIG. 9 is a configuration diagram of a test bit cell for data cell compensation in the cell transmitting/receiving apparatus according to the first embodiment of the present invention. FIG. 10 is a configuration diagram of a test bit cell for cell discard detection and cell compensation in the cell transmitting/receiving apparatus according to the first embodiment of the present invention. FIG. 11 is a block configuration diagram of a cell addition circuit for detecting cell discard in the cell transmitting/receiving apparatus according to the second embodiment of the present invention. FIG. 12 is a block diagram of a test bit cell adding circuit of a cell transmitting/receiving device according to a second embodiment of the present invention. FIG. 13 is a block diagram of a cell discard detection and dummy cell insertion circuit of a cell transmitting/receiving apparatus according to a second embodiment of the present invention. FIG. 14 is a block diagram of the discarded cell restoration circuit of the cell transmitting/receiving apparatus according to the second embodiment of the present invention. FIG. 15 is a configuration diagram of a large block of a cell transmitting/receiving apparatus according to a second embodiment of the present invention. FIG. 16 is a configuration diagram of a cell for cell discard detection in the cell transmitting/receiving apparatus according to the second embodiment of the present invention. FIG. 17 is a configuration diagram of a test bit cell for data cell compensation in a cell transmitting/receiving apparatus according to a second embodiment of the present invention. FIG. 18 is a configuration diagram of a test bit cell for cell discard detection and cell compensation in the cell transmitting/receiving apparatus according to the second embodiment of the present invention. FIG. 19 is a configuration diagram of a small block of a cell transmitting/receiving device according to a third embodiment of the present invention. FIG. 20 is a configuration diagram of a large block of a cell transmitting/receiving apparatus according to a third embodiment of the present invention. FIG. 21 is a configuration diagram of a cell discard detection cell of a cell transmitting/receiving apparatus according to a third embodiment of the present invention. FIG. 22 is a block diagram of a cell in an asynchronous transfer mode network of cell transmitting and receiving equipment. FIG. 23 is a block diagram of a conventional cell transmitting/receiving device. 21.31.42.55.71.73.102.122
．． 124.142.155.181...Buffer, 2
2.53.77...addition circuit, 23...NX(M-
1) Decimal counter, 24.34.46 to 48.52.60
．． 74.106.125.146-148.152.1
67.184...Switch, 25.35.107.1
85... Sequence number addition counter, 26... Test bit cell storage memory, 27... Data cell CLD cell identification circuit, 32... Transmission identification information (CRPs) extraction circuit, 33.79.183... (N-1) base counter, 3
6.186...CLD cell generation circuit, 37.187.
...CRC24 generation circuit, 41.141...Distribution circuit, 43.143...Memory, 44.144...CR
P, generation circuit, 45.50.145.150.166-
...Dummy cell generation circuit, 49.149...Cell discard, 51.151...Output cell number counter, 54.15
4...CLD cell restoration circuit, 56.60.156.1
60.165...Sequence number inspection circuit, 57.75.1
27.157.161...CLD cell holding memory, 5
8.158...Cell position detection circuit, 59.159...
・Switching control circuit, 61.162...Data cell output terminal, 62.163...CLD cell output terminal, 63.8
4.132.168...(N-1)XM counter,
72...Check bit cell discard circuit, 76...VCI
Area restoration circuit, 78...Discarded cell restoration circuit, 80.1
33...Dummy cell detection circuit, 81.126...C
LD cell input terminal, 82.121...data cell input terminal, 83...(N-1)X(M-1) base counter,
101.164...input terminal, 103.129...
Data cell holding memory, 104...(M.p) encoder, 105...NX(M-p) base counter,
108...Inspection bit cell retention memo! J, 109...
・CLD cell data cell identification circuit, 123... Inspection bit cell discard circuit, 128... VCL area restoration circuit,
130.153...(M,p) decoder, 131...
Discarded cell restoration circuit, 182...CRPs1VCI extraction circuit, 210.210A...Transmission side device, 211.2
21...Terminal, 212-...Multiple conversion device, 213.
213A... Discard compensation encoding circuit, 220... Receiving side device, 222... Demultiplexing/converting device, 223.22
3A...Discard compensation decoding circuit.兇 - Iboshi example and 1 Father CLD 7 Ru 兇 - Implementation # 1 Small professional 1, 2 Ryo - Seibo example Dai block Ryo 7 times Ryo 8 picture 弗 - Banquet example Ditayaru #! 10th figure Di-Ta7al (N-1) 2nd turn of the year] Daipro, 2nd year: 15th figure y2 actual threat; 1 Yaru disposal detection cell Ryo 16th time Actual cell example Data cell inspection pit cell ¥) 18 figure child Goshosaibin] Small professional 1.7 Rikei Futami Koei j Large block Ryo 20 Kei Ryo 21 figure (part-time job) Asynchronous Akira L mo): M@'s cell Ryo 22 figure

Claims (1)

[Claims] 1. A transmitter device and a receiver device; the transmitter device includes a plurality of transmitter terminals and a multiplex converter that multiplexes and transmits cells or packets from the transmitter terminals. a cell transmitting/receiving device including a multiplexing/demultiplexing/converting device that separates the output signal of the multiplexing/converting device, and a plurality of receiving side terminals each receiving the output signal of the multiplexing/converting device; In the above, the transmitting side device includes a discard compensation encoding means that performs processing for cell discard detection and cell discard compensation on the output signal of the multiplex converter, encodes it, and transmits it to the receiving side, and the receiving side device includes the above A cell characterized in that it includes a discard compensation decoding means for detecting cell discard and compensating for cell discard on a signal obtained by receiving and decoding an output signal of a transmitting side device at a stage before the demultiplexing device and providing the signal to the demultiplexing and converting device. Transmitting/receiving device. 2. The discard compensation encoding means includes a transmission cell identification information extraction means for extracting transmission cell identification information from (an integer N of 2 or more - an integer q of 1 or more) data cells output from the multiplex conversion device; Cell discard detection cell generation means for generating q cell discard detection cells to which sequence numbers are added based on the output information of the transmitting cell identification information extraction means;
a cell discard detection cell adding means that adds to N-q) data cells and outputs them as a small block, and a set of (an integer M of 2 or more - an integer p of 1 or more) output by the data cell discard detection cell addition means. Enter a small block and (
M-p) sets of (N-q) data cells and q
Information bits (M-p) bits and check bits for part or all of the information of L sets of integers of 1 or more consisting of (M-p) bits recorded in the same bit position for a set of cell discard detection cells. Perform systematic encoding of p bits, insert the check bits generated by this systematic encoding into N sets of p cells to generate N sets of check bit cells each consisting of p cells, and then Test bit cell s_1
Insert a sequence number from the s_2nd bit to the s_2nd bit, and (M
2. The cell transmitting/receiving apparatus according to claim 1, further comprising: -p) test bit cell adding means for adding the test bit cells to the small blocks of the set and transmitting the test bit cells as a large block. 3. The discard compensation decoding means detects the discard of the cell discard detected cell based on the sequence number added to the received cell discard detected cell, and detects the discard of the cell discard detected cell based on the received cell discard detected cell compensation check bit. a cell discard detection cell restoration means for restoring a cell discarded detection cell; a reception cell identification information generating means for generating reception cell identification information for each of the received (M-p) small blocks; data cell discard detection for detecting data cell discard in a small block by comparing (N-q) pieces of transmitting cell identification information included in the cell discard detection cells with the receiving cell identification information of the receiving identification information generating means; means, a check bit detection means for checking the sequence number added to the check bit cell to detect its discard, and a cell set (M-p) of data cells having the same cell position within the small block ( For the set (M
- information bits (M-p) bits and check bits are decoded and discarded using M bits of information recorded in the same bit position of p) data cells and p check bit cells as a unit; The part other than the s_1st bit to s_2nd bit of the data cell is restored, the information recorded in the s_1st bit to s_2nd bit of the data cell is extracted from the cell discard detection cell, and the s_2nd bit of the data cell is restored.
2. The cell transmitting/receiving device according to claim 1, further comprising a discarded cell restoring means for restoring the original information by inserting the bit from the _1st bit to the s_2nd bit.