JPH04207524A - Clock signal variable device - Google Patents

Abstract

PURPOSE:To facilitate digital IC processing and miniaturization with less jitter by providing a reference clock generating circuit, a switch circuit, a frequency divider circuit, a counter circuit and a preset data output circuit on the variable device. CONSTITUTION:Since a control signal GS from a counter circuit 23 makes a switch circuit 22 nonconductive for a prescribed period decided by a preset data PSO, the switch circuit 22 extracts a prescribed number of reference clock signal pulses CKST. The degree of a change in the clock signal CKT outputted from the switch circuit 22 is adjusted depending on the extracted pulse number. Since the clock signal is changed without using a voltage controlled oscillator(VCO), jitter is reduced and digital IC processing and miniaturization are facilitated.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is applicable to electronic devices, such as data playback devices for CDs (compact discs) and DATs (digital audio tapes). , relates to a clock signal varying device for varying a clock signal.

(Prior Art) When making the playback speed adjustable in a data playback device such as a CD player, that is, when making the data output rate variable, a method is used that changes the frequency of a clock signal related to data processing. ing.

FIG. 6 shows a conventional device for this purpose. That is, the clock signal CKT to be varied is generated by a voltage controlled oscillator (hereinafter referred to as VCO) and is applied to a data processing circuit (not shown).

VCOII is controlled by the phase error signal output from phase comparator 12. This phase error signal is the reference clock signal CK output from the reference clock generation circuit 13.
It is generated by comparing the phases of ST and a frequency-divided clock signal CKN obtained by dividing the clock signal CRT by N by the program frequency divider 14. This configuration generally corresponds to a PLL circuit. By configuring such a PLL circuit, the poor frequency stability of VCOII is compensated for by synchronizing the phase with the stable reference clock signal CKST.

Here, the frequency division ratio 1/N of the program frequency divider] 4 is set by preset data from the preset data output circuit 15. As this preset data output circuit 15, a system controller in the data reproducing apparatus, for example, a microcomplexer, is used.

In such a configuration, when changing the clock signal CKT, the frequency division ratio of the program frequency divider ]4 is 1/N.
All you have to do is change. For example, if the reference clock signal CKST is 100 KHz, the division ratio of the program frequency divider 14 is 1.
/N is set to N -100. In this case, the frequency-divided clock signal CKN output from the program frequency divider 14 is 100.
KHz, and the clock signal CKT from VCO]1 is 1. It is controlled to be OMHz. Therefore, if the preset data output circuit 15 sets the frequency division ratio 1/N of the program frequency divider 14 to N - 101, the clock signal CRT becomes LO, LMHz, and N=9.
9, the clock signal CKT will be 9.9 MHz. In this way, by changing the frequency division ratio 1/N of the program frequency divider 14, the frequency of the clock signal CKT can be changed.

However, in the configuration of the conventional device described above, VColl
Although the jitter of the PLL circuit is suppressed to some extent by the PLL circuit, this is up to the frequency of the reference clock signal CKST input to the phase comparator 12, and jitter of frequency components higher than that can not be absorbed. Also,
Since it is a VCOII or analog circuit, it is a digital IC.
It is not suitable for miniaturization and is difficult to miniaturize.

(Problem to be solved by the invention) As mentioned above, in the conventional clock signal variable device, V
Due to the presence of CO, jitter cannot be improved, and furthermore, it is not suitable for digital ICs or miniaturization.

Therefore, the present invention has been made in consideration of the above circumstances.
It makes it possible to vary the frequency of the clock signal without using a vCO, has less jitter, and is compatible with digital ICs.
It is an object of the present invention to provide a clock signal variable device suitable for miniaturization and miniaturization.

[Structure of the Invention] (Means for Solving the Problems) A clock signal variable device of the present invention includes a reference clock generation circuit that outputs a reference clock signal, a switch circuit provided on the output signal line thereof, and a switch circuit. A frequency divider circuit divides the frequency of the conductive clock signal, and the preset timing is set based on the output of the frequency divider circuit, and a count operation is performed according to the reference clock signal, and the preset timing is set based on the value of the preset data that is variably set. The counter circuit includes a counter circuit that outputs a control signal that makes the switch circuit non-conductive during a period of counting up to a preset value, and a preset data output circuit that outputs preset data.

(Function) According to the above configuration, the control signal from the counter circuit or the switch circuit is made non-conductive for a predetermined period determined by the preset data, so that the switch circuit extracts a predetermined number of pulses of the reference clock signal. It will be done.

The degree of change in the clock signal output from the switch circuit is adjusted by the number of pulses extracted. In this way, since the clock signal is changed without using a vCO, jitter can be reduced, and furthermore, digital ICs and miniaturization can be facilitated.

In addition, since the extraction of the reference clock signal is synchronized with the output of the frequency dividing circuit, the frequency dividing circuit is By setting the frequency division ratio, it is possible to make the clock signal variable without affecting the data.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

In FIG. 1, the clock signal CKT is the reference clock signal CKST output from the reference clock generation circuit 21.
is obtained by passing it through the switch circuit 22. The switch circuit 22 controls the conduction/conduction of the reference clock signal CKST.
Non-conduction is controlled by a control signal GS from the counter circuit 23. By passing through this switch circuit 22, the clock signal CKT becomes the reference clock signal CKS.
A predetermined number of pulses are extracted from T.

The counter circuit 23 has a preset counter as described later, and inputs the reference clock signal CKST as a count clock, and also inputs the divided clock signal CKN output from the frequency dividing circuit 24 as a preset timing signal. . The frequency dividing circuit 24 divides the clock signal CKT at a predetermined frequency division ratio of 1/N.

Further, the preset value of the counter circuit 23 is set by preset data PSD from a preset data output circuit (microprocessor, etc.) 25.

Therefore, the counter circuit 23 uses the divided clock signal CK
When N is input, a preset is performed, and a control signal GS that makes the reference clock signal CKST non-conductive is output to the switch circuit 22, and this state is continued until the counter value reaches a predetermined value. Thereafter, a control signal GS that makes the reference clock signal CKST conductive is output to the switch circuit 22 until it is preset again.

Further, the frequency division ratio 1/N of the frequency dividing circuit 24 is the clock signal C
This is a value corresponding to the frequency of data processed using KT, and if it relates to processing of an audio signal, for example, a value proportional to an integer to the sampling frequency of the audio signal is selected.

Here, the case of a CD player will be explained as an example. C
The sampling frequency of the audio signal to be processed by the D-player is 44°IKI (z), and the commonly used clock signal CRT is 1.6.9344 MHz.

Therefore, the frequency division ratio 1/N of the frequency dividing circuit 24 is N-(16,9344XIO) / (44,1X10
3) It becomes -384, and it is an integral multiple of this. In other words,
N-384°192.12g, 96,...

Also, as the clock signal CKT, 33.8688 MH
If you use z, N-768, 3g4.2
5B, 192, . . . may be selected.

Next, the specific configuration of this embodiment will be explained with reference to FIG. 2. Here, the frequency division ratio 1/N of the frequency dividing circuit 24 is set to 1/B4 assuming that the present invention is applied to a CD player. In FIG. 2, a reference clock signal CKST output from a reference clock generation circuit 21 made of, for example, a crystal oscillator is applied to a terminal 31. The frequency of this reference clock signal CKST is 1.6.9344 Mtl
It is z. On the other hand, from the terminal 32, the clock signal CKT
is supplied to a data processing circuit (not shown). Frequency divider circuit 2
4, the counter 33 divides the clock signal CKT to a frequency of 1/384 and outputs the divided clock signal CKN.
Output as . Further, the AND gate 34 constituting the switch circuit 22 performs a digital switching operation based on the control signal GS.

The counter circuit 23 is configured as follows.

The frequency-divided clock signal CKN is input to one input terminal of the Nant gate 35 and the first flip-flop 36 . 1st
The output of the flip-flop 36 is input to the second flip-flop 37, and the output of the second flip-flop 37 is input to the other input terminal of the Nant gate 35. and,
A load signal LAD, which is a negative pulse, is generated from the Nant gate 35 at the rise of the frequency-divided clock signal CKN and is input to the up counter 38. This up counter 38 is a 4-bit binary counter, and is connected to terminals A and BSC for inputting preset data.
, D, a load terminal LD for presetting, an enable terminal T for inputting a signal GSN that controls prohibition of counting operation, and a terminal CO that outputs a carry-out signal CO when the count value reaches 15. are doing. The up counter 38 performs a counting operation by inputting the reference clock signal CKST as a clock. Further, the third flip-flop 39 receives the reference clock signal CKST as a clock input via the inverter 40, and receives the carry-out signal CO as the reference clock signal C.
It is latched and output at the rising edge of KST. The third flip-flop 39 outputs a control signal GS to the AND gate 34 and also outputs a reverse magnetic signal GSN to the up counter 38 as a count prohibition signal. Further, the fourth flip-flop 41 is connected to the preset data output circuit 25.
Input preset data PSD from terminals DA, DB, and DC1DD connected to terminals QA, QB, and QC at the rising edge of the divided clock signal CKN.
, QD and output to the up counter 38.

Next, the operation timing of the circuit configuration shown in FIG. 2 will be explained with reference to FIGS. 3 to 5. FIG. 3 is a timing chart when the preset data PSD is set to 13. In Figure 3, now up counter 3
The count value of 8] is 5, and the carry-out signal C
O is rHJ, the output signal G of the third flip-flop 39
SN or rLJ, and the enable terminal T of the up counter 38 is set to "L" and the counting operation is stopped. At this time, the control signal GS is rHJ, and the reference clock signal CKST is output as is as the clock signal CKT. Here, the counter 33 outputs the frequency-divided clock signal CKN or rHJ at the rising edge of pulse 1 of the clock signal CKT. When the divided clock signal CKN becomes rHJ, the rotor signal LAD
becomes rLJ, and the first and second flip-flops 36
．． By the operation in step 37, the load signal LAD returns to rHJ when the reference clock signal CKST falls twice.

When the load signal LAD becomes rLJ, the up counter 38 internally presets preset data PSD (13) at the fall of the reference clock signal CKST.

Therefore, since the count value becomes 13, the carry-out signal CO becomes rLJ. Then, in the third flip-flop 39, the signal GSN is inverted from rLJ to rHJ at the rise of the reference clock signal CKST. Further, the control signal GS is inverted from rHJ to rLJ, and the output of the AND gate 34, that is, the clock signal CKT, is fixed at rLJ.

Therefore, when the signal GSN becomes rHJ, the up counter 38 starts counting, and when the count value reaches 15, the carry-out signal becomes rHJ. Then, the signal GSN changes to rLJ, and the up counter 38
The counting operation stops when the count value remains at 15.

Further, since the control signal GS becomes rHJ, the reference clock signal CKST passes through the AND gate 34 as it is and becomes the clock signal CRT. Therefore, as shown in Figure 3,
A signal obtained by extracting pulses 3.4 from the reference clock signal CKST becomes the clock signal CKT.

In other words, if the preset data PSD is set to 13, the clock signal CKT will output 386 pulses in one cycle of the frequency-divided clock signal CKN instead of the original 386 pulses.
Only 84 pulses will be output.

Similarly, the preset data PSD is 1 in Figures 4 and 5.
Timing charts for cases 4 and 15 are shown. As shown in Figs. 3 to 5, preset data PSD or 384/38B in the case of PSD-13, P S
3847385 for D-14, P 5D-1
5, the clock signal CK at a ratio of 384/384
T can be varied.

As described above, 1. According to this embodiment, the frequency of the clock signal CKT can be made variable by extracting the pulses of the reference clock signal CKST without using a VCO. Therefore, since vCO is not used, the circuit configuration has extremely good frequency stability and little jitter. Moreover, since there are no analog circuits, it is easy to convert into a digital IC and is suitable for miniaturization.

Furthermore, since the timing of extracting the pulses of the reference clock signal CKST, that is, the frequency division ratio 1/N of the frequency dividing circuit 24, is synchronized with the sampling frequency of the audio signal, processing is performed using the generated clock signal CKT. However, the sound quality will not be compromised.

Note that the present invention is not limited to the above embodiments,
In addition, various modifications can be made without departing from the gist of the invention.

[Effects of the Invention] As detailed above, according to the present invention, the frequency of the clock signal can be varied without using a vCO, and the clock signal can be varied with less jitter and is suitable for digital ICs and miniaturization. equipment can be provided.

[Brief explanation of the drawing]

1 is a block configuration diagram showing an embodiment of a clock signal variable device according to the present invention, FIG. 2 is a circuit configuration diagram showing a specific configuration of the same embodiment, and FIGS. A timing chart for explaining the operation of the example, and FIG. 6 is a block diagram showing a conventional clock signal variable device. 21... Reference clock generation circuit 22... Switch circuit 23... Counter circuit 24... Frequency dividing circuit 25... Preset data output circuit

Claims (2)

[Claims] (1) A reference clock generation circuit that generates a reference clock signal; a switch circuit that receives the reference clock signal, conducts conduction/non-conduction of the reference clock signal, and outputs the conductive signal as a clock signal; and this switch. A frequency dividing circuit divides the clock signal outputted from the circuit by a predetermined frequency division ratio, and a preset timing is set based on the output of this frequency dividing circuit, and a counting operation is performed according to the reference clock signal. , a counter circuit that outputs a control signal that makes the reference clock signal non-conductive to the switch circuit during a period of counting from a variably set preset data value to a preset value; A clock signal variable device comprising: a preset data output circuit that outputs the preset data. (2) In the clock signal variable device according to claim 1,
A clock signal variable device characterized in that a frequency division ratio of the frequency dividing circuit is set in accordance with a sampling frequency of an audio signal processed according to the clock signal.