JPH04206742A - amplifier circuit - Google Patents

Abstract

PURPOSE:To obtain an amplification circuit with an improved sensitivity in a simple configuration by forming a film thickness of a gate insulating film of an amplification MOSFET constituting a source follower circuit which receives a voltage signal of a capacitor which receives a signal charge to be thicker than that of other gate insulating films which are formed on a same semiconductor substrate. CONSTITUTION:A title item is provided with a source follower circuit with a capacitor C3 which receives a signal charge, an amplification MOSFETQ2 which receives a voltage of the capacitor C3, and a loading means Q3 which is located at a source side of the amplification MOSFETQ2 and a film thickness of a gate insulating films 3 of the above amplification MOSFETQ2 is formed to be thicker than that of other gate insulating film 3' which is formed on a same semiconductor substrate 1. For example, in the above amplification MOSFETQ2, a gate electrode 4 is formed on a gate insulating film 3 which is formed relatively thickly. In other MOSFETQ1, Q3-Q5, a gate electrode 4' is formed on a gate insulating film 3' which is formed thinly by the half-etching technique with the above gate electrode 4 as a mask.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an amplifier circuit, and provides a technology that is effective when applied to, for example, an amplifier circuit that amplifies and outputs signal charges in a C0D (charge-coupled device) solid-state image sensor. It is related to.

[Conventional technology]

In a CCD solid-state image sensor, signal charges from the CCD are transferred to an output diffusion layer (structurally equivalently represented in the form of a diode).
and is converted into a signal voltage form by a capacitor consisting of its junction capacitance.

This signal voltage is applied to the amplification MOSFET and load MOSFET.
The signal is output via a source follower circuit consisting of an ET.

Such an amplifier circuit is called a floating diffusion layer amplifier (FDA;
Floating Diffusion Ampli
fier). When the signal voltage corresponding to the signal charge is amplified and output, the reset L-M03FET provided in the output diffusion layer is connected to the capacitor by a reset pulse before the next signal charge is transferred. The held signal charge is reset by a reference voltage.

Regarding such FDA, for example, see page 64 of ``rCCD Camera Technology'' published by Radio Gijutsusha on November 3, 1986.

[Problem to be solved by the invention]

The sensitivity of the above FDA is determined by the combined capacitance 1E (l!) consisting of the parasitic capacitance and output diffusion layer in the reset MOSFET and amplification MOSFET, and the gain (A) of the source follower circuit.
It is proportional to the product (As/C) of s<1).

There is a limit to the improvement of the gain AS, such as As<l, and improvement in FDA sensitivity depends on how small the combined capacitance value is. For this reason, in conventional FDA, an output diffusion layer and an amplification MOS are used to reduce the capacitance value.
A lot of effort is being put into how to make FETs etc. as small as possible. However, if the size of the amplifying MOS FET is reduced, the output power will also inevitably be reduced, which is a contradiction in terms, as the load driving capability of the subsequent stage will be lost.

An object of the present invention is to provide an amplifier circuit that achieves improved sensitivity with a simple configuration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the film thickness of the gate insulating film of the amplification MOSFET constituting the source follower circuit that receives the voltage signal of the capacitor receiving the signal charge is made thicker than that of other gate insulating films formed on the same semiconductor substrate.

[For production]

According to the above means, since the gate capacitance of the amplification MOSFET can be significantly reduced, the capacitance value of the detection capacitor can be reduced, and a large signal voltage can be obtained with respect to the transferred signal charge, so that high sensitivity can be achieved.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of an amplifier circuit used in a COD solid-state image sensor to which the present invention is applied. Each circuit element in the figure is formed on a single semiconductor substrate such as single crystal silicon along with other elements constituting the COD solid-state image sensor using known semiconductor integrated circuit manufacturing techniques.

Signal charges transferred through a COD transfer circuit as described below are transferred from an N layer formed on the surface of a P-type well region formed on a P-type semiconductor substrate (P-SUB) or an N-type semiconductor substrate. It is input to the output diffusion layer. This output diffusion layer N' is equivalently represented in the form of a diode by the P-type substrate or P-type well region, and the signal charge is held in its junction capacitance.

A voltage signal corresponding to the signal charge is outputted to the output diffusion layer N' through an amplifier circuit, and a reset MOSFET QI is connected to perform reset (sweeping out) before the next signal charge is transferred. This reset MOSF
ETQI is turned on by a reset pulse RG and applies a reset voltage RD to the output diffusion layer N''.

The output diffusion layer N+ is connected to the gate of the amplification MOSFET Q2. Amplification MOSFET Q2 is a depletion type MOS whose gate and source are grounded.
FETQ3 is provided as a load to constitute a source follower circuit.

The signal charge Q transferred through the above COD transfer circuit is
The PN junction capacitance C3 in the output diffusion layer N', the overlap capacitance C1 between the source and drain of the reset MOSFET Q2, and the gate capacitance C of the amplification MOSFET QI
3 combined capacitance C (C1+c2+C3), V=Q/
It is converted to a voltage of C.

In this way, the voltage signal of capacitor C is
Power is amplified by a source follower circuit consisting of TQ2 and load MOSFET Q3. The output signal of this first stage amplifier circuit is connected to the amplifier MOSFET Q4 and the same load MO5F as above.
The power is amplified by ETQ5 and output from the output terminal Vout.

As mentioned above, the detection capacitor C converts the signal charge into a voltage signal
By reducing the capacitance value, it is possible to obtain a voltage signal (2) larger than the equation of V=Q/C, and higher sensitivity can be achieved.

Therefore, in this embodiment, in order to reduce the gate capacitance C2 of the amplifying MOSFET Q2 connected to the output diffusion layer N', the film thickness of the gate insulating film is made thick. Thereby, the capacitance value of the gate input capacitor C2 can be significantly reduced in inverse proportion to the membrane pressure. Thereby, the input capacitance C2 can be reduced without extremely reducing the size of the amplification MOSFET Q2. As a result, the detection capacitance itC (C1 + C2 + C3) can be made smaller as the gate capacitance C2 is reduced, so from the voltage conversion formula V=Q/C, the detection capacitance C for the same signal charge Q can be reduced. The voltage V can be increased by the amount by which the capacitance value is reduced.

By the way, the capacitance value of C2 is 70% of the capacitance value of detection capacitor C.
, by simply increasing the film thickness of the gate insulating film from 350 to 1000 with the planar dimensions unchanged, C
The capacitance value of No. 2 can be reduced to about 30%. As a result, the capacitance value of the detection capacitor C is reduced by 50%, and the output voltage can be doubled even if the signal charge is the same. By connecting the source follower circuits in series, the output terminal has a large load driving capability, thereby enabling high-speed reading. As a result, it is possible to obtain, for example, a CCD solid-state image sensor that has both high sensitivity that compensates for the decrease in signal charge due to the increase in the number of pixels, and high-speed operation.

In FIGS. 2A to 2C, the amplification MOSFETQ
2 and another manufacturing process cross-sectional view of an embodiment of the manufacturing method of MOSFETQ4.

In FIG. 2A, after forming a thick field insulating film 2 in an element isolation region on a P-type semiconductor substrate (or a P-type well region formed on an N-type semiconductor substrate),
A thick gate insulating film 3 is formed in the element formation region. The film thickness of this gate insulating film 3 is the same as that of the amplification MOSFET mentioned above.
It is formed thickly corresponding to the gate insulating film of Q2. Then, on the gate insulating film in the element formation region where the MO5FETQ2 is to be formed, a polysilicon layer 4 constituting a gate electrode is formed using a photographic technique.

In FIG. 2B, the entire surface of the insulating film is half-etched using a controlled etching technique. In this case, the polysilicon layer 4 serves as a mask and the gate insulating film remains thick in the portion where the amplifying MO5FET Q2 is formed.

Therefore, the gate insulating film on the other element formation regions where the MO5FETQ4 etc. shown as a representative are formed becomes the gate insulating film 3' thinned by the above-mentioned half etching, and the gate electrode 4' is formed on top of the gate insulating film 3'. is formed by the same photographic technique as above.

In FIG. 2C, the gate electrode 4,4' and the field insulating film 2 are used as a mask to perform the ion implantation method.
Type impurities are introduced into the source.

A drain region 5 is formed and a polysilicon layer 4 is formed.
．． N-type impurities are also introduced into 4' to form a conductor layer.

In addition, the CCD transfer path may be configured or the amplification MOSFETQ
2. Although a step of forming wiring for Q4 is required, the explanation thereof will be omitted since it is not directly related to this invention.

In this manner, by adding a relatively simple manufacturing process, two types of MOSFETs having different gate insulating film thicknesses, such as MOSFETs Q2 and C4 in the above embodiment, can be formed.

FIG. 3 shows a schematic circuit configuration diagram of an embodiment of a CCD solid-state image sensor to which the present invention is applied.

In the figure, in order to facilitate understanding of the invention, photodiodes D1 to D4 consisting of a total of four photodiodes arranged in two rows and two columns are exemplarily shown as a representative. In practice, photodiodes are arranged in a matrix in a plurality of rows and columns to provide a total number of about 200,000 to about 400,000 photodiodes, as is known in the art.

The anode side of the photodiode DI is connected to the ground potential point of the circuit, and a photogate (hereinafter simply referred to as PG gate) is provided on the cathode side, and the photoelectrically converted signal charge is connected to the v1 of the vertical CCD (hereinafter referred to as VCCD). Transferred to gate. The other photodiode D2 in the same column is transferred to the 3 gate of VCCD via the PG gate. Photodiodes in other columns D3. Similarly to the above, D4 is also transferred to the corresponding VCCD via the PG gate.

The signal charge at the final stage of the VCCD is transferred to the horizontal CCD (hereinafter referred to as HC).
(referred to as a CD). The HCCD receives a transfer pulse H1,
A charge transfer operation is performed at high speed in synchronization with H2, and the signal charge is transmitted to the above-mentioned detection capacitor C that converts the signal charge into a voltage signal.

The OG provided at the output part of the HCCD is an output gate, and the signal charge of the HCCD is smoothly transferred to the detection capacitor C.
It acts to cause the transfer to. The signal charge is converted into a voltage signal by the detection capacitor C, and is amplified by the amplifier Amp having the circuit configuration shown in FIG.
Sent from ut. When the signal charge transferred to the detection capacitor C is outputted as a voltage signal through the amplifier Amp, it is reset pixel by pixel by the reset MOSFETQ, in other words, it is swept out. RG is a reset gate pulse and RD is a reset voltage.

An outline of the signal charge readout operation of this CCD solid-state image pickup device will be described below.

When the PC pulse is set to high level, the 1 gate and V3 gate of VCCD connected to the PC gate are set to high level. This causes the photodiodes Di, D2 (D
3. The photoelectric conversion charges of D4) are read out to the vl and v3 gates of the VCCD.

Next, for example, in an odd field, the V2 gate is set to high level. As a result, the signal charges under the Vl and V3 gates are mixed and once collected under the v2 gate. below,
At the next timing, the V3 gate is set to high level, and at the next timing, the V4 gate is set to high level, and the signal charge is transferred downward.

Hereinafter, each gate is set to a high level in the order of (1) to (v4), and the photoelectric conversion charge converted by the photodiode placed above it is transferred in the same manner as described above.

Further, in an even field, V4 is set to high level instead of the above-described 2 gate. As a result, the signal charges under the gates ``3'' and ``V1'' are mixed by one line and are once collected under the gate ``v4''. Thereafter, at the next timing, the gate (1) is set to high level, and at the next timing, gate (2) is set to high level, and the signal charge is transferred downward. In this way, by shifting the combination of signal charges by one row between the odd field and the even field, readout is equivalently performed in the increment manner.

The effects obtained from the above examples are as follows.

(1) By forming the gate insulating film of the first-stage amplification MOSFET that constitutes the source follower circuit that receives the voltage signal of the capacitor that receives the signal charge to be thicker than other gate insulating films formed on the same semiconductor substrate, As the gate capacitance of the first stage amplification MO5FET can be significantly reduced, the capacitance value of the detection capacitor that converts the signal charge into a voltage signal can be reduced, and the transferred signal charge is converted into a large signal voltage, resulting in higher sensitivity. You can get the effect of being able to

(2) As a method of increasing the film thickness of the gate insulating film of the first-stage amplification MOSFET, half-etching technology can be used to relatively easily create a MOSFET with two types of gate insulating films.
The effect of forming an OSFET can be obtained.

(3) By connecting multiple stages of source follower circuits in series and forming only the gate insulating film of the first-stage amplification MOSFET to be thick, it is possible to achieve the effects of increasing sensitivity and enabling high-speed readout.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples (although it is possible to make various changes without departing from the gist thereof). For example, in Fig. 1, the output signal of the first stage amplifier circuit is a source-grounded amplifier MOSFET.
It may be input to an ET and inverted and amplified. When an inverting amplifier circuit is provided in this way, it has a voltage gain, so it is possible to achieve even higher sensitivity. Also, 2nd B
In the figure, the thick gate insulating film in the other element formation region is completely removed and a thin gate insulating film 3 is added.
It may also form a As described above, a method of forming a MOS FET having two types of gate insulating films, in other words, a manufacturing method of forming only a thick gate insulating film of the amplifier MO5FETQ2 of the first stage source follower circuit employs various embodiments. It is something that can be done.

Furthermore, in the CCD solid-state image sensor shown in FIG.
The vertical COD can take various embodiments, such as one using a four-phase clock or one using a three-phase clock.

The amplifier circuit according to the present invention includes, in addition to a CCD solid-state image sensor constituting a line sensor or an area sensor, a photodiode that simply forms a signal charge according to the amount of received light, and an amplifier that amplifies the signal charge. It can also be used as a weak light monitor element or a light sensor element consisting of four circuits or the like. That is, the amplifier circuit according to the present invention can be widely used in circuits that amplify minute signal charges.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, the first stage amplification MOSF constitutes a source follower circuit that receives a voltage signal of a capacitor that receives signal charges.
By making the film thickness of the gate insulating film of the ET thicker than other gate insulating films formed on the same semiconductor substrate, the gate capacitance of the first stage amplification MOSFET can be significantly reduced, and signal charges can be converted into voltage signals. The capacitance value of the detection capacitor can be made small, and the transferred signal charge is converted into a large signal voltage, resulting in high sensitivity.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of an amplifier circuit according to the present invention, and FIGS. 2A to 2C are manufacturing steps for explaining an example of a method for manufacturing a MOS FET used in the above amplifier circuit. A cross-sectional view and FIG. 3 are schematic configuration diagrams showing one embodiment of a CCD solid-state image sensor to which the present invention is applied. C1-C5...MOSFET, C1-C3...capacitor, C...detection capacitance, P-3UB...substrate, N゛・
・Output diffusion layer, 1...substrate, 2...field insulating film,
3,3゛...Gate insulating film, 4゜4''...Gate electrode, 5...Source, drain, D1-D4...Photodiode, PG...Photogate, VCCD--Vertical CCD
, HCCD...Horizontal CCD, OG...Output gate, Amp...Amplification circuit.

Claims (1)

[Claims] 1. A capacitor that receives a signal charge, an amplification MOSFET that receives the voltage of this capacitor, and this amplification MOSFET
A source follower circuit is provided with a load means provided on the source side of the T, and the gate insulating film of the amplifying MOSFET is formed to have a film thickness thicker than other gate insulating films formed on the same semiconductor substrate. An amplifier circuit featuring: 2. The amplification MOSFET has a gate electrode formed on a relatively thick gate insulating film, and is connected to other MOSFETs.
2. The amplifier circuit according to claim 1, wherein the SFET has a gate electrode formed on a thin gate insulating film formed by a half-etching technique using the gate electrode as a mask. 3. Claim 1 or 2, characterized in that the source follower circuit is connected in series in a plurality of stages, and only the amplifying MOSFET in the first stage circuit has the thick gate insulating film. The amplifier circuit described.