[go: up one dir, main page]

JPH04206689A - Manufacture of multilayer printed wiring board - Google Patents

Manufacture of multilayer printed wiring board

Info

Publication number
JPH04206689A
JPH04206689A JP32978190A JP32978190A JPH04206689A JP H04206689 A JPH04206689 A JP H04206689A JP 32978190 A JP32978190 A JP 32978190A JP 32978190 A JP32978190 A JP 32978190A JP H04206689 A JPH04206689 A JP H04206689A
Authority
JP
Japan
Prior art keywords
hole
board
printed wiring
wiring board
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32978190A
Other languages
Japanese (ja)
Inventor
Kenichi Nakada
中田 研一
Fujio Tadokoro
田所 富士夫
Shin Kuramochi
蔵持 伸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP32978190A priority Critical patent/JPH04206689A/en
Publication of JPH04206689A publication Critical patent/JPH04206689A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To make it possible to align an outer layer pattern with both a via hole and a through hole and enhance the yield of a product by pasting a film with the via hole prior to the integration of laminated layers. CONSTITUTION:After a via hole 1 of IVH and a through hole 2 for an AC layer and an FB layer are bored and the through hole is plated, an inner layer circuit is formed and laminated layers are pressed. During this process, the IVH installed inside and outside a product where no circuit pattern is formed is pasted with release tape from the inner layer side. A print positioning guide 3 is installed to the outer layer which is located at a position, responding to the via hole 1. Printing is carried out monitoring the hole positions of the IVH of the guide 3 and the through hole 2. If the inside display of the guide 3 does not cover the through hole and the via hole 1 during this operation, the deviation of the pad against hole positioning will be absorbed within the specification.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、多層プリント配線板の製造方法に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a method for manufacturing a multilayer printed wiring board.

(従来の技術) 従来より、多層プリン1〜配線板の製造方法では、絶縁
板の両面に銅箔を貼り合わせた両面銅張積層板の両面を
接続する箇所に孔をあけ、その孔の内壁を金属化すると
ともに、一方の面に回路パターンを形成した基板を、予
め回路加工した内層回路板と絶縁層を交互に重ね合わせ
る。そうして、加熱・加圧して積層一体化した内層回路
板と、絶縁層を介して基板の回路面を内側にして、さら
に加熱・加圧して積層一体化した多層積層板に全体を貫
通する貫通孔をあけ、その貫通孔内を金属化した後、最
外層の回路形成をするようにしている。
(Prior art) Conventionally, in the manufacturing method of multilayer print 1 to wiring board, a hole is made at the location where both sides of a double-sided copper-clad laminate, in which copper foil is bonded to both sides of an insulating board, are connected, and the inner wall of the hole is A substrate with a circuit pattern formed on one side is alternately laminated with an inner layer circuit board on which a circuit has been processed in advance and an insulating layer. Then, the inner layer circuit board is laminated and integrated by heating and pressurizing, and the circuit surface of the board is turned inside through the insulating layer, and then the whole is penetrated into the multilayer laminate board, which is further heated and pressurized to integrate the layers. After drilling a through hole and metallizing the inside of the through hole, the outermost layer circuit is formed.

また、このとき、上記貫通孔に対してエツチングレジス
トのずれが小さくなるように貫通孔のみて外層のパター
ンの位置合わせを行なっている。
Further, at this time, the pattern of the outer layer is aligned using only the through holes so that the deviation of the etching resist with respect to the through holes is reduced.

(発明か解決しようとする課題) しかしながら、上述した従来の方法では、貫通孔のみで
外層のパターン位置合わせを行なっているため、バイア
ホールと外層バイアホールパッドのずれが生じ、プリン
ト配線板の製品の歩留りを悪化させるなどの問題点があ
った。
(Problem to be solved by the invention) However, in the conventional method described above, pattern alignment of the outer layer is performed only using the through holes, which causes misalignment between the via hole and the outer layer via hole pad, resulting in the product of the printed wiring board. There were problems such as deterioration of yield.

さらに、積層一体化したときの加熱・加圧により絶縁層
の樹脂が孔内へ流れ込み、次工程での貫通孔内壁の金属
化によって孔が塞がれてしまうため、バイアホールと外
層パターンとの位置合わせができない等の問題もあった
Furthermore, the resin of the insulating layer flows into the hole due to heating and pressure when the layers are integrated, and the hole is closed by metallization of the inner wall of the through hole in the next process, so the via hole and the outer layer pattern are There were also problems such as not being able to align the positions.

この発明は上述した問題点を解決するためになされたも
ので、バイアホールと貫通孔の両方に対して外層パター
ンの位置合わせができ、製品の歩留りの向上を図ること
のできる多層プリント配線板の製造方法を提供するもの
である。
This invention was made in order to solve the above-mentioned problems, and it is a multilayer printed wiring board that can align the outer layer pattern with respect to both via holes and through holes, and improve the product yield. A manufacturing method is provided.

(課題を解決するための手段) 上記目的を達成するため、この発明に係る多層プリント
配線板の製造方法は、絶縁板の両面に銅箔を貼り合わせ
た両面鋼張積層板の両面を接続する箇所に孔をあけ、そ
の孔の内壁を金属化し、−方の面に回路パターンを形成
した基板を、予め回路加工した1以上の内層回路板と絶
縁層を交互に重ね加熱・加圧し、積層一体化した内層回
路板と、上記絶縁層を介して基板の回路面を内側にして
、さらに加熱・加圧して積層一体化した多層積層板に全
体を貫通する貫通孔をあけ、その孔内を金属化し、最外
層の銅箔の必要でない箇所を選択的にエツチング除去し
て回路構成する多層プリント配線板の製造方法において
、 上記回路パターンが形成されない部分に、前記両面銅張
積層板に位置合わせ用の第1の孔を設け、上記内層回路
板と積層一体化する前に、その孔内に樹脂か侵入するの
を防止するために上記基板の孔の位置にフィルムを貼り
、積層一体化した後に、上記第1の孔の近傍に多層積層
板を貫通する第2の孔を設け、最外層の回路を構成する
際に用いるエツチングレジストを形成するときに、第1
の孔と第2の孔の両方に対してエツチングレジストのず
れが小さくなるように位置合わせ可能としたことを特徴
とする。
(Means for Solving the Problems) In order to achieve the above object, the method for manufacturing a multilayer printed wiring board according to the present invention connects both sides of a double-sided steel-clad laminate in which copper foil is bonded to both sides of an insulating board. Holes are drilled at the locations, the inner walls of the holes are metallized, and a circuit pattern is formed on the negative side of the board. One or more inner circuit boards with pre-processed circuits and an insulating layer are alternately layered and heated and pressurized to laminate the board. A through hole is made through the integrated inner layer circuit board and the multilayer laminate board, which is integrated by heating and pressurizing the integrated inner layer circuit board with the circuit surface of the board facing inside through the above insulating layer. In a method for manufacturing a multilayer printed wiring board in which a circuit is formed by metallizing and selectively etching away unnecessary parts of the outermost layer of copper foil, the part where the circuit pattern is not formed is aligned with the double-sided copper-clad laminate. A first hole was provided for the board, and before lamination and integration with the inner layer circuit board, a film was pasted on the hole position of the board to prevent resin from entering the hole, and the lamination was integrated. Later, a second hole penetrating the multilayer laminate is provided in the vicinity of the first hole, and when forming an etching resist to be used for configuring the circuit of the outermost layer, the first hole is formed.
The second hole is characterized in that it is possible to align the etching resist with respect to both the first hole and the second hole so that the deviation of the etching resist becomes small.

(作用) 上記のようにこの発明の製造方法によれば、積層一体化
する前にバイアホールにフィルムを貼ることにより、積
層一体止後でバイアホールの孔位置が確認できる。
(Function) As described above, according to the manufacturing method of the present invention, by pasting a film on the via hole before the lamination is completed, the position of the via hole can be confirmed after the lamination is completed.

したかって、バイアホールと貫通孔の両方に対して外層
パターンの位置合わせが可能になる。
Therefore, it is possible to align the outer layer pattern with respect to both the via hole and the through hole.

このように、製品外の部分にバイアホールを設けるとと
もに、多層プリント配線板として積層−体化する前に、
そのバイアホールの孔位置にフィルムを貼り、その孔内
に樹脂が侵入するのを防止するとともに、かつ、バイア
ホールと貫通孔の両方に対して外層パターンの位置合わ
せを可能にすることにより、製品の歩留りの向上が図ら
れるようになる。
In this way, in addition to providing via holes in the outside of the product, before laminating it into a multilayer printed wiring board,
By pasting a film on the hole position of the via hole to prevent resin from entering the hole, and making it possible to align the outer layer pattern with respect to both the via hole and the through hole, the product The yield will be improved.

(実施例) 以下、この発明に係る多層プリント配線板の製造方法の
一実施例を説明する。
(Example) Hereinafter, an example of the method for manufacturing a multilayer printed wiring board according to the present invention will be described.

なお、第1図はこの発明の使用状態を説明する平面図、
第2図はこの発明の製造方法における1態様を示す要部
断面図である。
Note that FIG. 1 is a plan view illustrating the state of use of this invention;
FIG. 2 is a sectional view of a main part showing one embodiment of the manufacturing method of the present invention.

第2図に示すように、この実施例の多層プリント配線板
の製造方法に使用される多層プリント配線板は、6層プ
リント配線板で構成されている。
As shown in FIG. 2, the multilayer printed wiring board used in the method of manufacturing a multilayer printed wiring board of this embodiment is composed of a six-layer printed wiring board.

この6層プリント配線板の信号層は4層、このうちAC
層およびFB層がそれぞれIVHにより導通ずるパター
ンに形成されている。
This 6-layer printed wiring board has 4 signal layers, of which AC
The FB layer and the FB layer are each formed in a pattern that is electrically conductive by IVH.

この際、製造工程は、まず始めにAC層およびFB層の
IVHのバイヤホール1および貫通孔2の孔あけをし、
スルーホールのめっきを行なった後、次に、内層(、C
−F層)の回路形成を行ない、積層プレスをすることに
なる。
At this time, the manufacturing process first involves drilling the IVH via holes 1 and through holes 2 in the AC layer and FB layer,
After plating the through holes, the inner layer (, C
-F layer) circuit formation will be performed and lamination pressing will be performed.

その際、回路パターンが形成されない製品内外に設けた
IVHを内層側から離型テープで貼っておく。
At this time, the IVH provided inside and outside the product, on which no circuit pattern is formed, is pasted with release tape from the inner layer side.

このバイヤホール1に相当する位置の外層には、第1図
で示すように、焼付位置合せカイト3か設けられている
In the outer layer at a position corresponding to the via hole 1, a printing alignment kite 3 is provided, as shown in FIG.

このガイド表示は、バイヤホール1と貫通孔2に対する
ずれを0.15mm以内に抑える寸法に構成されている
This guide display is configured to have dimensions that suppress the deviation between the via hole 1 and the through hole 2 to within 0.15 mm.

したがって、プレスした後は、貫通孔2の孔あけおよび
スルーホールめっきを経て外層焼付となる。
Therefore, after pressing, the outer layer is baked after drilling the through holes 2 and plating the through holes.

ここで、焼付位置合せガイド3のIVHと貫通孔2およ
びバイヤホール1の孔位置を見ながら焼付を行なう。
Here, the printing is performed while observing the IVH of the printing positioning guide 3 and the hole positions of the through holes 2 and via holes 1.

そして、このとき、焼付位置合せガイド3の内側表示が
貫通孔2およびバイアホール1にかかっていなければ孔
位置法めに対するパッドのすれは仕様内におさまってい
ることになる。
At this time, if the inner markings of the printing positioning guide 3 do not cover the through hole 2 and the via hole 1, it means that the slippage of the pad with respect to the hole position is within the specifications.

なお、外層焼付以降はエツチング、レジスト焼付、外形
加工を経て製品は完成となる。
After baking the outer layer, the product is completed through etching, resist baking, and external processing.

(発明の効果) 以上述べてきた構成より明らかなように、この発明の製
造方法によれば、外層回路を形成する際に、バイアホー
ルと貫通孔の両方に対してパターンのずれを小さくする
ことができるように位置合わせか可能に構成されている
ため、回路パターンが形成されない製品外の部分にバイ
アホールを設けるとともに、多層のプリント配線板とし
て積層一体止する前に、そのバイアホールの孔の位置に
フィルムを貼り、その孔内に樹脂が侵入するのを防止す
るようにし、かつ、バイアホールと貫通孔の両方に対し
て外層パターンの位置合わせを可能にすることにより、
製品歩留りの向上が図れるようになる等の効果を有する
(Effects of the Invention) As is clear from the configuration described above, according to the manufacturing method of the present invention, when forming an outer layer circuit, it is possible to reduce pattern deviation for both via holes and through holes. Because the structure allows for positioning so that the circuit pattern is not formed, via holes are provided outside the product, and the holes of the via holes are carefully aligned before being laminated together as a multilayer printed wiring board. By applying a film to the position to prevent resin from entering the hole, and by allowing alignment of the outer layer pattern with respect to both the via hole and the through hole,
This has effects such as improving product yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は焼付位置合わせのガイドの平面図であり、第2
図はこの発明の製造方法における多層プリント配線板の
層構成を示した断面図である。 1・・・バイアホール 2・・・貫通孔 3・・・焼付位置合せガイド 第2図
Fig. 1 is a plan view of the guide for printing position alignment;
The figure is a sectional view showing the layer structure of a multilayer printed wiring board in the manufacturing method of the present invention. 1... Via hole 2... Through hole 3... Seizing positioning guide Figure 2

Claims (1)

【特許請求の範囲】[Claims] 1.絶縁板の両面に銅箔を貼り合わせた両面銅張積層板
の両面を接続する箇所に孔をあけ、その孔の内壁を金属
化し、一方の面に回路パターンを形成した基板を、予め
回路加工した1以上の内層回路板と絶縁層を交互に重ね
加熱・加圧し、積層一体化した内層回路板と、 上記絶縁層を介して基板の回路面を内側にして、さらに
加熱・加圧して積層一体化した多層積層板に全体を貫通
する貫通孔をあけ、その孔内を金属化し、最外層の銅箔
の必要でない箇所を選択的にエッチング除去して回路構
成する多層プリント配線板の製造方法において、 上記回路パターンが形成されない部分に、前記両面銅張
積層板に位置合わせ用の第1の孔を設け、上記内層回路
板と積層一体化する前に、その孔内に樹脂が侵入するの
を防止するために上記基板の孔の位置にフィルムを貼り
、積層一体化した後に、上記第1の孔の近傍に多層積層
板を貫通する第2の孔を設け、最外層の回路を構成する
際に用いるエッチングレジストを形成するときに、第1
の孔と第2の孔の両方に対してエッチングレジストのず
れが小さくなるように位置合わせ可能としたことを特徴
とする多層プリント配線板の製造方法。
1. A hole is drilled at the point where both sides of the double-sided copper-clad laminate are to be connected, with copper foil pasted on both sides of the insulating board, the inner wall of the hole is metallized, and a circuit pattern is formed on one side of the board. One or more inner layer circuit boards and insulating layers are alternately stacked and heated and pressurized to form an integrated laminated inner layer circuit board. A method for manufacturing a multilayer printed wiring board, in which a through hole is formed through an integrated multilayer laminate, the inside of the hole is metallized, and unnecessary parts of the outermost layer of copper foil are selectively etched away to form a circuit. In this step, a first hole for positioning is provided in the double-sided copper-clad laminate in a portion where the circuit pattern is not formed, and resin is prevented from entering the hole before laminating and integrating with the inner layer circuit board. In order to prevent this, a film is pasted on the hole position of the substrate, and after the lamination is integrated, a second hole is provided near the first hole to penetrate the multilayer laminate to form the outermost layer circuit. When forming the etching resist to be used in the process, the first
A method for manufacturing a multilayer printed wiring board, characterized in that the etching resist can be aligned with respect to both the first hole and the second hole so that the deviation of the etching resist is reduced.
JP32978190A 1990-11-30 1990-11-30 Manufacture of multilayer printed wiring board Pending JPH04206689A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32978190A JPH04206689A (en) 1990-11-30 1990-11-30 Manufacture of multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32978190A JPH04206689A (en) 1990-11-30 1990-11-30 Manufacture of multilayer printed wiring board

Publications (1)

Publication Number Publication Date
JPH04206689A true JPH04206689A (en) 1992-07-28

Family

ID=18225196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32978190A Pending JPH04206689A (en) 1990-11-30 1990-11-30 Manufacture of multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JPH04206689A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07162158A (en) * 1993-12-03 1995-06-23 Nec Corp Manufacture of printed wiring board
US6529179B1 (en) * 1998-07-31 2003-03-04 Kabushiki Kaisha Toshiba Flat panel display unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07162158A (en) * 1993-12-03 1995-06-23 Nec Corp Manufacture of printed wiring board
US6529179B1 (en) * 1998-07-31 2003-03-04 Kabushiki Kaisha Toshiba Flat panel display unit

Similar Documents

Publication Publication Date Title
KR20010056624A (en) Multi-layer pcb and the manufacturing method the same
JP4043115B2 (en) Multi-layer printed wiring board
JP4206545B2 (en) Manufacturing method of multilayer printed wiring board
JPH04206689A (en) Manufacture of multilayer printed wiring board
JP2005116811A (en) Multilayer wiring circuit board and method for manufacturing the same
JP2001326469A (en) Printed wiring board and method of manufacturing the same
JPH0637515A (en) Printed wiring board
JPH06164148A (en) Multilayer printed wiring board
JPH04168794A (en) Manufacture of multilayer printed-circuit board
JPH07221460A (en) Method for manufacturing multilayer printed wiring board
JPH01140698A (en) Manufacture of multi-layered printed circuit board
JPS6247199A (en) Manufacture of inner layer circuit board for multilayer circuit board
JPH0590762A (en) Manufacture of multilayer printed wiring board
JP2005109299A (en) Multilayer wiring board and its manufacturing method
JPS63137499A (en) Manufacture of multilayer printed interconnection board
JP2001144445A (en) Method for producing multilayer printed wiring board
JP2002344140A (en) Method of manufacturing laminated ceramic electronic component
JPH0545079B2 (en)
JPH09199855A (en) Manufacture of multilayer interconnection board
JPH03194998A (en) Manufacture of multilayer circuit board
JPH0870183A (en) Manufacture of multilayer printed-wiring board
CN117202542A (en) Manufacturing method of rigid-flex printed circuit board with built-in inner finger bonding pad
JPH05299844A (en) Multilayer printed wiring board and manufacturing method thereof
JPH05299838A (en) Manufacture of multilayer wiring board
JPH0428292A (en) Manufacture of multilayer printed wiring board