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JPH04205783A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPH04205783A
JPH04205783A JP2335370A JP33537090A JPH04205783A JP H04205783 A JPH04205783 A JP H04205783A JP 2335370 A JP2335370 A JP 2335370A JP 33537090 A JP33537090 A JP 33537090A JP H04205783 A JPH04205783 A JP H04205783A
Authority
JP
Japan
Prior art keywords
semiconductor memory
vbb
power consumption
memory device
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2335370A
Other languages
Japanese (ja)
Inventor
Tetsuo Kato
哲夫 加藤
Hideyuki Ozaki
尾崎 英之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2335370A priority Critical patent/JPH04205783A/en
Publication of JPH04205783A publication Critical patent/JPH04205783A/en
Pending legal-status Critical Current

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Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To offer a semiconductor memory whose power consumption is low by impressing voltage on a VBB by using a solar battery from the outside only in the case of standby. CONSTITUTION:A VBB terminal 2 is led out of a package 4 and the voltage is impressed on the VBB terminal 2 by using the solar battery when the semiconductor memory is in the standby state. Thus, a DRAM whose power consumption is low is offered.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体記憶装置に関し、特に低消費電力型
のDRAMに関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a low power consumption type DRAM.

〔従来の技術〕[Conventional technology]

第3図は従来のIMDRAMのDIRのピン配置図であ
る。
FIG. 3 is a pin layout diagram of DIR of a conventional IMDRAM.

図において、(6)はDIRパッケージ概略図であり、
左上が1ピンである。(7)はピンの名称である。VB
B端子は存在しないため、デバイス内部で発生させてい
た。
In the figure, (6) is a schematic diagram of the DIR package,
The top left is pin 1. (7) is the name of the pin. VB
Since the B terminal does not exist, it was generated inside the device.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体記憶装置は以上のように構成されているの
で、動作時には、多くの電流を消費していた。
Since the conventional semiconductor memory device is configured as described above, it consumes a large amount of current during operation.

近年、ノートサイズパソコン等の普及で消費電力の小さ
いDRAMが必要となる。
In recent years, with the spread of notebook-sized personal computers and the like, DRAMs with low power consumption have become necessary.

従って、VBBを内部で発生させる半導体記憶装置は、
実用上、何らかの改善を必要とする問題点があった。
Therefore, a semiconductor memory device that generates VBB internally is
In practice, there were problems that required some kind of improvement.

この発明は、−F記のような問題点を解決するためにな
されたものてあり、消費電力の小さい半導体記憶装置を
提供することを目的とする。
This invention has been made to solve the problems mentioned in -F, and it is an object of the invention to provide a semiconductor memory device with low power consumption.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置は、パッケージよりVBB端
子を出して、スタンバイ状態(RAS信号、CAS信号
クロックが旧gh状態)にある時は、太陽電池によって
VBB端子に電圧を印加するものである。
In the semiconductor device according to the present invention, the VBB terminal is taken out from the package, and when in the standby state (RAS signal and CAS signal clock are in the old gh state), a voltage is applied to the VBB terminal by a solar cell.

〔作用〕[Effect]

この発明における半導体記憶装置は、 DRAMがスタンバイ状態にある時、外部よりVBBに
電圧を印加することによって、消費電力が小さくなる。
In the semiconductor memory device according to the present invention, power consumption is reduced by applying a voltage to VBB from the outside when the DRAM is in a standby state.

(実施例〕 以下、この発明を図に基づいて説明する。(Example〕 Hereinafter, this invention will be explained based on the drawings.

第1図はこの発明の一実施例による半導体記憶装置を示
す概略図である。
FIG. 1 is a schematic diagram showing a semiconductor memory device according to an embodiment of the present invention.

図において、(1)は太陽電池、(2)はVBB端子、
(3)は他の信号端子、(4)はパッケージである。
In the figure, (1) is a solar cell, (2) is a VBB terminal,
(3) is another signal terminal, and (4) is a package.

パッケージよりVBB端子(2)を出して、太陽電池(
1)を用いて半導体記憶装置がスタンバイ状態にある時
にVBB端子に電圧を印加する。
Take out the VBB terminal (2) from the package and connect the solar cell (
1) is used to apply a voltage to the VBB terminal when the semiconductor memory device is in a standby state.

なお、上記実施例では太陽電池(1)を用いたが、電圧
源としては第2図に示すようにリチウム2次電池等を用
いても良い。この場合、並列に太陽電池を用いることに
よってリチウム2次電池(5)を充電する。又、パッケ
ージはDIR以外でも用いることができる。
In addition, although the solar cell (1) was used in the above embodiment, a lithium secondary battery or the like may be used as the voltage source as shown in FIG. In this case, the lithium secondary battery (5) is charged by using solar cells in parallel. Also, the package can be used for things other than DIR.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、DRAMのスタンバ
イ状態において、VBB端子に太陽電池を用いることに
よって、低消費電力のDRAMを提供することができる
効果がある。
As described above, according to the present invention, by using a solar cell for the VBB terminal in the standby state of the DRAM, it is possible to provide a DRAM with low power consumption.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による半導体記憶装置を示
す概略図、第2図はこの発明の他の実施例による半導体
記憶装置を示す概略図、第3図は従来のIMDRAMの
DIRのピン配置図である。 図において、(1)は太陽電池、(2)はVBB端子、
(3)は他の信号端子、(4)はパッケージ、(5)は
リチウム2次電池、(6)はDIPパッケージ概略図、
(7)はピンの名称である。 なお、図中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a schematic diagram showing a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a schematic diagram showing a semiconductor memory device according to another embodiment of the invention, and FIG. 3 is a schematic diagram showing a DIR pin of a conventional IMDRAM. It is a layout diagram. In the figure, (1) is a solar cell, (2) is a VBB terminal,
(3) is another signal terminal, (4) is a package, (5) is a lithium secondary battery, (6) is a schematic diagram of a DIP package,
(7) is the name of the pin. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] デバイスにVBB端子を備え、スタンバイ時のみに外部
より太陽電池でVBBを印加することを特徴とする半導
体記憶装置。
A semiconductor memory device characterized in that the device is equipped with a VBB terminal, and VBB is externally applied by a solar cell only during standby.
JP2335370A 1990-11-28 1990-11-28 Semiconductor memory Pending JPH04205783A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2335370A JPH04205783A (en) 1990-11-28 1990-11-28 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2335370A JPH04205783A (en) 1990-11-28 1990-11-28 Semiconductor memory

Publications (1)

Publication Number Publication Date
JPH04205783A true JPH04205783A (en) 1992-07-27

Family

ID=18287777

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2335370A Pending JPH04205783A (en) 1990-11-28 1990-11-28 Semiconductor memory

Country Status (1)

Country Link
JP (1) JPH04205783A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017097946A (en) * 2011-06-10 2017-06-01 株式会社半導体エネルギー研究所 Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017097946A (en) * 2011-06-10 2017-06-01 株式会社半導体エネルギー研究所 Semiconductor device

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