JPH04205237A - Memory access system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access method, and particularly to a memory access method used in a multiprocessor system.

[Prior Art] Conventionally, a multiprocessor system (hereinafter referred to as a system) has a configuration that has a shared memory that is accessed by all processors, and a unique memory attached to each processor in addition to the shared memory to improve processing efficiency. A configuration with memory was common. This shared memory has a configuration in which all memory is centrally located in one storage device, a configuration in which the shared memory is distributed in a plurality of storage devices to correspond to each processor, and an intermediate form thereof.

[Problems to be Solved by the Invention] However, in systems with a configuration in which shared memory is centrally allocated, memory access contention from multiple processors occurs, resulting in a problem that processing efficiency decreases due to bus necks or memory necks. was. To solve this problem, a system is used in which a unique memory attached to each processor is added, but this unique memory cannot be accessed by other processors. Therefore, there was a problem in that shared data could not be stored in private memory. If shared data is stored in a unique memory, inter-processor communication must be performed frequently in order to maintain consistency with shared data that may exist in unique memories attached to other processors. This creates another problem: extra load on the system.

Furthermore, in the case of a configuration in which shared memory is distributed, a processor and memory are paired as a unit (hereinafter referred to as PU).
In many cases, each PU has a core unit number (hereinafter referred to as
The shared memory address of the system was determined from the PU-ID and the memory address within the PU to avoid memory address conflicts between PUs. In other words, when the system is started, memory is allocated according to the system configuration so that the address of the shared memory becomes a common address for the entire system.

-However, in such a system configuration, e.g.
In the case of an 8PU system, a failure of the IPU causes a gap in the physical memory space, which has the disadvantage that the system must be reconfigured or restarted.

The present invention has been made in view of the above conventional example, and an object of the present invention is to provide a memory access method that enables access to memory dedicated to each processor in a multiprocessor system.

[Means for Solving the Problems] In order to achieve the above object, the memory access method of the present invention has the following configuration. That is, in a multiprocessor system, a storage means attached to each of the plurality of processors, an information transmission means used as a path for exchanging information between the plurality of processors, and a storage means attached to each of the plurality of processors. a first address conversion means for converting a storage address in order for one of the plurality of processors to access the storage means attached to another processor; a second address conversion means for converting a storage address in order to allow access from another processor to the storage means attached to one of the processors; A control means is provided for controlling access to the storage means from a processor to which the storage means belongs and from other processors.

[Operation] With the above configuration, the present invention can convert a first address conversion means possessed by a processor, an information transmission means connecting the processors, and a second address possessed by another processor having a storage means desired to be accessed. It operates to access the storage means of other processors through the conversion means.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a multiprocessor system that is a typical embodiment of the present invention. In FIG. 1, 1 is a shared memory accessed by each processor, 2 is a common bus to which each processor unit (hereinafter referred to as PU), the shared memory 1, an I10 system (not shown), etc. are connected, and 3a to 3b, etc. are It is PU. Also, each PU is
CPU 4, cache memory (hereinafter referred to as cache) 5, translation lookaside buffer (hereinafter referred to as TLB) 6, page map ii which converts addresses from virtual addresses to internal memory addresses (hereinafter referred to as internal addresses), virtual addresses to system A page map ie8 that converts a common intermediate address, a page map ei9 that converts a system common intermediate address to an internal address, and an avita 10 that arbitrates between memory accesses generated by requests from within the PU and memory accesses generated by external requests. , a unique memory 11 that can be referenced from other PUs.

It is also assumed that the cache 5 includes units necessary to configure a cache system, such as a cache tag and a comparator. In this embodiment, cache 5
is configured to be externally attached to the CPU 4, but a CPU with a built-in cache may also be used.

Now, the virtual address issued from CPU4 is given to cache 5, TLB6, page map ii7, and page map ie8.Next, the virtual address issued from CPU4 is checked to see if it hits cache 5 first or not. 5. cache 5
When a hit occurs, address translation in the TLB 6, page map ii 7, and page map ie 8 is stopped, and the hit data is transferred to the CPU 4, and at the time of a write hit, information according to the cache coherence protocol is transmitted to the common bus 2.

On the other hand, if there is no cache hit in the cache 5, the TLB 6 that holds the internal address determines whether the virtual address exists in the specific memory 11. Determine whether TL here
If there is an entry corresponding to the virtual address in B6, the virtual address is converted into an internal address in TLB6 and given to the private memory 11 via the arbiter 10.

At this time, the page map ii7 is simultaneously notified of this and address conversion to an internal address is prohibited. moreover,
The same notification is transmitted to the page map ie8, and address translation by the page map ie8 is prohibited.

If there is no entry for the virtual address in the TLB6 entry, address translation is performed using page map ii7. The conversion may be executed in hardware by a memory management unit (MMU) or in software via the CPU 4.

FIG. 2 is a diagram showing the state of address mapping in this embodiment. In Figure 2, the virtual space is assumed to be mapped based on a 24-bit addressing architecture. In Figure 2, from the left, the virtual space of the process running on the PU (3a), the internal space of the PU (3a) (address space of specific memory 11), intermediate real space, PU (3
b) shows the address mapping of the internal space (the address space of the unique memory of PU (3b)) and the real space of the shared memory 1. According to Figure 2, PU (3a
), the part of the virtual space address of the running process is indicated by the arrow group a in the private memory 11 of the PU (3a).
It is shown that it is mapped to the internal space corresponding to . Here, the arrow group a indicates that address translation is being performed between the virtual space and the internal space via the TLB 6 or page map ii7.

The page map ie8 maps the virtual space of the process currently being executed by the CPU 4 to an intermediate real space common to the entire system. The specific memory in each PU, the shared memory 1, and the I10 space of the I10 system (not shown) are mapped on the intermediate real space. As shown by the arrow group in FIG. 2, the virtual space address and other spaces of the process running on the PU (3a) are
Due to the effect of e8, addresses are mapped as continuous addresses in the intermediate real space.

If the virtual address issued by the CPU 4 does not exist in the specific memory 11 in this way, the virtual address is converted to an address on the intermediate real space through the page map IE 8, and only then is the intermediate real address sent to the common bus 2 outside the PU 3. is output.

Now, the intermediate real address output to the common bus 2 is taken in by the shared memory 1 or another PU. This is shown by arrow group C and arrow d in FIG. Here, the arrow group C indicates that the intermediate real space is each PU (here, PU
3a to 3b) are mapped to the specific memory by the action of page map ei9. Also, the arrow d is
This shows that the real space address of the shared memory 1 is set to have the same address as the intermediate real space address.

First, a case will be described in which the shared memory 1 has an area corresponding to the address.

The virtual address generated by the CPU 4 is converted into an intermediate real space address by the page map ie 8 so that the shared memory 1 in the intermediate real space indicates a defined area of the mapped space. The intermediate real space address is provided to the shared memory 1 via the common bus 2.

Next, consider a case where an area corresponding to the virtual space address exists in the private memory of another PU (in this case, PU (3b)).

The unique memory 11 of PU (3b) is mapped onto the intermediate real space by the page map ei included in PU (3b), similarly to the unique memory 11 of PU (3a).

So, PU (3a) page map ie8
An address mapped in the intermediate real space by the page map ei in (3b) is prepared (In this state, the virtual address generated from the CPU 4 is mapped by the PU (3b) in the intermediate real space. The address is converted into an intermediate real space address by the page map ie8 of the PU (3a) so as to indicate a defined area of the space.The intermediate real space address is supplied to the PU (3b) via the common bus 2.On the other hand, , PU (3b) In the page map ei, the intermediate real space address is converted to an internal address of PU (3b) and given to the specific memory.In this way, PU (3a)
The private memory of PU (3b) can be accessed by using the virtual address issued by PU (3a) through page map ie8 of PU (3a) and page map ei of PU (3b).

As explained above, the specific memory 11 is accessed through three routes: TLB6, page map ii7, and page map ei9. However, accesses from TLB6 and page map ii7 occur exclusively, so TLB
6 or page map ii7, and an access route from the outside via page map and ei9.

In this embodiment, the arbiter 10 is used to give priority to accesses from inside the PU, and even if an external access is in progress, immediately after the end of that cycle, an internal access is interrupted and executed with priority. , the access priority to the private memory is controlled so that external access is resumed after the internal access operation is completed.

Therefore, according to this embodiment, an address indicating a defined area of the space where shared memory 1 is mapped, and PU (3
The address indicating the intermediate real space to which the specific memory (not shown) of b) is mapped is mapped to the page map of PU (3a).
By preparing for CPU 8, CPU 4 of PU (3a)
Shared memory 1 and PU (3b
) can access its own memory. moreover,
By giving priority to accesses from the own processor to the specific memory over accesses from other processors, it is possible to prevent a decrease in processing efficiency within the own processor.

[Other Embodiments] In the above embodiment, the shared memory is mapped to the same address as the intermediate real space, and only the base address of each area is shifted to convert the address from the intermediate real space to the internal space of each PU. Each area itself has been described as being mapped as a continuous address space. In this embodiment, by placing another page map between the shared memory and the common bus, the intermediate real space is handled in predetermined small processing units (hereinafter referred to as pages), and each unit is An example of mapping an arbitrary intermediate real space to the real space of the shared memory or the internal space of each PU will be described.

Note that this embodiment uses a device having the same configuration as the memory access device used in the previous embodiment, except that another page map is provided between the shared memory and the common bus.
The same device reference numbers as in FIG. 1 are used, and descriptions of the various parts of the device common to the previous embodiments are omitted.

FIG. 3 is a diagram showing the configuration of the shared memory 12 used in this embodiment, in which a page map em13 is provided between the memory section 14 and the common bus 2. This page map e+n1
3, the intermediate real address on the common bus 2 is assigned to the memory section 1.
4 is converted into an internal address of the memory unit 14 in order to access it.

FIG. 4 is a diagram showing address space mapping in this embodiment. Using FIG. 4, when a process running on the PU (3a) accesses the shared memory 12,
The case of accessing the specific memory of PU (3b) will be explained.

First, the page of the virtual space of the process being executed on the PU (3a) is address-converted by the page map ie8 to the area of intermediate real space addresses C0 to Cmax. Next, the intermediate real space address is converted into an internal address of the memory section 14 by the page map em13 inside the shared memory 12. At this time, the internal address conversion to the memory unit 14 is executed in page units, so if consecutive addresses exist in the memory unit 14 in page size units, the address conversion is executed normally. Therefore, even if shared memory 1
Even if a part of the shared memory is inaccessible due to a failure (the part indicated by [xxxx] in the real space of the shared memory in Figure 4),
It is possible to map intermediate real space without using it.

Next, the case of accessing the private memory of PU (3b) will be described.

First, the address of a page (SA) of a part of the text of the process being executed on the PU (3a) shown in Figure 4 is converted into an address of an area (SC) in the intermediate real space by address conversion using page map IE8. be done. Next, PU (3
The page map ei in b) is mapped to a certain area (SB) of the specific memory of the PU (3b). In this embodiment, some pages of the process running on PU (3a),
In particular, by mapping the common area for process execution to the internal space of each PU (3a and 3b) as shown in the shaded area shown in FIG. 4, the internal memory capable of high-speed response is utilized.

Therefore, according to this embodiment, even if a part of the shared memory 1 has a fault and is unusable, the intermediate real space can be mapped without using the faulty part, so that it is possible to map the intermediate real space without using the faulty part. System down can be prevented. Furthermore, since the unique memory of other PUs can be accessed on a page-by-page basis, efficient use of memory resources is possible.

Note that in the above two embodiments, a case has been described in which access to the specific memory from within the PU is prioritized over access from the outside, but the present invention is not limited to this. For example, PU with unique memory access priority
It is also possible to perform dynamic control in consideration of each load balance.

In other words, if process A, which cannot be divided, is executed by only one PU in a multiprocessor system, only the load on the PU that executes that process will increase, and the other PUs will be required to maintain the system. Small loads, e.g.
This is only due to clocks, network management, etc.

For this reason, internal cPs to specific memory attached to other PUs
Since the access frequency from U decreases, its own memory is allocated for the execution of process A. Under these conditions, in order to increase the processing efficiency of process A, the access priority of the specific memory of other PUs is set to external Dynamically control to prioritize access. As a result, processes that require a large amount of memory can be operated efficiently, and memory resources can be used effectively.

[Effects of the Invention] As described above, according to the present invention, in a multiprocessor system, a unique memory dedicated to each processor can be accessed from other processors, so that memory usage efficiency is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a multiprocessor system that is a typical embodiment of the present invention, FIG. 2 is a diagram showing address space mapping, and FIG. 3 is a diagram showing the configuration of a shared memory according to another embodiment. FIG. 4 is a block diagram illustrating address space mapping according to another embodiment. In the figure, 1...shared memory, 2...shared bus, 3a. 3b... Processor unit, 4... CPU, 5.
...Cache memory, 6...TLB, 7...Page map ii, 8...Page map ie, 9...
Page map ei, 10... arbiter, 11... private memory, 13... page map em. Patent applicant Canon Co., Ltd.

Claims (3)

[Claims] (1) In a multiprocessor system, a storage means attached to each of the plurality of processors, an information transmission means used as a path for exchanging information between the plurality of processors, and a storage means attached to each of the plurality of processors; , a first address conversion means for converting a storage address in order for one of the plurality of processors to access the storage means attached to another processor; a second address translation means for converting a storage address in order to allow another processor to access the storage means attached to one of the plurality of processors; and for each of the plurality of processors, the storage means 1. A memory access system comprising: control means for controlling access from a processor to which the storage means belongs and access from other processors to the storage means. (2) The control means controls the storage means so that accesses from a processor to which the storage means belongs are given priority to accesses from other processors. Memory access method. (3) The control means dynamically controls the priority of accesses to the storage means from the processor to which the storage means belongs and accesses from other processors, depending on the load of the entire multiprocessor system. The memory access method according to claim 1, characterized in that: