JPH04205133A - disk controller - Google Patents

Abstract

PURPOSE:To improve the reliability of handled data and the whole disk device by providing a means which performs arithmetic for ECC while storing a buffer with parallel data in block units sent out of a host computer. CONSTITUTION:The figure shows writing operation for data from the host computer to the buffer. The data (DATA 23) sent out of the host computer while stored in the buffer through a buffer control part 5 are inputted to an ECC part 2, which performs the ECC arithmetic. When one block of DATA 23 is all inputted, the ECC part 2 generates an inspection symbol (ECC 24), which is stored in the buffer 27 right after the DATA 23. Consequently, the reliability of a disk device 9 and the whole system including the disk device 9 is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention utilizes a data error detection/correction function in a disk control device to detect and correct errors in a semiconductor memory.

The present invention relates to a device for improving data reliability.

[Conventional technology] For example, as described in HD64950S (Hitachi hard disk controller), the conventional technology is to improve the reliability of data between the disk control device and the recording medium. , When writing data, a check symbol is generated for the block-by-block parallel data sent from the host computer and added to the recording medium following the data, and when reading data, it is added to the data read from the recording medium. The data is checked for errors based on the test symbols, and if an error is detected, the erroneous data is corrected and then the data is transferred to the host computer.

The prior art will be explained in more detail below.

9 and 10 are block diagrams showing the internal configuration of a disk control device used in a conventional disk device, including an error detection/correction section 2 (hereinafter referred to as ECC section), a host interface control section 3, a drive interface control section 4, a buffer control section 5, and a selector 6. 9th
The figure shows the data flow when data transfer between the host computer and the drive sofa 7 (hereinafter referred to as host-buffer transfer) and data transfer between the recording medium and the drive sofa 7 (hereinafter referred to as drive-buffer transfer) are performed simultaneously. FIG. 10 shows a case where these two transfers are not performed simultaneously.

The operation when writing data to a recording medium in the conventional disk control device 1 is shown in FIGS. 11 and 14, and the operation when reading data from a recording medium is shown in FIGS. 12 and 13.
This will be explained using figures.

(1) When writing data to a recording medium, block-based parallel data (hereinafter referred to as DATA 23) sent from the host computer is processed by the host interface control in the disk controller 1 as shown in FIG. The data is transferred from the unit 3 to the buffer control unit 5 and stored in the buffer 7. Thereafter, as shown in FIG. 14, the stored DATA 23 is transferred to the drive interface control section 4 via the buffer control section 5, but at the same time,
The signal is also transferred to the ECC unit 2, where ECC calculation is performed, and a check symbol (hereinafter referred to as ECC 24) is generated. Then, following DATA23 read from buffer 7, E
CC24 is also transferred to the drive interface control unit 4, and DATA23 and ECC24 are recorded on the recording medium.

(2) When reading data from the recording medium, the DATA23 and ECC24 read from the recording medium are
Drive interface control section 4 of disk control device 1
will be forwarded to. Then, as shown in Figure 12, DATA2
3 is stored in the buffer 7 from the drive interface control section 4 via the buffer control section 5, but at the same time, E.
The data is also transferred to the CC unit 2, where ECC calculation is performed. E.C.C.
In part 2, the ECC 24 read following the DATA 23
is also input, and error detection of DATA23 is performed.

If an error is detected in the DATA 23, the error data stored in the buffer 7 is corrected. And the 13th
As shown in the figure, DATA 23 is transferred from the buffer control unit 5 to the host computer via the host interface control unit 3.

[Problems to be Solved by the Invention] The above-mentioned conventional technology has an error detection/correction function for data between the disk control device 1 and the recording medium, but it has an error detection/correction function for data between the disk control device 1 and the buffer. does not have error detection/correction functionality. Therefore, even if a malfunction occurs in the buffer storing data and an error occurs in the data, there is no way to detect this, so there is a risk that the incorrect data will be transferred to the host computer as is. , the reliability of the disk device 1 and the entire system including the disk device 1 deteriorates.

The longer the time that data is stored in the buffer, the higher the probability that the data will be erroneous due to error differences in the buffer. For example, if a data buffer is equipped with a cache function, data may be stored for a long time, which increases the probability of data errors.

An object of the present invention is to improve the reliability of the data handled and the entire disk device.

[Means for Solving the Problems] In order to achieve the above object, in the present invention, in a disk control device having a data error detection/correction function, parallel data in blocks sent from a host computer is stored in a buffer. Means for performing FCC calculations at the same time as storage is provided, and furthermore, means for writing generated check symbols into a buffer is provided. Further, when transferring data from the sofa to the host computer and the recording medium, and when storing data read from the recording medium in a buffer together with the FCC, means for checking whether or not there are errors in the transferred data; When a data error is detected, a means is provided to correct the error data.

[Operations] FIGS. 1 and 2 are block diagrams showing the internal configuration of a disk control device 1 equipped with the technical means of the present invention, which includes an error detection/correction section (hereinafter referred to as ECC section) 2, a host interface control section 3, drive interface control section 4,
It consists of a buffer control section 5, and FIG. 1 shows a case where the above-mentioned host-buffer transfer and tribo buffer transfer are performed simultaneously, and FIG. 2 shows a case where these two transfers are not performed simultaneously. The operation of the technical means described above will now be explained. Using FIGS. 5 and 6, the operation when writing data from the host computer or from the recording medium to the buffer will be explained, and using FIGS. Alternatively, the operation when reading data to a recording medium will be explained.

(1) When writing data to the buffer FIG. 5 shows the operation when writing data from the host computer to the buffer. Data (hereinafter referred to as DATA23) sent from the host computer is stored in the buffer through the buffer control unit 5, and at the same time it is ECC-coded.
The signal is also input to section 2 and ECC calculation is performed thereon. - When the DATA 23 of all blocks is input, the ECC unit 2
A check symbol (hereinafter referred to as ECC24) is generated and D
Following the ATA 23, the ECC 24 is also stored in the buffer 7.

Further, FIG. 6 shows the operation when writing the DATA 23 and ECC 24 read from the recording medium to the buffer 7. At this time, DATA23 and ECC24 are stored in the buffer 7 and are also input to the ECC unit 2, and the DATA23 and ECC24 are
Check whether there are any errors in 23. If an error is detected, the error data stored in the buffer 7 is corrected.

(2) When reading data from the buffer FIGS. 7 and 8 show operations when data is sent to the host computer and the recording medium, respectively. At this time, similarly to FIG. 6, the DATA 23 and ECC 24 read from the buffer 7 are also sent to the ECC section 2,
Perform error detection. If an error is detected, the error data is corrected at each transfer destination.

[Embodiment 1] As an embodiment of the present invention, the above-mentioned host
The operation of the disk control device when buffer transfer and drive-buffer transfer are not performed simultaneously will be described. Here, it is assumed that a 12-byte Reed-Solomon code is used as the error correction code.

As shown in FIG. 2, the disk control device 1 includes a fox detection/correction section 2 (hereinafter referred to as ECC section), a host interface control section 3, a drive interface control section 4,
It consists of a buffer control section 5 and a selector 6.

The ECC unit 2 receives multiple bytes of input DATA23.
A 12-byte ECC24 is generated from the data, and the ECC is output. Furthermore, by inputting DATA 23 and ECC 24, it is determined whether or not an error has occurred in the input DATA 23, and if an error is detected, the function is provided to obtain a correction pattern for the error data.

Next, the operation of the disk control device which is an embodiment of the present invention will be explained. FIG. 3 is a block diagram showing the internal configuration of the disk device 9 having the disk control device 1. As shown in FIG.

As seen in the figure, the disk device 9 includes a disk controller 1, a microprocessor 10. Data buffer 7, host interface control device 11, serial/parallel conversion circuit 12, recording/reproducing circuit 13, recording medium 14
Consists of.

FIG. 4(a) shows the configuration of the recording/reproducing circuit 13 at the time of data writing, which includes an encoding circuit 16.degree. write clock generation circuit 15, a head amplifier 17, and a read/write head 18. Further, FIG. 4(b) shows the configuration of the recording/reproducing circuit 13 at the time of data reading, in which the decoding circuit 21, the phase synchronization circuit 20, . It consists of a waveform shaping circuit 22, a head amplifier 17, and a read/write head 18.

Here, a host computer 8 as shown in FIG.
The data transfer path between the disk drive 2 and the disk drive 2 will be explained with a focus on the error detection/correction function described above. It is assumed that DATA 23 is a block of 512 bytes, and that the transfer of DATA 23 and FCC 2-1 on the disk controller is performed in units of 1 hide.

Hereinafter, the operation when writing data to the recording medium 14 will be explained using FIGS. 5 and 8, and FIG. 6.

The operation when reading data from the recording medium 14 will be described in detail with reference to FIG.

(1) When writing data to a recording medium Parallel data sent from the host computer 8 is received by the host interface control device J1 of the disk unit 9 via the parallel interface, and is then sent to the host interface control device J1 of the disk control device 1. The data is transferred to the interface control unit 3. This transferred data (hereinafter referred to as DATA23
) is.

As shown in FIG. 5, the data is transferred to the data buffer 7 through the buffer control section 5 and simultaneously transferred to the EC0 section 2, where ECC calculation is performed. - DA of all blocks
When TA23 is transferred, 12-byte ECC24 is generated in EC0 section 2, and ECC2 is generated following DATA23.
4 is also written to the data buffer. In addition, as shown in FIG. 8, DATA23 and ECC2 in the data buffer 7
4 is transferred to the drive interface control unit 4 for writing to the recording medium 14, but is also input to the EC0 unit 2 at the same time to detect errors in the DATA 23.

If an error is detected, the correction position and correction pattern can be determined from the error syndrome, which is the calculation result of the EC0 unit 2.
It is possible to correct the TA 23 and transfer the corrected DATA 23 to the drive interface control unit 4 again. moreover.

DATA 23 and ECC 24 are transferred from the drive interface control unit 4 to the serial/parallel conversion circuit 12, converted into serial data, and then transferred to the recording/reproducing circuit 1.
3 and recorded on the recording medium 14 using the read/write head 18.

(2) When reading data from the recording medium, the DATA 23 and ECC 24 stored in the recording medium 14 are
The data is read using the write head 18 and the recording/reproducing circuit 13
After being decoded, the signal is transferred to the serial/parallel conversion circuit 12 as an NRZ signal 19, becomes parallel data, and is sent to the disk controller as DATA 23 and ECC 24.

As shown in FIG. 6, the sent DATA 23 and ECC 24 are transferred from the drive interface control section 4 to the data buffer 7 via the buffer control section 5, and at the same time are also transferred to the EC0 section 2. Perform error detection. If an error is detected, the erroneous read data stored in the data buffer 7 can be corrected, as in the case described above.

Further, as shown in FIG. 7, the DATA23 in the data buffer 7 is transferred from the buffer control unit 5 to the host interface control unit 3 and simultaneously transferred to the EC0 unit 2, and furthermore, the ECC24 is transferred to the EC0 unit 2. By inputting the data, errors in the DATA 23 transferred from the data buffer 7 to the host computer 8 are detected. If an error is detected, the erroneous DATA 23 in the data buffer 7 is corrected and the corrected DATA 23 is
can be transferred to the host interface control unit 3 again.

In this embodiment, error detection/correction functions can be provided both between the disk control device and the recording medium and between the disk control device and the data 911277 by making some changes to the conventional disk control device. This makes it possible to improve the reliability of the entire disk device.

[Effects of the Invention] According to the present invention, the ECC section 2 of the disk control device 1 not only connects the disk control device 1 and the recording medium 14;
Since error detection/correction can be performed even during data transfer between the disk controller 1 and the data buffer 7,
The reliability of the disk device 9 and the entire system including the disk device 9 can be improved. Furthermore, when the error detection/correction circuit 2 is shared, an increase in the amount of one circuit can be suppressed. Furthermore, when the data buffer 7 shown in FIG. 3 has a cache function, the time for which data is held in the data buffer 7 becomes longer, so that improving the reliability of the data buffer 7 according to the present invention is very effective. this is,
The same applies when the data buffer is used as a semiconductor disk device.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing the internal configuration of the disk control device of the present invention, FIG. 3 is a block diagram showing the internal configuration of the disk device, FIG. 4 is a block diagram of the recording/reproducing circuit, and FIG. 8 are explanatory diagrams of the operation of the disk control device of the present invention, FIGS. 9 and 10 are block diagrams of the internal configuration of a conventional disk control device, and FIGS. 11 to 14 are conventional disk control device FIG. Explanation of symbols 1... Disk control device, 2... Error detection/correction unit, 3... Host interface control unit, 4... Drive interface control unit, 5... Buffer control unit, 6...
Selector, 7... Buffer, 8... Host computer, 9... Disk device, 10... Microprocessor, 11... Host interface control device, 12...
Serial/parallel conversion circuit, 13... Recording/reproducing circuit, 14... Recording medium, 15... Write clock generation circuit, 16- Encoding circuit, 17... Head amplifier, 18
...Read/write head, 19...NRZ signal, 2
0. Phase synchronization circuit, 21.. Decoding circuit, 22.. Waveform shaping circuit, 23. DATA, 24. EC0 No. 6L21 JI20 No. 14L2] Ha Nofa'l

Claims (1)

[Claims] 1. In a disk control device having an error detection/correction circuit, parallel data in units of blocks sent from a host computer is written to a semiconductor memory and at the same time an ECC operation is performed to generate check symbols. means for writing the generated test symbol into a semiconductor memory; and a means for performing the ECC operation at the same time as writing the data read from the recording medium and the test symbol into the semiconductor memory, and detecting an error in the read data. means for performing detection; means for correcting error data on a semiconductor memory when error data is detected; and simultaneously transmitting the data on the semiconductor memory and the test symbol to the host computer or the recording medium. A disk control device comprising means for performing the ECC calculation and detecting errors in the transferred data, and means for correcting the error data at the transfer destination when the error data is detected. Device. 2. In claim 1, the ECC operation performed when writing the data read from the recording medium and the test symbol into the semiconductor memory, and the data on the semiconductor memory and the test symbol, are performed by the host computer,
Alternatively, a disk control device that uses one error detection/correction circuit to perform the ECC calculations respectively performed when sending data to the recording medium. 3. The disk control device according to claim 1 or 2, wherein a Reed-Solomon code is used as the error correction code. 4. The disk control device according to claim 1 or 2, wherein the function is provided on one chip of LSI. 5. A disk control device comprising the disk control device according to claim 1 or 2.