JPH042006B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tuning control method in a PLL radio receiver, and particularly to an intermediate frequency setting method. Generally, in a PLL radio receiver, the broadcast signal and the output signal of a voltage controlled oscillator as a local oscillator are mixed to obtain an intermediate frequency signal, and the intermediate frequency is determined by the oscillation frequency of the voltage controlled oscillator by a crystal resonator. , for example, 450KHz in the AM band,
In the FM band, a predetermined intermediate frequency of 10.7MHz can be determined with high accuracy. That is, in the AM band, the receiving band is 522 to 1611 KHz and the channel separation is 9 KHz, and when inputting 9 KHz as the reference frequency to the phase comparator, the frequency division number of the programmable divider should be 108 to 229, and the voltage The oscillation frequency of the controlled oscillator may be set to 972 to 2061 KHz.
In addition, the reference frequency 9KHz is the oscillation frequency of the reference oscillator.
Obtained by dividing 7.2MHz by 800 using a reference divider. However, the center frequency of the ceramic filter in the intermediate frequency amplification stage varies and does not necessarily match the above-mentioned predetermined intermediate frequency. for example,
If the center frequency of the ceramic filter is shifted to 451KHz instead of the predetermined intermediate frequency of 450KHz, in order to receive broadcast signals of 522 to 1611KHz, the oscillation frequency of the voltage controlled oscillator must be changed to 973 to 1611KHz.
The frequency division number of the programmable divider is determined to be 108 to 229 based on the predetermined intermediate frequency of 450KHz, so the oscillation frequency of the voltage controlled oscillator is 972 to 2061KHz, and therefore the optimum tuning point is 2062KHz. Unable to receive. Therefore, the reference frequency to the phase comparator is set to 1KHz, and the frequency division number of the programmable divider is set to 973~
2062 enables reception at the optimal tuning point, but lowering the reference frequency ratio number to the phase comparator in this way prevents deterioration of the S/N ratio due to a decrease in the PLL loop gain. Unfavorable due to inviting characteristics,
Furthermore, since the center frequency of the ceramic filter varies over a wide range, it is extremely troublesome and impractical to adjust the frequency division number for each receiver. Another problem was that the intermediate frequency shift could only be corrected every 1 KHz. Therefore, the present invention solves these problems by varying the oscillation frequency of the PLL reference oscillator. In other words, the center frequency of the ceramic filter is
For example, to receive a 522KHz broadcast signal, the frequency division number of the programmable divider should be 108 as described above, and the oscillation frequency of the reference oscillator should be f ₁ = 7.2M x 973/972 = 7.207407... MHz
Then, the oscillation frequency of the voltage controlled oscillator is f ₁ ÷
800×108=973KHz, the intermediate frequency is 973−
522 = 451KHz, which matches the center frequency of the ceramic filter, allows reception at the optimal tuning point. However, if the oscillation frequency of the reference oscillator is kept at f ₁ , when receiving a broadcast signal of 1611KHz,
The oscillation frequency of the voltage controlled oscillator is f ₁ ÷ 800 x 229 =
2063.120370...KHz, so the intermediate frequency deviates from 451KHz by more than 1KHz. That is,
When receiving a 1611KHz broadcast signal, set the oscillation frequency of the reference oscillator to f ₂ = 7.2M x 2062/2061 =
Must be 7.203493...MHz. In this way, the oscillation frequency of the voltage controlled oscillator is f ₂ ÷ 800
×229=2062KHz, and the intermediate frequency is 451KHz. However, conversely, the oscillation frequency of the reference oscillator
If you leave it set to f ₂ and receive a 522KHz broadcast signal, the oscillation frequency of the voltage frequency control oscillator will be f ₂ ×
800×108=972.471616…KHz, and the intermediate frequency will still be shifted by 500Hz. In view of the above, the present invention has been developed to change the reception frequency for each reception frequency when changing channels such as preset tuning or manual tuning, or changing reception frequencies such as band switching.
This invention provides a new tuning control method that enables reception at the optimal tuning point by changing the oscillation frequency of the PLL reference oscillator and setting the intermediate frequency to the center frequency of the ceramic filter. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is an antenna, 2 is a mixing circuit, 3 is a filter circuit consisting of a ceramic filter, etc., 4 is an intermediate frequency amplification circuit, 5 is a detection circuit, and 6 is a detection circuit. A low frequency amplifier circuit, 7 is a speaker. Further, 8 is a voltage controlled oscillator as a local oscillator, 9 is a programmable divider, 10 is a variable frequency reference oscillator including a crystal resonator 11 and a variable capacitance diode 12, 13
is a reference binder, 14 is a phase comparator, 15
is a low-pass filter, and these constitute a general PLL. Further, 16 is a frequency division number setting means for setting a frequency division number corresponding to each reception frequency in the programmable divider 9 in response to a signal P instructing to change the reception frequency, and 17 is obtained from the intermediate frequency amplification circuit 4. An intermediate frequency signal strength determining means 18 for determining the strength of the intermediate frequency signal _VIF converts the input digital signal _D0 into an analog signal, applies this analog output voltage _V0 to the variable capacitance diode 12, and outputs the reference oscillator. 10 oscillation frequencies
A D/A converter 19 for controlling f ₀ inputs the signal P, and when _changing the reception frequency, the D/A converter 1
8 is a D/A conversion control means that supplies a digital signal D ₀ to the reference oscillator 10, and if the value of this digital signal D ₀ is changed to change the oscillation frequency f ₀ of the reference oscillator 10,
The oscillation frequency f _L of the voltage controlled oscillator 8 changes, and the intermediate frequency f _IF changes accordingly. FIG. 2 is a specific circuit diagram of the intermediate frequency signal strength determination means 17, in which the rectified intermediate frequency signal V _IF is input to one terminal of the comparator 20, and the determination level V _T is input to the + terminal. ing. Figure 3 shows the intermediate frequency f _IF and intermediate frequency signal V _IF
It is a characteristic diagram showing the relationship between the intermediate frequency signal V _IF
shows substantially symmetrical characteristics with respect to the center frequency f _D of the filter circuit 3. Also, FIG. 4 shows the D/A converter 1.
Relationship between the digital input signal D ₀ and the output voltage V ₀ of 8 and the output signal of the intermediate frequency signal strength determination means 17
FIG. 3 is a diagram showing the relationship with C ₀ . Furthermore, FIG. 5 shows the frequency division number setting means 16 and the D/A
This is a specific circuit diagram of the conversion control means 19 , in which a preset tuning signal PS is used as a signal P instructing a change in reception frequency. In Figure 5,
21 is an up-down counter for supplying the digital signal _D0 to the D/A converter 18; 22 is a down counter to which the contents of the up-down counter 21 are set at a predetermined timing; and 23, when the contents of the down counter 22 are set to "0". 24 is a shift register to which the D input terminal of the most significant bit is contacted and the output is inputted in order from the most significant bit to the least significant bit, and the output terminal is connected to the D/A converter. 18, and when the PE terminal is at "H" level, the up/down counter 21
The content of is taken as the digital signal D ₀ as it is,
The signal is supplied to the D/A converter 18. Next, the operation of this embodiment will be explained with reference to timing charts shown in FIGS. 6 and 7. Here, the center frequency of the filter circuit 3 of this receiver is f _D , which is shifted from the predetermined intermediate frequency of 450 KHz, as shown in FIGS. The frequency is this
Assume that f _A is different from f _D , and the content RA of the up-down counter 21 at that time is "10". First, when the preset selection button is pressed,
A preset channel selection signal PS is generated, a frequency division number corresponding to the channel is input from the preset memory 25 to an up-down counter 26, and this frequency division number is set in the programmable divider 9. At the same time, the RS flip-flop 27 is reset,
The signal U/D becomes "L" level, the up-down counter 21 works as a down counter, and
The RS flip-flop 28 is set, and the PE terminal of the shift register 24 goes to "H" level.
The contents of the up-down counter 21 remain as D/
The signal is supplied to the A converter 18. Next, the output signal PC of the D flip-flop 29 to which the signal PS is input goes to the "H" level at the rising edge of the clock φ, so the up-down counter 21 starts counting down the clock φφ via the AND gate 30. The content RA is getting smaller. Therefore, the output voltage V ₀ of the D/A converter 18 decreases as shown in FIG. 4, and the oscillation frequency f ₀ of the reference oscillator 10 also decreases. Along with this, the intermediate frequency signal V _IF also decreases as shown in FIG. 3 and reaches the determination level V _T . Then, the output signal _C0 of the comparator 20 is inverted from the "L" level to the "H" level, and in order to set the RS flip-flop 27, the signal U/D goes to the "H" level and the counter direction of the up/down counter 21 is set to the "H" level. direction. In addition, since the _Q1 signal of the T flip-flop 31 also becomes "H" level, the output of the AND gate 32 becomes "H" level, and the content RA "6" of the up-down counter 21 when it reaches the judgment level becomes the down counter. 22, and its content RB becomes "6". Since the up-down counter 21 will now up-count the clock φφ, its contents will become larger and the output voltage V ₀ of the D/A converter 18 will also rise. Therefore, the oscillation frequency f ₀ and the intermediate frequency signal V _IF also rise. However,
The content RA of the up-down counter 21 and the oscillation frequency f ₀ continue to rise, but when the intermediate frequency signal V _IF exceeds the center frequency f _D of the filter circuit 3, it starts to fall, and then returns to the judgment level V _T. I reach it. Then, the output signal of the comparator 20 again
Since _C0 becomes "H" level and the _Q2 output of T flip-flop 33 becomes "H" level, AND
A clock φφ begins to be applied to the down counter 22 via the gate 34. Then, the up-down counter 21 continues to count up from the content RA "20" when it reaches the judgment level again.
The down counter 22 shows the set content RB “6”
Count down from . When the count progresses and the content of the down counter 22 becomes "0", the output signal R _BO of the NOR gate 23
goes to "H" level, and the output signal CLD of the extraction circuit consisting of two D flip-flops 35, 36 and AND gate 37 resets the D flip-flop 29, so the output signal RC goes "L".
level, the application of the clock φφ to the up-down counter 21 and the down counter 22 is stopped, and the content of the up-down counter 21 becomes "26". That is, it is the sum of the content "6" when the intermediate frequency signal V _IF first reaches the determination level and the content "20" when it reaches the determination level again. Furthermore, the output signal CLD resets the T flip-flops 31 and 33 through the OR gate 38 and
Since the flip-flop 28 is reset, the PE terminal of the shift register 24 becomes "L" level, and
The contents of the up-down counter 21 are no longer set, and the contents remain at "26". However, since the output signal CLD is inverted to the "L" level at the next rising edge of the clock φφ, the shift register 24 is shifted to the left by one pit at the falling edge, and its contents are halved to become “13”. At the same time, the signal Q _B of the D flip-flop 36 goes high.
level, and at this time the D flip-flop 39
Since signal _C is also at "H" level, AND gate 4
The output signal _G0 of 0 attains the "H" level, this signal _G0 is input to the PE terminal of the up-down counter 21, and the content "13" of the shift register 24 is set in the up-down counter 21. Therefore,
The output signal of the shift register 24, that is, the input digital signal _D0 of the D/A converter 18, is the content "6" when the intermediate frequency signal _VIF first reaches the judgment level, and the content "6" when the intermediate frequency signal VIF reaches the judgment level again. The midpoint value “13” of the content “20” is supplied to the D/A converter 18. Therefore, the output voltage V ₀ of the D/A converter 18 is
When the intermediate frequency signal V _IF reaches the determination level, the voltage V _D becomes the midpoint between the voltage V _B and V _C , and the reference oscillator 1
Oscillation frequency f ₀ of 0 is also the frequency at which the intermediate frequency signal V _IF reaches the judgment level f 0 The frequency at the midpoint between _OB and f _OC
f Set to _OD . Therefore, the intermediate frequency f _IF is set to the center frequency f _D of the filter circuit 3. Therefore, during reception, reception can be performed at the optimal reception point. Now, when you try to select another channel and change the receiving frequency again, the frequency division number set in the programmable divider 9 will change and the intermediate frequency f _IF will deviate from the center frequency f _D. When changing the reception frequency, the same operation as described above is performed and the oscillation frequency of the reference oscillator 10 is controlled, so that the intermediate frequency f _IF is set to the center frequency f _D again. In this embodiment, the oscillation frequency of the reference oscillator 10 is controlled to first decrease and then increase, but conversely, it may be controlled to increase first and then decrease. Furthermore, when the broadcast signal level is low as shown by the dashed line in Fig. 3, or when the intermediate frequency f _A becomes lower than f _B when changing the reception frequency, the transistor 41 shown in Fig. 2 is used. By providing this and turning it on, the determination level can be switched from V _T to a lower V _T ' as shown in FIG. Also the fifth
The circuit shown in the figure is one example, and a similar operation may be performed using a microcomputer, for example. Furthermore, if a certain degree of error is allowed, it is possible to make some changes, such as not changing the oscillation frequency of the reference oscillator 10 in the adjacent channel and changing the oscillation frequency only when the receiving frequency changes significantly. can not use. As described above, the tuning control method according to the present invention changes the oscillation frequency of the RLL reference oscillator while determining the strength of the intermediate frequency signal when changing the reception frequency, so that the intermediate frequency can be reliably adjusted to the intermediate frequency amplification stage. can be set to the center frequency of the filter, thus making it possible to receive at the optimum tuning point. In addition, since the intermediate frequency can be set automatically, there is no need to adjust the intermediate frequency setting for each receiver, and there is no need to select filters as strictly as before. has advantages.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a specific circuit diagram of intermediate frequency signal strength determining means,
Figure 3 is a characteristic diagram showing the relationship between the intermediate frequency f _IF and the intermediate frequency signal V _IF , and Figure 4 is the relationship between the digital input signal D ₀ and the output voltage V ₀ of the D/A converter and the intermediate frequency signal strength. A characteristic diagram showing the relationship with the output signal _C0 of the determination means, FIG. 5 shows the frequency division number setting means and the D/A
Specific circuit diagrams of the conversion control means, FIGS. 6A to 6C, and FIGS. 7I to IB are timing charts for explaining the operation of this embodiment. Explanation of main figure numbers, 2...Mixing circuit, 3...Filter circuit, 4...Intermediate frequency amplification circuit, 8...Voltage controlled oscillator, 9...Programmable divider,
10...Reference oscillator, 13...Reference divider, 14...Phase comparator, 15...Low pass filter, 16 ...Dividing number setting means, 17...Intermediate frequency signal strength determining means, 18...D /A converter, 19 ... D/A conversion control means, 20... Comparator, 21... Up/down counter, 22... Down counter, 24... Shift register.

Claims (1)

[Claims] 1. A voltage controlled oscillator that generates a local oscillation frequency signal, a programmable divider that divides the local oscillation frequency, a variable frequency reference oscillator whose oscillation frequency is variable, a signal obtained from the variable frequency reference oscillator, and the programmable divider that divides the local oscillation frequency. A phase comparator to which the output signal of the divider is applied controls the oscillation frequency of the voltage controlled oscillator, and the signal strength of the intermediate frequency signal obtained from the local oscillation frequency signal and the reception frequency signal reaches a predetermined level. intermediate frequency signal strength determining means for determining the intermediate frequency signal strength; and intermediate frequency correcting means for controlling the oscillation frequency of the variable frequency reference oscillator under the control of the intermediate frequency signal strength determining means; At the same time, the intermediate frequency correction means lowers or increases the oscillation frequency of the variable frequency reference oscillator to reach the determination level of the intermediate frequency signal strength determination means. The oscillation frequency of the variable frequency reference oscillator when the frequency is reached is stored as a first frequency, and then the oscillation frequency of the variable frequency reference oscillator is increased or decreased until the determination level of the intermediate frequency signal strength determination means is reached. The oscillation frequency of the variable frequency reference oscillator of
A tuning control method characterized in that the oscillation frequency of the variable frequency reference oscillator is set to a frequency approximately in the middle of the first frequency and the second frequency.