JPH04199870A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To make it possible to obtain a high capability and a high reliability integrated circuit by installing an internal grounding potential conversion circuit in order to raise internal supply grounding potential over external grounding potential. CONSTITUTION:A semiconductor device is formed with conventional dynamic type MOS, RAM or the like on a P type substrate. A substrate voltage generatio circuit is built-in so that this substrate potential may be a lower value than the grounding potential (negative value). The grounding potential of circuit system is set Vss' (> Vss) while the substrate potential is set to outside grounding voltage (Vss). Therefore, no substrate voltage generation circuit is required, which makes it possible to reduce the size of a chip. Furthermore, this construction stabilizes the substrate potential an avoids the adverse effect on the device characteristics induced by the deflection of the substrate potential. It is, therefore, possible to enhance both reliability and operational performance.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to integrated circuit devices, and particularly to improving the reliability and performance of miniaturized large-scale integrated circuits.

[Conventional technology]

Conventionally, in large-scale integrated circuits (LSI), as the gate length of MO3 type transistors has become shorter, it has become increasingly difficult to believe that if the power supply voltage is kept constant, the threshold value of the transistor will change due to the injection of hot carriers into the gate oxide film. sexual problems or
This results in a problem of increased leakage current due to the lower breakdown voltage of the transistor. As a solution to this problem, (1) lower the externally supplied power supply voltage, and (2) maintain the externally supplied power supply voltage, convert it to a lower voltage inside the element, and supply it to the internal circuit.

or is being done. However, (1) involves changing the external specifications of the element, which is a big problem in practice.

Furthermore, as one method (2), a method of incorporating an internal power supply voltage step-down circuit is known. An example is shown in FIG. FIG. 4 shows a conventional power supply voltage step-down diagram, in which the power supply voltage of 5V is converted to a low voltage of about 3.5V and supplied to the internal circuit.

Next, the operation will be explained. For example, when configuring a CMO3 circuit, the output impedance of the power supply voltage conversion circuit is usually not 0 (zero) but rather high.

In this case, the ability to supply current to the load is limited, and if more current flows than this, the output voltage will drop. This slows down the rise of the note that should change from "H" potential to "H" potential within the circuit, causing a reduction in speed. In the CMO3 circuit system, the circuit note is usually set to “L”.
Depending on the difference in the mobility of electrons and holes, it may be necessary to use a P-channel transistor to raise the voltage from ``H'' to ``H'' and an n-channel transistor to lower the voltage from ``H'' to ``L''. When compared in width), the current drive capability of the P-channel type is smaller than that of the N-channel type.Therefore, the time required for the transition from the circuit node "L' to "H" and from "H" to "L" is usually shorter than the n-channel type. In order to align them, the gate width of P-channel transistors forming the same stage (for example, an inverter) is made larger than that of N-channel transistors.

If there is a further drop in the power supply voltage as described above, this difference will become even larger and may cause problems in circuit operation.

[Problem to be solved by the invention]

Since the conventional integrated circuit device is constructed as described above, there is a problem in that the drop in internal power supply voltage has a large negative effect on circuit performance.

This invention was made to solve the above-mentioned problems, and aims to provide a high-performance and highly reliable integrated circuit device.

[Means to solve the problem]

The integrated circuit device according to the present invention is provided with an internal ground potential conversion circuit so that the internal ground potential is higher than the externally supplied ground potential.

[Effect]

The integrated circuit device according to the present invention converts an externally supplied ground potential to a higher potential (a potential close to the source voltage) and supplies it to the internal circuit.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram of a ground potential conversion circuit according to an embodiment of the present invention, which boosts an external ground potential and supplies it to an internal circuit system. In the figure, V ref is, for example, 1.5 V, the internal ground potential is about 1.5 V, the power supply voltage applied to the circuit is 5 V - 1,5 V = 3.5 V, and as in the conventional example, the pot Problems such as transistor deterioration due to carrier injection are avoided.

According to this embodiment, for the same reason as before, the gate of the n-channel transistor is Making the width a little thicker than usual is easy considering that it is originally much smaller than an n-channel transistor or a p-channel transistor.

FIG. 2 shows another embodiment of the invention. P board CMO
A configuration diagram of 3 circuits, usually dynamic type MO3, RAM
For example, a device is formed on a P-type substrate, and the potential of this substrate is set to a value lower than the ground potential (negative value). For this purpose, it has a built-in substrate voltage generation circuit. In this embodiment, the ground potential of the circuit system is set to V ss'(> V ss), and the substrate potential is set to external ground potential (V ss). This eliminates the need for a substrate voltage generation circuit, making it possible to reduce the chip size.Also, since the substrate potential becomes extremely stable, the device characteristics are not affected by noise caused by fluctuations in the substrate potential, which occurs in the conventional example. Negative effects can be avoided.

FIG. 3(a) is a block diagram of an n-substrate CMO3 circuit showing still another embodiment of the present invention, in which a P-well is formed on an n-type substrate to realize a CMO3 circuit system. Usually P-
The well potential is set to the ground potential, but in this example, the ground potential of the internal circuit system is Vss', and the P-well potential is Vss
(external ground potential).

This makes the P-well potential lower than the circuit system ground potential, which has the effect of significantly increasing the resistance to latch-up, which is an abnormal phenomenon in the CMO3 circuit system.

Moreover, FIG. 3(b) shows a further improved example of FIG. 3(a). Here, in addition to the third embodiment, the power supply voltage V cc' of the internal circuit is further lowered than the external power supply voltage VCC, and Vc, ( is applied to the n-board. This further increases the latch-up resistance. This can be similarly applied to an n-well system on a P substrate.

〔Effect of the invention〕

As described above, according to the present invention, since the internal ground potential is higher than the externally supplied ground potential and is supplied to the internal circuit, it is possible to improve reliability and performance.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a ground potential booster circuit according to one embodiment of the present invention, FIG. 2 is a block diagram of a P-substrate CMO3 circuit system according to another embodiment of the present invention, and FIG. 3 (al, (b)) 4 is a block diagram of an n-board CMO3 circuit system according to yet another embodiment of the present invention, and FIG. 4 is a circuit diagram of a conventional power supply voltage step-down circuit. In the figure, Vcc is an external power supply voltage, and V cc' is a power supply voltage. , Vss is the external ground potential, and V ss' is the ground potential of the circuit system. In the figures, the same symbols indicate the same or equivalent parts. Agent Masu Oiwa Yubaku 11 ■ Ext, Vss [xt , VssWef
= 1.5v Vss -L5 Vcc: Outside 4? Electric skin pressure ゛Vcc': @I! f,fe)”r'Vss
: Tato! 6Pg'a Ride 1gu Yume Nii 1YSS'
: IE RiS(T←搏加しいり-ψreport No. 311 5S vss > Vss Vc do(Vcc No. 41'ff1 Ext, Vcc Ext, Vcc
'VrCf = 3.5v

Claims (1)

[Claims] In an integrated circuit device to which a first potential and a second potential lower than the first potential are supplied, a conversion circuit system for converting the first or second potential into a third potential close to the other potential is provided. An integrated circuit device provided in the integrated circuit device, wherein the third potential is used as the first or second potential of at least some of the circuits in the integrated circuit device. .