JPH04199740A - Lead frame of semiconductor ic - Google Patents
Lead frame of semiconductor icInfo
- Publication number
- JPH04199740A JPH04199740A JP33402890A JP33402890A JPH04199740A JP H04199740 A JPH04199740 A JP H04199740A JP 33402890 A JP33402890 A JP 33402890A JP 33402890 A JP33402890 A JP 33402890A JP H04199740 A JPH04199740 A JP H04199740A
- Authority
- JP
- Japan
- Prior art keywords
- inner lead
- stage
- stage inner
- lead
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000010276 construction Methods 0.000 abstract 1
- 230000010485 coping Effects 0.000 abstract 1
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 238000007789 sealing Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、多ビン化に対応が可能なインナーリードを備
えた半導体集積回路のリードフレームに関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a lead frame for a semiconductor integrated circuit equipped with an inner lead that can accommodate a large number of bins.
従来の技術
近年、半導体集積回路は、微細化、高集積化が進んでお
り、半導体チップ自体の大容量化、多機能化に伴い、外
部からの入出力数も増すものもあり、多ピン化が進んで
きている。Conventional technology In recent years, semiconductor integrated circuits have become smaller and more highly integrated.As semiconductor chips themselves have become larger in capacity and more multifunctional, the number of external inputs and outputs has also increased, resulting in an increase in the number of pins. is progressing.
以下に従来の半導体集積回路のリードフレームについて
説明する。A conventional lead frame for a semiconductor integrated circuit will be described below.
第３図、第４図は、従来の半導体集積回路のリードフレ
ームを示すものである。第３図は平面図、第４図は断面
図である。第３図、第４図において、１は半導体チップ
、２はダイパッド、３はインナーリード、４は半導体チ
ップとインナーリードをワイヤボンディングを行い接続
するワイヤである。従来は、ダイパッド２に装置した半
導体チップ１の表面上の電極部からワイヤボンディング
を行いインナーリード３にワイヤで結線し、アウターリ
ードと半導体チップの接続を行い、外部から半導体集積
回路に信号を送る、半導体集積回路から外部に信号を送
るという動作を行っている。3 and 4 show lead frames of conventional semiconductor integrated circuits. FIG. 3 is a plan view, and FIG. 4 is a sectional view. In FIGS. 3 and 4, 1 is a semiconductor chip, 2 is a die pad, 3 is an inner lead, and 4 is a wire for connecting the semiconductor chip and the inner lead by wire bonding. Conventionally, wire bonding is performed from the electrode part on the surface of the semiconductor chip 1 installed on the die pad 2, and the wire is connected to the inner lead 3, the outer lead is connected to the semiconductor chip, and a signal is sent from the outside to the semiconductor integrated circuit. , which performs the operation of sending signals from a semiconductor integrated circuit to the outside.
発明が解決しようとする課題
従来の半導体集積回路のリードフレーム構造では、イン
ナーリードとグイパッド間の距離が技術的に短くするこ
とが難しく、これ以上インナーリード数を増すことがで
きなくなってきている。インナーリード数が増えないと
いうことは、半導体集積回路のピン数を増すことが、難
しくなってきている。ビン数を増すため、隣接するイン
ナーリート間の距離を短くすると、後工程の樹脂封止工
程で、半導体チップとインナーリードを接続するｒツイ
ヤ線が容易に接触する可能性があり、ワイヤ線の接触に
より半導体集積回路の誤動作をまねく原因となる。Problems to be Solved by the Invention In the conventional lead frame structure of a semiconductor integrated circuit, it is technically difficult to shorten the distance between the inner leads and the lead pads, and it has become impossible to further increase the number of inner leads. The fact that the number of inner leads cannot be increased means that it is becoming difficult to increase the number of pins of a semiconductor integrated circuit. If the distance between adjacent inner leads is shortened in order to increase the number of bins, the r-wire wires that connect the semiconductor chip and the inner leads may easily come into contact with each other in the later resin sealing process, and the wire wires may Contact may cause malfunction of the semiconductor integrated circuit.
課題を解決するための手段
本発明は、上記問題点を解決するもので、半導体１回路
のリードフレームのインナーリートを従来の１段のもの
でなく、２段式のインナーリードをもつ半導体集積回路
のリードフレームである。Means for Solving the Problems The present invention solves the above-mentioned problems, and provides a semiconductor integrated circuit having a two-stage inner lead instead of the conventional one-stage inner lead of the lead frame for one semiconductor circuit. This is a lead frame.
作用
２段式のインナーリード構造により、１段目のインナー
リートを増ずことはない為、隣接するワイヤ線の接触を
防止することになる。又、半導体１回路外部への入出力
ピン数も容易に増すことができ多ピン化に対応すること
ができる。Function: Due to the two-stage inner lead structure, the number of inner leads in the first stage is not increased, which prevents adjacent wire lines from coming into contact with each other. Further, the number of input/output pins to the outside of one semiconductor circuit can be easily increased, and it is possible to cope with an increase in the number of pins.
実施例
第１図、第２図は、本発明の一実施例による半導体集積
回路のり一トフレームの２段式インナーリード構造を示
すものである。第１図は平面図、第２図は断線図である
。第１図、第２図において、１１は半導体チップ、１２
はダイパッド、１３は１段目インナーリード、１４は２
段目インナーリード、］５は１段目インナーリードと半
導体チップをワイヤボンディングで接続する１段目ワイ
ヤ、１６は２段目インナーリードと半導体チップをワイ
ヤボンディングで接続する２段目ワイヤである。以下に
本発明の一実施例の作用について説明する。Embodiment FIGS. 1 and 2 show a two-stage inner lead structure of a semiconductor integrated circuit board frame according to an embodiment of the present invention. FIG. 1 is a plan view, and FIG. 2 is a cross-sectional view. In FIGS. 1 and 2, 11 is a semiconductor chip, 12
is the die pad, 13 is the first stage inner lead, 14 is 2
5 is a first stage wire that connects the first stage inner lead and the semiconductor chip by wire bonding, and 16 is a second stage wire that connects the second stage inner lead and the semiconductor chip by wire bonding. The operation of one embodiment of the present invention will be explained below.
この一実施例の発明は、第３図、第４図にて説明した従
来例の１段式インナーリードをもつ半導体集積回路のリ
ードフレームに、インナーリードを１段増設した２段式
インナーリードをもつ半導体集積回路のリードフレーム
である。２段式インナーリードをもつ半導体集積回路の
リードフレームについて説明する。隣接する１段目イン
ナーリートの中心と中心との間の上部に２段目のインナ
ーリードを設ける。２段目インナーリードは、１段目イ
ンナーリートよりダイパッドからの距離を長くする。そ
して、１段目、２段目のインナーリードがダイパッドか
ら十分に距離の長いところで、幅を細い形状にし、その
細くした部分から、隣接する１段目インナーリートの間
に、２段目インナーリードを入れて、１段目、２段目イ
ンナーリードの高さを同しにする。又、樹脂封止方法は
、２段式インナーリード構造とすると、従来の封止方法
であると隅々まで樹脂が送りこまれない可能性もあり、
従来１方向からの樹脂の注入を、多方向からの樹脂の注
入を行うことにより、通常のパッケージと同程度の樹脂
封止の実力を得る。The invention of this embodiment is a two-stage inner lead in which one additional stage of inner leads is added to the lead frame of a semiconductor integrated circuit having a single-stage inner lead of the conventional example explained in FIGS. 3 and 4. This is a lead frame for semiconductor integrated circuits. A lead frame for a semiconductor integrated circuit having a two-stage inner lead will be described. A second stage inner lead is provided above between the centers of adjacent first stage inner leads. The second-stage inner lead is located at a longer distance from the die pad than the first-stage inner lead. Then, at a point where the first and second stage inner leads are at a sufficiently long distance from the die pad, the width is made narrow, and the second stage inner lead is inserted between the adjacent first stage inner leads from the narrowed part. , and make the heights of the 1st and 2nd tier inner leads the same. In addition, if the resin sealing method is a two-stage inner lead structure, there is a possibility that the resin will not be sent to every corner with the conventional sealing method.
By injecting resin from multiple directions instead of conventionally from one direction, resin sealing performance comparable to that of a normal package can be obtained.
以」二のように、本実施例によれば、２段式インナーリ
ードを増設することにより、１段目インナーリードだと
考えられるワイヤの問題を解決することができる。As described above, according to this embodiment, by adding a two-stage inner lead, it is possible to solve the problem of the wire that is considered to be the first-stage inner lead.
発明の効果
以上、説明してきたように、本発明にかかる半導体集積
回路のり一トフレームは、従来の１段だけであったイン
ナーリード部に、２段目インナーリードを設ける。これ
により、半導体集積回路の多ピン化、ワイヤ線の接触な
どの問題を十分に解決することができる。Effects of the Invention As described above, in the semiconductor integrated circuit board frame according to the present invention, a second stage inner lead is provided in the inner lead portion, which is conventionally provided with only one stage. This makes it possible to sufficiently solve problems such as the increase in the number of pins in semiconductor integrated circuits and the contact of wire lines.
第１図は本発明の半導体集積回路のリードフレーム形状
を示す平面図、第２図はその断面図、第３図は従来の半
導体集積回路のリードフレーム形状を示した平面図、第
４図はその断面図である。
１１・・・・・・半導体チップ、１２・・・・・・ダイ
パッド、１３・・・・・・１段目インナーリード。１４
・・・・・・２段目インナーリード、１５・・・・・・
１段目ワイヤ、１６・・・・・・２段目ワイヤ。FIG. 1 is a plan view showing the shape of a lead frame of a semiconductor integrated circuit according to the present invention, FIG. 2 is a sectional view thereof, FIG. 3 is a plan view showing the shape of a lead frame of a conventional semiconductor integrated circuit, and FIG. FIG. 11...Semiconductor chip, 12...Die pad, 13...1st stage inner lead. 14
...2nd stage inner lead, 15...
1st stage wire, 16...2nd stage wire.
Claims (1)
を行い接続する２段式のインナーリードをもつ半導体集
積回路のリードフレーム。A lead frame for semiconductor integrated circuits that has a two-stage inner lead that connects to the semiconductor chip by wire bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33402890A JPH04199740A (en) | 1990-11-29 | 1990-11-29 | Lead frame of semiconductor ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33402890A JPH04199740A (en) | 1990-11-29 | 1990-11-29 | Lead frame of semiconductor ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04199740A true JPH04199740A (en) | 1992-07-20 |
Family
ID=18272697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33402890A Pending JPH04199740A (en) | 1990-11-29 | 1990-11-29 | Lead frame of semiconductor ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04199740A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5530281A (en) * | 1994-12-21 | 1996-06-25 | Vlsi Technology, Inc. | Wirebond lead system with improved wire separation |
| US5557143A (en) * | 1993-09-16 | 1996-09-17 | Rohm Co., Ltd. | Semiconductor device having two staggered lead frame stages |
| US5864173A (en) * | 1995-04-05 | 1999-01-26 | National Semiconductor Corporation | Multi-layer lead frame |
-
1990
- 1990-11-29 JP JP33402890A patent/JPH04199740A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5557143A (en) * | 1993-09-16 | 1996-09-17 | Rohm Co., Ltd. | Semiconductor device having two staggered lead frame stages |
| US5530281A (en) * | 1994-12-21 | 1996-06-25 | Vlsi Technology, Inc. | Wirebond lead system with improved wire separation |
| US5864173A (en) * | 1995-04-05 | 1999-01-26 | National Semiconductor Corporation | Multi-layer lead frame |
| US5994768A (en) * | 1995-04-05 | 1999-11-30 | National Semiconductor Corporation | Multi-layer lead frame |
| US6087204A (en) * | 1995-04-05 | 2000-07-11 | National Semiconductor Corporation | Method of making a multi-layer lead frame |
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