JPH04199572A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve contact hole coverage and reduce the difference in level of cells by forming a hole between storage node electrodes, and forming bit lines on the bottom and side of the hole. CONSTITUTION:A stacked-capacitor semiconductor device has storage electrode nodes 7, between which a contact hole 14 is formed. Bit lines 12 are formed on the bottom and side of the hole 14. Specifically, the bit lines are formed only on the bottom and side 15-b of the hole, but not on inner insulating layers. Therefore, device height can be maintained low, and in addition, the coverage of the contact hole is improved to reduce the difference in level of cells.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to wiring of a semiconductor device.

(Prior Art) A conventional semiconductor device will be described below with reference to FIGS. 3, 4, and 5. FIG. 3(a) is a pattern diagram of a conventional semiconductor device; (b) is a pattern diagram of a conventional semiconductor device; FIG. 3(C) is a pattern diagram of a conventional semiconductor device;
4 and 5 are cross-sectional views of the semiconductor device.

Conventional technology STC (stacked capacitor) type DRA
The structure of M cell will be explained. Source 2 on the surface of semiconductor substrate 1
, a drain 3 are formed, and a transfer gate 4 is formed on the semiconductor substrate 1 between them with a gate insulating film 6 interposed therebetween.

In addition, an element separation film 5 is used to separate the two transfer gates 4.
is formed.

A storage node electrode 7 is formed on the drain 3, and a capacitor insulating film 8 and a capacitor electrode 9 are formed thereon. Further, a thin insulating film 10 is formed on the capacitor electrode 9 and the interlayer insulating film 6, and an interlayer insulating film 11' is formed thereon.
is formed, and a bit line 12 is formed thereon. This bit line 12' is formed at the bottom and side surfaces of the contact hole 14 to make contact with the source 2.

Also, the principle of this operation will be explained. When writing,
When a potential corresponding to the information "1" and "0" is applied to the bit line 12' and the potential of the transfer gate 4 is raised to a predetermined potential, a channel is formed between the source 2 and the drain 3, and the drain 3 The potential is transmitted to the storage node electrode 7. A cavater coating 8 is formed on the surface of the electrode 7, and information charges are stored as the old S capacitance between the capacitor electrode 9 and the capacitor electrode 9 formed thereon.

In a conventional semiconductor device, in order to increase the old S capacitance of a cell in order to increase the soft error withstand voltage, it is necessary to thin the capacitor insulating film 8 or increase the surface area of the storage node electrode 7. Since the former method tends to cause dielectric breakdown, the latter method of increasing the surface area does not cause reliability failure. In order to increase the surface area of the storage node electrode 7, in addition to increasing the thickness of the storage node electrode 7 to increase the lateral area as shown in FIGS. 3(b) and 3(c), There is also a method of adopting a fin structure as shown in the figure or a box shape as shown in Fig. 5.

As can be said in any of these cases, as the thickness of the storage node electrode 7 increases, the height of the semiconductor device itself increases. Therefore, the depth of the contact hole 14 of the bit line 12' becomes deeper, leading to deterioration of step coverage of the bit line 12'.

Furthermore, since the height of the device is increased, patterning of wiring becomes difficult.

(Problems to be Solved by the Invention) Conventional semiconductor devices have had problems in that coverage is poor and patterning is difficult when forming wiring layers in contact holes provided in multilayered semiconductor substrates.

In view of the above points, the present invention provides a semiconductor device with good contact hole coverage and reduced cell level differences.

[Structure of the Invention (Means for Solving the Problems)] A semiconductor memory device according to the present invention is a stacked capacitor type semiconductor device in which a hole is provided between storage node electrodes and a bit line is provided at the bottom and side surface of the hole. It is characterized by the formation of

(Function) A hole is formed in a stacked capacitor type semiconductor memory device, and a wiring layer is formed only on the side surface of the hole, reducing the height of the device, resulting in good contact hole coverage and cell It also reduces steps.

(Embodiment) An embodiment of the semiconductor device of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1(a) is a pattern diagram of an embodiment of the present invention, FIG. 1(b) is in the direction of arrow A-A', and FIG. 1(c) is a pattern diagram of an embodiment of the present invention.
is a sectional view taken along the line BB'.

An STC type DRAM cell structure according to an embodiment of the present invention will be explained. A source 2 and a drain 3 are formed on the semiconductor substrate/surface, and a transfer gate 4 is formed on the semiconductor substrate between them with a gate insulating film 6 interposed therebetween.

A storage node electrode 7 is formed on the drain 3 and the insulating film 6. A capacitor insulating film 8 is formed on the surface so as to surround the storage node electrode 7, and a capacitor electrode 9 is formed thereon. Further, a thin insulating film 10 is provided on the capacitor electrode 9 and the interlayer insulating film 6.
, an interlayer insulating film 11 is formed thereon. and,
As shown in FIG. 1(b), a bit line 12 is formed only at the bottom and side surfaces of the contact hole 14 to make contact with the source 2. Also, this bit line 1
2 is a hole 15-a in which the distance between the side surfaces of the storage node electrode 7 is short in the B-B' force direction as shown in FIG. 1(C).
It is not formed in the long hole 15-b, but is formed only in the long hole 15-b. The distance of this long hole 15-b in the B-B' direction is twice the film thickness of the capacitor electrode 9, and the distance between the insulating films 10 and 1
It is made longer than the sum of twice the film thickness of bit line 1 and twice the film thickness of bit line 12 to prevent short circuits between bit lines 12.

Such a structure is formed through the following steps. As shown in the pattern diagram FIG. 2(a), the storage node electrode 7
After forming capacitor insulating film 8 and capacitor electrode 9
, a thin insulating film 10 and an interlayer insulating film 11 are sequentially formed, a contact hole 14 for a bit line 12 is opened, a bit line material 16 is deposited on the entire surface, and a resist 18 is formed over the contact hole 14 of a bit line 2. Apply on top. next,
As shown in FIG. 2(b), anisotropic etching is performed to obtain the state shown in FIG. 2(a). The bit line 11 remains only on the side surface of the hole 15-b. However, in this state, two bit lines 12 are short-circuited, so in order to cut at the terminal end, the bit line material 16 in the shaded area 17 is removed by isotropic etching using photolithography again. In addition,
During this process, care must be taken not to melt the interlayer insulating film If too much and make it flat in order to form a nearly perpendicular step on the side surface of the bit line 12. If it is desired to wire the peripheral circuits using the same material as the bit line 12, a resist may be formed on the wiring portion using the photolithography method as shown in FIG. 2(a).

Also, the write operation of this device will be explained. bit line 1
2 is given a potential according to the information “1” and “0”, and
When the potential of the transfer gate 4 is raised to a predetermined potential, a channel is formed in the semiconductor substrate/surface between the source 2 and drain 3. The potential of the drain 3 is transmitted to the storage node electrode 7. Then, the storage node electrode 7 and the capacitor electrode 9
The information charges are stored in the capacitor insulating film 8 between them as the old S capacitance.

Therefore, in this semiconductor device, since the bit line 12 is formed only on the inner bottom and side surface of the contact hole 14 and the side surface of the hole 15-b without passing over the interlayer insulating film 11, the height of the device is high. The coverage of the contact hole 14 is good without any problems, and the level difference in the cell is also reduced.

Note that this embodiment had a relatively conventional storage node electrode shape, but as shown in FIGS. 4 and 5 of the conventional device, a fin structure was used to increase the surface area of the storage node electrode. Needless to say, the true value of the present invention is demonstrated when the semiconductor substrate has a complex shape such as a box shape, and the thickness of the layer accumulated on the semiconductor substrate increases.

[Effects of the Invention] According to the above results, by using the present invention, contact hole coverage is improved and cell level differences are reduced.

[Brief explanation of the drawing]

1 is a pattern diagram and a sectional view of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a pattern diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a diagram of a conventional semiconductor device. Pattern diagram and cross-sectional diagram of storage device, 4th
FIG. 5 is a cross-sectional view of a conventional semiconductor memory device. 1...Semiconductor substrate. 2... Source area. 3...Drain region. 4... Transfer gate. 7...Storage node electrode. 8...Capacitor insulating film. 9...Capacitor electrode. 11.13...Interlayer insulating film. 12...Bit line. 14...Contact hole. 15-b...Hall. /2 y ◆ 2nd Surrounding Sacrifice 1 m '-= yo' 5th Plan ゝr'''Kugutsu＼ Ri N ＼

Claims (1)

[Claims] In a stacked capacitor type semiconductor memory device,
1. A semiconductor memory device characterized in that a hole is provided between storage node electrodes, and a bit line is formed at the inner bottom and side surface of the hole.