JPH04199523A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04199523A JPH04199523A JP2335353A JP33535390A JPH04199523A JP H04199523 A JPH04199523 A JP H04199523A JP 2335353 A JP2335353 A JP 2335353A JP 33535390 A JP33535390 A JP 33535390A JP H04199523 A JPH04199523 A JP H04199523A
- Authority
- JP
- Japan
- Prior art keywords
- bonding pads
- semiconductor substrate
- row
- pads
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 241000288673 Chiroptera Species 0.000 description 8
- 230000000694 effects Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0605—Shape
- H01L2224/06051—Bonding areas having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
- H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置に関し、詳しくは半導体基板上の
ホンディングバット形状およホンディングバット配列に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and more particularly, to the shape and arrangement of honda bats on a semiconductor substrate.
第３図は従来の半導体装置を示す全体図であり、同図は
半導体基板上のボンディングパッド形状およびボンディ
ングバット配列を示している。図において、（２）は半
導体基板、（３）は半導体基板（２）上に四角形の形状
を持つボンディングパッドである。FIG. 3 is an overall view showing a conventional semiconductor device, and the same figure shows the shape and arrangement of bonding pads on a semiconductor substrate. In the figure, (2) is a semiconductor substrate, and (3) is a rectangular bonding pad on the semiconductor substrate (2).
上記ホンディングバット（３）は半導体基板（２）周辺
に、上記半導体基板（２）の各辺と並行で１列に配置さ
れている。The homing bats (3) are arranged around the semiconductor substrate (2) in a row parallel to each side of the semiconductor substrate (2).
第４図は第３図の一部を拡大した図であり、図において
、（４）はホンディングパット間の間隔である。従来の
半導体装置ではホンディングパット間（４）の間隔を減
少させることによって、ホンディングパット数の増加を
図っている。FIG. 4 is an enlarged view of a part of FIG. 3, and in the figure, (4) is the spacing between the pads. In conventional semiconductor devices, the number of honding pads is increased by reducing the distance between the honding pads (4).
従来の半導体装置、いわばポンディングバッドの形状及
び配列は以上のように構成されているので、ボンディン
グパット数を増やすには、ホンディングバット面積を縮
小するか、ホンディングパット間の間隔を減少させなけ
ればならないという問題点かあった。Conventional semiconductor devices, so to speak, the shape and arrangement of bonding pads are configured as described above, so in order to increase the number of bonding pads, it is necessary to reduce the area of the bonding pads or reduce the spacing between the bonding pads. There was a problem that it had to be done.
この発明は上記のような問題点を解消するためになされ
たもので、ホンディングパソ）へ面積は従来のままで、
ホンディングパット間の間隔を減少させず、ホンディン
グパット数を増加することかできる半導体装置を得るこ
とを目的とする。This invention was made to solve the above-mentioned problems, and the area remains the same as before.
To obtain a semiconductor device capable of increasing the number of honding pads without reducing the interval between honding pads.
この発明に係る半導体装置は、半導体基板上に形成され
ている多角形の形状を持つボンディングバットと、前記
ボンディングバットか半導体基板上に少なくとも１つ以
上配置しているホンディングバット列か、少なくとも１
列以上配置しているものである。The semiconductor device according to the present invention includes a bonding bat having a polygonal shape formed on a semiconductor substrate, and at least one row of bonding bats arranged on the semiconductor substrate.
They are arranged in more than one row.
この発明における半導体装置は、多角形のホンディング
バッドを半導体基板周辺上に、半導体基板各辺と並行に
少なくとも１列以上、各列ごと交互に配置することによ
り、各列のボンディングパット間の間隔を減少させず、
ホンディングバット面積を縮小せずに済む。In the semiconductor device of the present invention, polygonal bonding pads are arranged on the periphery of the semiconductor substrate in at least one row or more in parallel with each side of the semiconductor substrate, and the distance between the bonding pads in each row is increased. without reducing
There is no need to reduce the area of the honda bat.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例による半導体装置の全体図
である。図において、（１）は多角形の形状を持つホン
ディングバット、（２）は半導体基板である。ここでホ
ンディングバット（１）の各列は半導体基板（２）周辺
上に半導体基板（２）の各辺と並行に２列で配置してい
る。FIG. 1 is an overall diagram of a semiconductor device according to an embodiment of the present invention. In the figure, (1) is a homing bat having a polygonal shape, and (2) is a semiconductor substrate. Here, each row of bonding bats (1) is arranged in two rows on the periphery of the semiconductor substrate (2) in parallel with each side of the semiconductor substrate (2).
第２図は第１図の一部を拡大した図であり、図において
、（Ｉａ）、 （Ｉｂ’）は多角形の形状を持ちかつ同
面積を有するホンディングバｙ ｌ’、（４）はホシデ
ィングパット間の間隔である。ホンディングバッド（１
ｂ）はホンディングバット（１ａ）と中心か重ならない
ように配置してあり、ホンデイ〉グバット間（４）の間
隔は等しいものである。Fig. 2 is an enlarged view of a part of Fig. 1. In the figure, (Ia) and (Ib') are polygonal shapes and have the same area, and (4) is a homing board. This is the spacing between the pads. Honding Bad (1)
b) is arranged so as not to overlap the center of the bat (1a), and the distance between the bats (4) is equal.
以上のように、この発明によれは従来のものと同面積を
有する、多角形の形状を持つホンディングバッドを、半
導体基板周辺上に、半導体基板各辺と並行に少なくとも
１列以上、各列ごど交互に配置するように構成したので
、ホンデイ〉グバ。As described above, according to the present invention, boarding pads each having a polygonal shape and having the same area as a conventional one are arranged on the periphery of a semiconductor substrate in at least one row or more in parallel with each side of the semiconductor substrate. I configured it so that the words are arranged alternately, so it's easy to use.
ト面積を縮小させず、かつ各列でのホンディングバット
間の間隔を減少させずに、ホシディシグバソト数を増加
させることかできる。It is possible to increase the number of bats without reducing the bat area and without reducing the spacing between bats in each row.
第１図はこの発明の一実施例による半導体装置を示す全
体図、第２図は第１図の一部を拡大した閃、第３図は従
来の半導体装置を示す全体図、第・１図は第３図の一部
を拡大した図である。
図において、（１）は多角形の形状を持つホンディング
バッド、（Ｉａ）、 （ｌｂ）は多角形の形状を持ちか
一つ同面積を有すホンディングバット、（２）は半導体
基板、（３）は四角形のホンディングバット、（４）は
ボンディングパット間の間隔である。
なお、図中、同一符号は同−又は相当部分を示す。
代理人 大 岩 増 雄
Ｅｌ 図
第２図
ｆｆ１３ 区FIG. 1 is an overall view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is an enlarged portion of FIG. 1, and FIG. 3 is an overall view showing a conventional semiconductor device. is an enlarged view of a part of FIG. 3. In the figure, (1) is a bonding pad having a polygonal shape, (Ia) and (lb) are bonding bats having a polygonal shape or having the same area, (2) is a semiconductor substrate, (3) is a rectangular bonding butt, and (4) is an interval between bonding pads. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa El Figure 2 ff13 Ward
Claims (1)
ディングパッドと、前記ボンディングパッドが半導体基
板上に少なくとも１つ以上配置しているボンディングパ
ッド列が、少なくとも１列以上配置していることを特徴
とする半導体装置。A bonding pad having a polygonal shape formed on a semiconductor substrate and at least one row of bonding pads in which at least one bonding pad is arranged on the semiconductor substrate are arranged. semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2335353A JPH04199523A (en) | 1990-11-28 | 1990-11-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2335353A JPH04199523A (en) | 1990-11-28 | 1990-11-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04199523A true JPH04199523A (en) | 1992-07-20 |
Family
ID=18287581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2335353A Pending JPH04199523A (en) | 1990-11-28 | 1990-11-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04199523A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5635424A (en) * | 1992-07-17 | 1997-06-03 | Lsi Logic Corporation | High-density bond pad layout arrangements for semiconductor dies, and connecting to the bond pads |
| DE10231647A1 (en) * | 2002-07-12 | 2003-10-23 | Infineon Technologies Ag | Connecting pads for integrated circuit have first and second contact surfaces arranged so edge of first and edge of second are facing each other and offset so rows transversely mesh with each other |
-
1990
- 1990-11-28 JP JP2335353A patent/JPH04199523A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5635424A (en) * | 1992-07-17 | 1997-06-03 | Lsi Logic Corporation | High-density bond pad layout arrangements for semiconductor dies, and connecting to the bond pads |
| DE10231647A1 (en) * | 2002-07-12 | 2003-10-23 | Infineon Technologies Ag | Connecting pads for integrated circuit have first and second contact surfaces arranged so edge of first and edge of second are facing each other and offset so rows transversely mesh with each other |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH04199523A (en) | Semiconductor device | |
| JPH0274046A (en) | Semiconductor integrated circuit device | |
| JPH04180668A (en) | Lead frame for semiconductor device | |
| JPS60146364U (en) | light emitting diode array head | |
| JP2024010613A5 (en) | ||
| JPH0541557Y2 (en) | ||
| JPS62199848U (en) | ||
| JPH02273962A (en) | Lead frame | |
| JPH04163928A (en) | semiconductor equipment | |
| JPH0574389A (en) | Lead of fluorescent display tube | |
| JPH0682781B2 (en) | Semiconductor device | |
| JPH01278736A (en) | semiconductor equipment | |
| JPH0450742B2 (en) | ||
| JPS60139290U (en) | hourglass | |
| JPS59162896U (en) | clamping tool | |
| JPH04163953A (en) | Package for semiconductor device | |
| JPH04176158A (en) | Surface-mounting type semiconductor device | |
| KR970012956A (en) | TCP structure | |
| JPS5969746U (en) | underwear | |
| JPS60119803U (en) | Accelerator setting device code plate | |
| JPH0248990U (en) | ||
| JPS6022524U (en) | rotary screen | |
| JPH04119651A (en) | Semiconductor device | |
| JPH0265278A (en) | One-dimensional image sensor | |
| JPH0499052A (en) | Lead frame |