JPH04199243A - Cache storage device - Google Patents

Abstract

PURPOSE:To eliminate the need of making one request to wait even when a read-out and writing requests are simultaneously issued by providing two address arrays. CONSTITUTION:The 1st and 2nd address arrays (AA1 and AA2) 2 and 3 are memories for storing the addresses of data blocks of a cache memory in a main storage device. Thus the two sets of address arrays are provided to the cache memory so that references can be made simultaneously for reading-out and writing. In addition, the data arrays 2 and 3 are divided into plural parts by means of the addresses so that operations of reading-out and writing cycles can be performed independently. Therefore, when reading-out and writing operations are made to different parts of a divided data array, the reading-out and writing operations are executed simultaneously.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a cache storage device used in an information processing device.

[Conventional technology]

A cache storage device having conventional cache storage will be explained. As is well known, a cache storage device is a high-speed, small-capacity storage device that is provided to speed up data reading by an information processing device, and has the function of storing part of the data in the main storage device. do. At this time, the main memory and cache memory are divided into blocks of a certain size, and a small capacity block is used to remember which location on the main memory the data in cache memory belongs to. have memory. This memory is called an address array. Therefore, when an information processing device accesses a cache storage device, it indexes the address array using the address of the data on the main storage device to check whether the desired data exists in the cache storage device. If the desired data exists in the cache storage device, the address of the data in the cache storage device is determined. That is, the address array converts addresses in the main memory to addresses in the cache memory. By the way, in the past, the same address array was indexed for both reading and writing from cache storage, and when reading and writing requests conflicted, one of the requests had to wait.

[Problem to be solved by the invention]

The conventional cache storage device described above has only one address array, so if read and write requests occur simultaneously, it is necessary to make one of the requests wait. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a cache storage device that allows read and write requests to be performed simultaneously even if they are generated in different divided data arrays.

[Means to solve the problem]

A cache storage device according to the present invention is a cache storage device having a cache storage for temporarily storing data stored in a main storage device, the cache storage comprising:
a read address circuit comprising a data array divided by a data width to be read or written at once or a data width multiple times the data width, each having an address register, and holding a read address of the cache memory; A write address circuit holds a write address of the cache memory, and a write address circuit stores an address of data registered in the cache memory, and is supplied with the read address and writes the target data of the read address.
If the block is registered, a first address array outputting an address in the cache memory and a copy of the first address array provided with the write address; If the target data block is registered, the partitioned data block to be read is determined by comparing the read address and the write address with a second address array that outputs the address in the cache memory. determining means for determining whether the divided data array to be written is the same as the divided data array to which data is to be written; and controlling read and write operations for the data array based on the determination result by the determining means. The method is characterized by comprising a cache control means.

[For use]

If the judgment result by the judgment means is negative, the cache control means supplies the read address to the first address array and the divided data array corresponding to the read address, and also supplies the read address to the first address array and the divided data array corresponding to the read address. is supplied to the second address array and the divided data array corresponding to the write address to instruct read and write operations between different divided data arrays at that time, and If the determination results are the same, an operation that gives priority to reading is instructed.

【Example】

Next, the present invention will be explained with reference to the drawings. Referring to FIG. 1, a cache storage device according to an embodiment of the present invention includes a register (V
AAR) 13. This register 13 functions as a read address circuit that holds a read address of cache storage, which will be described later. An address translation buffer (TLB) 1 is a memory for indexing a real address from a virtual address held in a register [3]. First and second address arrays (AAI and AA2)
Memories 2 and 3 store the addresses of the data blocks of this cache storage on the main storage device. The first address array 2 is a part of the virtual address held in the register 13, and is indexed by a part of the real address part that is not affected by the address translation by the address translation buffer 1. Output. A comparator 4 compares this real address with the real address output from the address translation buffer. This comparison result indicates to the cache control circuit 20 the result of determination as to whether or not the target data block exists in this cache storage device. The first buffer 10 is a buffer that stores a real address whose virtual address is translated by the address translation buffer 1 when a write request is issued to the cache memory from the preceding control device. The output of the first buffer 10 is held in register 2. This register 12 functions as a write address circuit that holds the write address of the cache memory. A comparator 5 compares the real address held in the register 12 and the real address output from the second address array 3. This comparison result tells the cache control circuit 20 whether the cache storage device has the target data or not.
Indicates the result of determining whether a block exists. The second buffer 11 is a buffer that stores data until it receives the calculation result from the calculation device and writes it to the cache memory. Oth and first data array (DAO and DA, 1
．． ) 8 and 9 are cache memories divided so that when the least significant bit LSB of the address is "0", the 0th data array 8 is accessed, and when it is "]", the first data array 9 is accessed. It is. In other words, when the address accessing the cache memory is an even number, the 0th data array 8 is accessed, and when the address is an odd number, the 0th data array 8 is accessed.
data array 9 is accessed. Registers 14 and 16 are registers that hold addresses of the 0th and 1st data arrays 10 and 1, respectively. Registers 15 and 17 are registers that hold write data to the 0th and first data arrays 10 and 11, respectively. The first and second selectors 6 and 7 send addresses to the address translation buffer 1 to be sent to the registers 14 and 16, respectively.
This is a selector that determines read or write addresses for the O-th and first data arrays 8 and 9 by switching between the output of the register 12 and the output of the register 12. The third selector 18 is a selector for selecting one of the data read from the 0th and first data arrays 8 and 9 and supplying the selected data to the register]9. Next, the operation of the cache storage device shown in FIG. 1 will be explained in detail with reference to FIG. 2.3.4. FIG. 2 is a truth table showing the operation of the cache control circuit 20 of FIG. 1. When waiting for execution in case 1, register 13 and register 1
There is no valid address on the 2nd side, indicating that there are no requests for reading or writing to the 0th and 1st data arrays 8 and 9. At this time, the first and second selectors 6 and 7 may select either the address conversion buffer 1 side or the register 12 side. Such a state that can be either "0" or "1" is represented by x°. The first stage refers to the portion from register 13 or 12 to register 14 and 16 that operates in one machine cycle. Similarly, the second stage is register 14.16
This refers to the part that operates in one machine cycle from register 19 to register 19. In the second stage of the pending operation in case 1, the write enable signal WE is WE-0 and the 0th or first data array 8 or 9 is in a read cycle. Also,
The third selector 20 is undefined -x. Next, the operation in case of a read request in case 2 will be explained. If there is a valid address in register 13 and its L
Assume that it is SB-0. This means that there is a read request from the preceding control device to the cache storage, and that the necessary data exists in the 0th data array 8. Also, at this time, there is no valid address in the register 12, ie, there is no write request to the cache memory. At this time, in the first stage, the first selector 6 is set to “0”.
In other words, the output of the address translation buffer 1 is the address of the 0th data array 8.Subsequently, in the second stage, the 0th data array 8,
Both the first data array 9 is set as WE-0 in a read cycle, the third selector 18 is made to select the "0" side,
That is, the output of the O-th data array 8 is read into the register 19 and sent to the preceding control device or arithmetic device. Next, the operation in case of a write request in case 3 will be explained. If there is a valid address in register 12 and its L
Assume that the address is SB-0 and there is no valid address in the register 13. This means that there is no request for cache storage from the preceding controller, but there is a write request output from the first buffer 10. At this time, in the first stage, the first selector 6 is set to “1”.
In other words, the output of the register 12 is set as the address of the 0th data array 8.Subsequently, in the second stage, WE-1 of the 0th data array 8, the first data As WE-0 of array 9,
The 0th data array 8 is a write cycle, the 1st data array 9 is a read cycle, and the 2nd buffer 1 is a write cycle.
The operation is to write the operation result stored in 1 to the 0th data array 8 via the register 15. Next, with reference also to FIG. 3, the operation in case 4 where read and write requests occur simultaneously but the LSBs of the addresses are different will be described. LSB-0 of register 13, LSB 1 of register 12
Suppose that At this time, in the first stage, the first selector 6 is set to “0”.
” side, that is, the output of the address conversion buffer 1 is set to the address of the 0th data buffer 8, and the second selector 7 is set to the “1” side, that is, the output of the register 12 is set to the address of the 0th data buffer 8. Make it the address of data buffer 9. In the second stage, by making the 0th data array 8 a read cycle and the 1st data array 9 a write cycle, the read request from the preceding control device and the data stored in the first buffer 10 are processed. Write requests can be executed simultaneously. Next, referring also to FIG. 4, the operation in case 5 where read and write requests occur simultaneously and the LSBs of the addresses are the same will be described. register 13
Assume that the LSB-0 of the register 12 is the LSB-0 of the register 12. At this time, the read request is activated first. In the first stage, the first selector 6 selects the address translation buffer] side, and in the second stage, the 0th data array 8,
A read cycle is performed for both the first data array 9, the third selector 8 is made to select the O-th data array 8 side, and the read operation of the 0-th data array 8 is completed. At the same time that the second stage of the read request operates, the first
The stage acts on the awaited write request. That is, the first selector 6 is made to select the register 12 side, and the
Let this be the address of data array 8 of . Then, in the next machine cycle, the second stage, ie, the 0th data array 8, becomes a write cycle and completes the write request operation. FIG. 5 shows the internal logic circuit of the cache control circuit of FIG. In Figure 5, the symbol in the block is AN
The D gate, the symbol 0 represents an OR gate, the symbol N represents an inverter, and the symbol F represents a flip-flop that synchronizes with the machine clock and takes in the state of the left signal and outputs it as the right signal. The signal 201 indicates that the address held in the register 131ζ is valid and indicates that the first address array 2 or the first address array 2 or the data array 8 or the data array 9 is to be read out. ”.Therefore, signal 20
2 indicates that there is no read request to the 00th data array 8 or the first data array 0, or that there is a read request to the first data array 9. Also, the signal 203 is the 0th
3 data array 8 or first data a! Fi C)
. . , or there is a read request for the 0th data array 8. Signal 204 indicates that the address held in register 2 is valid and that second address array 3 is a hit, i.e.
This signal indicates that there is a write request to the 0th data array 8 or the first data array 9. Therefore, signal 205 indicates that there is a write request for the [-)th data array 8.\. Further, the signals 2 and 6 indicate that there is a request to write to the first data relay 9. As a result, the signal 105 indicates that writing to the 0th data array 8 is to be executed, causes the first selector 6 to select the write address side, and sets the signal 107 to "1", that is, in the next machine cycle. , 0th data array 8
The write operation ends as WE-1. The same applies to signals 106 and 108. The signal 20 near indicates that there is a request to read the first data array 9, and the signal 109 causes the third selector 18 to select the first data array 9.
The output of the data array 9 is sent to the arithmetic unit or advance control unit via one register.

【Effect of the invention】

As explained above, the present invention has two address arrays for cache storage so that reference can be made simultaneously during reading and writing, and the data array is divided into a plurality of parts based on the addresses, each of which can be read and written independently. The advantage of allowing read or write cycles to operate is that read or write operations to cache storage can be performed simultaneously on different partitioned data arrays.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a cache storage device according to an embodiment of the present invention, FIG. 2 is a truth table showing the operation of the cache control circuit in FIG. and write request address conflict 1. Figure 4 is a time chart showing the operation when the read and write request addresses conflict in case 5 of Figure 2. Figure 5 is the time chart of Figure 1. FIG. 3 is a circuit diagram showing details of the cache control circuit of FIG. 1...Address translation buffer (TLB), 2.1st
Address contention array (AAI), 3. Second address contention array (AA2), 4.5. Comparator, 67.. Selector, 8.. 0th data array (1) 7\O), 9
...first data array (DAl,, :1.10.
...1st buffer,] 1, 2nd ('') b, 7 a,]
2 to 17...Register, 18...Selector, 19.
...Register, 20...Cache control circuit. To calculation table To arrow control trap I Fig. 3

Claims (1)

[Scope of Claims] 1. A cache storage device having a cache memory for temporarily storing data stored in a main memory, wherein the cache memory has a data width or a plurality of data widths to be read or written at one time. a read address circuit that holds a read address of the cache memory; a write address circuit that holds a write address of the cache memory; and a write address circuit that holds a write address of the cache memory; A first step that stores the address of data registered in the cache memory, and outputs the address in the cache memory if the read address is supplied and a data block targeted by the read address is registered. 1 address array, and a copy of the first address array in the cache memory if the write address is supplied and the data block targeted by the write address is registered. By comparing the read address and the write address with the second address array that outputs the address, it is determined whether the divided data array to be read from and the divided data array to be written to are the same. 1. A cache storage device comprising: determination means for determining whether or not the data has been received; and cache control means for controlling read and write operations for the data array based on the determination result by the determination means. 2. If the judgment result by the judgment means is negative, the cache control means supplies the read address to the first address array and the divided data array corresponding to the read address, and supplying a write address to the second address array and the divided data array corresponding to the write address to direct read and write operations between the different divided data arrays; 2. The cache storage device according to claim 1, wherein if the determination results by the means are the same, an operation is instructed to give priority to reading.