JPH04196586A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an insulated gate field effect transistor (MOSF).
The present invention relates to a semiconductor device in which an ET) is formed, and particularly relates to a high-speed, highly integrated semiconductor integrated circuit.

[Prior Art] Sea of Gate (Sea of Gate) is described below as a conventional semiconductor device.
An example of a gate array (hereinafter abbreviated as SOG) will be explained.

In a gate array, internal basic gates are laid out in an array inside input/output cells, and a circuit is constructed by connecting the basic gates with wiring.

In a channel type gate array, the transistor area and the wiring area are completely separated, but in contrast, in the SOG type gate array, the entire interior is covered with basic gates, and there is an area dedicated to wiring! It does not have an IA (wiring channel). Therefore, depending on the design, calibration can be performed in both the transistor area and the wiring area, but the basic gate transistor 300 used as the wiring area, as shown in FIG. 3, is not connected to anything, that is, it is in a floating state. The wiring 301 will pass over this.

[Problems to be solved and attempted by 5e Ming] However, in conventional semiconductor integrated circuits, unused transistors are left floating without being connected anywhere, and when a wire is passed over it, the wire There was a problem in that fluctuations in the potential of the wiring affected the transistors below the wiring, causing the wiring capacitance to fluctuate and become unstable.

SUMMARY OF THE INVENTION The present invention is intended to solve these problems and provide a semiconductor integrated circuit that stabilizes wiring capacitance and is faster and more reliable.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a structure in which an insulated gate field effect transistor (MOSFET) is formed on a semiconductor substrate. [Embodiment] An embodiment of the present invention will be described below using an N-channel MOS as an example. Shown in Figure 1.

In the cross-sectional view of FIG. 1, 150, 151, and 152 are parasitic capacitances created due to the wiring 100 passing through. And 153, 154, 155, 156 are N channel MO
This is the parasitic capacitance of S.

The diffusion region of 110 and 111 and the gate of 112 are not connected to the power supply potential, so they are completely floating.
In terms of potential, it is unstable at an intermediate potential. If there is a parasitic capacitance due to the wiring as shown in FIG. 1, the potential of the diffusion region 110.111 and the gate 112 will change due to a change in the potential of the wiring, thereby affecting the depletion region 121, and the depletion region 153. 154.156 parasitic capacitance changes.

Therefore, in order to prevent the parasitic capacitances 153, 154, and 156 from changing, the diffusion region is connected to the substrate potential at 160 and 161 to fix the potential of the diffusion region.

By doing so, the potential of the diffusion region is stabilized, the depletion region is not affected, and the wiring capacitance is also stabilized.

FIG. 2 shows a layout diagram of the embodiment shown in FIG.

The substrate potential of transistor 201 and the diffusion region of unused transistor 200 are connected to wiring 204 and contact 203.

Since this is an N-channel MOS example, the substrate voltage fi201 is VSs.
It is.

Although this embodiment uses an N-channel MOS as an example, similar effects can be obtained in the case of a P-channel MOS by connecting the diffusion region to VDD.

In addition, although we have shown an example configured with MOSFET, MOS
The same applies to B1CMOS in which not only FETs but also MOSFETs and bipolar transistors are formed on the same substrate.

[Effects of the Invention] As explained above, the semiconductor device of the present invention has the following effects by connecting the diffusion regions of transistors that are not used in the semiconductor integrated circuit to the substrate potential.

(1) Since the potential of the expanded P1 area is constant, even if a wire passes over an unused transistor and the potential of the wire changes, the parasitic capacitance of the transistor remains unaffected and remains constant, making it easy to read the wire capacitance. be able to.

Further, this effect is effective mainly for crosstalk between adjacent wirings.

(2) Since the wiring capacitance is constant, high-speed, high-speed and highly integrated semiconductor integrated circuits can be realized, and reliability is improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of one embodiment of the present invention. FIG. 2 is a layout diagram of one embodiment of the present invention. FIG. 3 is a layout diagram of a conventional example. 100...Wiring passing over the transistor 110.111
・・・N゛diffusion region 112... ・Gate 113...Gate oxide film 120...PWELL 121...Depletion region 130...LOCO3 150, 151, 152...Created by the wiring passing through it Parasitic capacitance 153.154.155.156... Parasitic capacitance of transistor 160.161... Connection between diffusion region and substrate potential 200.300... Unused transistor 201...
Substrate power supply (Vss) 202.302... Wiring on the transistor 203... Contact 204... Wiring for connecting the diffusion region and substrate potential 205... Above the diffusion region Applicant: Seiko Epson Corporation Agent: Patent attorney Kisanbe Meiki (and 1 other person) Figure 1/ Figure 2 Figure 3

Claims (1)

[Claims] Insulated gate field effect transistor (MO
A semiconductor device characterized in that, in a structure in which a SFET is formed, a diffusion region constituting the source or drain of a transistor that is not logically connected is connected to the substrate potential of that transistor to have a fixed potential. .