JPH04196462A - Wiring method for multilayer wiring structure and semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring technique for a multilayer wiring structure and a semiconductor device, and particularly to a technique that is effective when applied to a technique for arranging clock wiring in a multilayer wiring structure.

[Conventional technology]

Multilayer wiring technology, or multilayering of metal wiring, has become an essential technology, especially for logic LSIs (Large Scale Integrated Circuits), in order to increase the degree of integration of semiconductor devices and improve the degree of freedom in wiring layout. .

By the way, in such a multilayer wiring technique, since metal wirings are stacked with an insulating thin film interposed therebetween, an indefinite parasitic capacitance is generated between the wirings. Particularly in clock wiring, variations in parasitic capacitance cause clock signal skew (phase shift), and appropriate countermeasures are required.

For this reason, conventionally, for example, Japanese Patent Application Laid-Open No. 60-25463
As disclosed in Publication No. 3, when there is a difference in the length of each of a pair of clock differential wirings, the lengths are made equal by intentionally detouring the shorter side, and the parasitic capacitance for both is reduced. We are trying to avoid the occurrence of skew by keeping the effects the same.

In addition, in the technology disclosed in Japanese Patent Application Laid-open No. 63-78611, a da, mi gate is inserted into a part of the clock wiring to intentionally delay the propagation of the clock signal, thereby reducing the skew caused by variations in parasitic capacitance. trying to avoid it happening.

[Problem to be solved by the invention]

However, in the case of the former conventional technology, although it is true that a skew reduction effect can be obtained by equalizing the parasitic capacitance in a pair of clock differential wirings, the absolute value of the parasitic capacitance increases, so the clock differential wirings in question Another problem arises in that the propagation delay time of the clock signal increases.

Furthermore, in the case of the latter conventional technique, there is a problem that the circuit structure becomes unnecessarily complicated due to the arrangement of the extra dummy gates.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a wiring technique for a multilayer wiring structure that can prevent clock signal skew without increasing propagation delay time or complicating the circuit structure.

Another object of the present invention is to provide a semiconductor device whose operating speed can be improved by reducing the skew of clock signals.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the wiring method for a multilayer wiring structure according to the present invention is to arrange power supply wiring on both sides of a clock wiring in any wiring layer constituting the multilayer wiring structure.

Further, the wiring method for a multilayer wiring structure according to the present invention assigns priorities regarding the arrangement of clock wiring to each wiring layer constituting the multilayer wiring structure according to the types of adjacent wiring layers, and The clock wiring is arranged in a high wiring layer.

In addition, the wiring method for a multilayer wiring structure according to the present invention gives the highest priority to the wiring layer adjacent to the gate laying wiring layer or the power supply flat wiring layer, and preferentially arranges the clock wiring in the wiring layer. It is.

Further, the wiring method of the multilayer wiring structure according to the present invention has the following advantages:
, prohibits parallel wiring between different layers.

Further, the semiconductor device according to the present invention is a semiconductor device having a multilayer interconnection structure, in which power supply interconnections are arranged on both sides of a clock interconnection in an arbitrary interconnection layer.

Further, a semiconductor device according to the present invention is a semiconductor device having a multilayer wiring structure, in which a clock wiring is arranged in a wiring layer where variation in parasitic capacitance between a clock wiring and an adjacent wiring layer is minimized. It is something.

Further, the semiconductor device according to the present invention is constructed by leaving a wiring area in another wiring layer parallel to a clock wiring arranged in an arbitrary wiring layer of a multilayer wiring structure as an empty area.

[Effect]

According to the above-described wiring method for a multilayer wiring structure of the present invention, power supply wirings with small potential changes run parallel to each other on both sides of the clock wiring, so variations in parasitic capacitance in the clock wiring are reduced, and the power supply wiring Since it is shielded from the wiring structure, crosstalk with other clock wiring of the same type is also prevented, and the skew of the clock signal propagating through the clock wiring is reliably reduced.

Furthermore, in general, when a clock wiring is arranged in an arbitrary wiring layer constituting a multilayer wiring structure, it is affected by variations in parasitic capacitance between both the upper and lower adjacent wiring layers. On the other hand, for example, in a logic LS'I, the bottom and top layers of a multilayer wiring structure are gate-covered layers in which wiring is routed vertically and horizontally without any gaps, and power supply wiring is routed almost entirely over the entire surface without any gaps. In a structure consisting of a power supply flat wiring layer that is connected to a gate, the variation in parasitic capacitance for the clock signal line placed in the wiring layer adjacent to the gate filling layer or the power supply flat wiring layer is small, and the influence of only the other adjacent wiring layer is small. Just consider it. In other words, by preferentially arranging the clock wiring in the wiring layer adjacent to the gate filling layer and the power supply flat wiring layer, it is possible to effectively reduce the skew of the clock signal caused by variations in parasitic capacitance between adjacent wiring layers. .

In addition, the parasitic capacitance that occurs in a clock wiring is affected more by parallel wiring than by wiring that intersects the clock wiring, and the influence from other parallel wiring in the same layer is greater when the power wiring runs parallel to the clock wiring. However, it is necessary to consider the influence of parallel wiring in other wiring layers.

Therefore, by prohibiting parallel wiring to the clock wiring in wiring layers other than the wiring layer in which the clock wiring is placed, it is possible to effectively reduce the variation and absolute amount of parasitic capacitance, and ensure the skew of the clock signal. can be reduced.

As a result, compared to measures such as intentionally increasing the length of one side of a pair of clock differential wiring by detouring or inserting a dummy gate, this increases the propagation delay time of the clock signal and reduces the It is possible to accurately prevent clock signal skew without complicating the process.

Further, according to the semiconductor device of the present invention described above, variations in parasitic capacitance between the clock wiring and the stable potential power supply lines located on both sides of the clock wiring are reduced, and the shielding effect of the power supply wiring allows other clock wiring It is also possible to prevent crosstalk between the clock wiring and the like, and to reduce the skew of the clock signal propagating through the clock wiring.

In addition, by preferentially arranging clock wiring in wiring layers adjacent to gate filling layers and power supply flat wiring layers with less variation in parasitic capacitance, it is possible to reduce the variation in parasitic capacitance and reduce the absolute value. can be definitely reduced.

In addition, by leaving the area parallel to the clock wiring as an empty area between the different wiring layers that make up the multilayer wiring structure, there is no parallel wiring that is parallel to the clock wiring and causes an increase in parasitic capacitance, and the skew is effectively reduced. can be significantly reduced.

This eliminates the need to unnecessarily increase the time margin in the operation cycle of a logic circuit, taking into account the skew of the clock signal, and it is possible to realize faster operation.

[Embodiment 1] Hereinafter, an example of a wiring method for a multilayer wiring structure and a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a plan view illustrating an example of the wiring method of the multilayer wiring structure according to the present embodiment in comparison with a conventional case, and FIG. 2 is a part of the multilayer wiring structure of the semiconductor device according to the present embodiment. FIG.

The semiconductor device 110 of this embodiment has a multilayer wiring structure in which a plurality of wiring layers M are stacked with a plurality of interlayer insulating films 11 interposed therebetween. Each wiring layer M includes general signal lines 12.
Clock wiring 13. The source wiring 14 is appropriately arranged.

- Here, in the case of this embodiment, as shown in FIGS. 2 and 1, in any wiring layer M, power supply wirings 14 are placed on both sides of a pair of clock wirings 13 forming clock differential wirings. are arranged in parallel.

That is, since the power supply wiring 14 is generally stable with less change in potential compared to the clock wiring 13 and the general signal line 12, the variation in parasitic capacitance in the clock wiring I3 parallel to the power supply wiring 14 is smaller than that of the conventional power wiring 14. It is smaller than when wiring is done randomly as in .

Furthermore, the clock wiring 13 is shielded by the power wiring J1114, and other general signal lines 12 in the same wiring layer M
The occurrence of waveform distortion due to crosstalk noise with other clock wiring lines 13 of the same type is reliably prevented.

Therefore, the occurrence of skew in the clock signal due to variations in parasitic capacitance, waveform distortion, etc. is reliably suppressed, and it is possible to shorten the time margin of the operating cycle, which is set in anticipation of the occurrence of such skew. , the operating speed of semiconductor devices is improved.

Additionally, compared to countermeasures such as intentionally increasing the length of the clock wiring 13 or inserting an extra dummy gate into the path, the propagation delay time of the clock signal increases due to the increased wiring length. There is also no concern that the circuit structure will become complicated.

[Example 2] FIGS. 3A to 3D are schematic cross-sectional views schematically showing an example of a wiring method and a semiconductor device of a multilayer wiring structure according to another embodiment of the present invention, and FIG. FIG. 1 is a schematic perspective view, partially cut away, of the multilayer wiring structure of the semiconductor device according to the present embodiment.

The semiconductor device 20 of this embodiment, as shown in FIG.
A gate covering layer M1 in which metal wires 22 connecting a plurality of logic gates (not shown) formed on a substrate 21 are stretched in all directions, and a plurality of wiring layers M2 . Wiring layer M3. Wiring layer M4. A plurality of interlayer insulating films 23 are used to connect the wiring layer M5 and the power supply flat wiring layer M6, which is located at the top and has power supply wiring made of metal wiring 22 with a relatively large cross-sectional area stretched vertically and horizontally.
It has a multilayer wiring structure in which the wiring is laminated via the .

Further, the power supply flat wiring layer M6 located at the top layer is covered with an insulation protection llI24.

The wiring layers M2 to M5 other than the gate spread layer M1 and the power supply flat wiring layer M6 are alternately stacked such that the running directions of the metal wirings 22 are orthogonal to each other.

Here, the magnitude of variation in parasitic capacitance such as cross capacitance between the metal wiring 22 in any one of the wiring layers M2 to M5 of such a multilayer wiring structure and the metal wiring 22 in other wiring layers is compared. Then, Fig. 3 FC) and (d)
As shown in , in the case of the metal wiring 22 in the intermediate wiring layer M3 or the wiring layer M4, the wiring layer M2 . M4 and wiring layer MS.

This will be influenced by both of the other metal interconnects 22 that are perpendicular to M5, and the variation in parasitic capacitance will increase.

On the other hand, as shown in FIG. In M6, since the metal wiring 22 is stretched across the entire surface vertically and horizontally, variations in parasitic capacitance due to the gate filling layer M1 or the power supply flat wiring layer M6 are extremely small, and the variation in parasitic capacitance due to the adjacent wiring layer M3 or the wiring is extremely small. The only variation in parasitic capacitance is due to layer M4.

Therefore, in the case of the second embodiment, the clock wiring 22a is preferentially arranged in the wiring layer M2 adjacent to the gate filling layer Ml or the wiring layer M5 adjacent to the power supply flat wiring layer M6, and the clock wiring 22a This prevents the occurrence of skew caused by variations in parasitic capacitance.

As a result, as in the first embodiment, the operating speed of the semiconductor device f120 such as a logic LSI can be improved without complicating the wiring structure.

[Embodiment 3] FIG. 5, FIG. 7, FIG. 6, and FIG. 8 are schematic diagrams showing an example of a wiring method of a multilayer wiring structure, a semiconductor device 20A, and a semiconductor device 20B, which are other embodiments of the present invention. They are a sectional view and a schematic perspective view.

For example, in the wiring layers M2 to M5 of the multilayer wiring structure exemplified in Example 2, the metal wirings 22 are normally arranged alternately so as to intersect with each other, so that any wiring layer (for example, wiring layer M2 or The parallel wiring that causes large variations in parasitic capacitance with respect to the clock wiring 22a arranged in the wiring layer M5) may be not only adjacent wiring within the same wiring layer but also parallel wiring between different layers.

In the former case, parallel wiring makes it possible to reduce variations in parasitic capacitance by running the power supply wiring 14 in parallel, as illustrated in Embodiment 1, but in the latter case, for example, an automatic wiring system (not shown), etc. This can be prevented by prohibiting the placement of parallel wiring in the wiring layer above (wiring layer M4 in this case) or the wiring layer below (wiring layer M3 in this case) the clock wiring 22a in a library or the like.

That is, for example, FIGS. 5 and 6, or FIG.
As shown in the figure and FIG. 8, the semiconductor device 20A (
In the semiconductor device 20B), in the wiring NM4 (wiring layer M3) whose wiring direction is parallel to the wiring layer M2 (wiring layer M5) in which the clock wiring 22a exists, the wiring layer M2
(M5) The arrangement of the metal wiring 22 in the area directly above (immediately below) the clock wiring 22a is prohibited, and the empty area El
(Free area E2).

Such a wiring method can be easily realized by designing the capacitance of the wiring channel (area) on the assumption that the fixed area where the clock arrangement 1122a is routed is only crossed by general signal lines.

In this way, by prohibiting the placement of parallel wiring in other wiring layers above and below the arrangement area of the clock wiring 22a, variations in parasitic capacitance due to the clock wiring 22a and other wiring being parallel are reduced. Therefore, the skew of the clock signal propagating through the clock wiring 22a can be reliably reduced.

Thereby, it is possible to shorten the time margin in consideration of skew in the operation of the semiconductor devices 1t2OA and 20B, and it is possible to improve the operating speed of the semiconductor devices 2OA and 20B.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, the number of wiring layers constituting the multilayer wiring structure is not limited to six as exemplified in each of the above embodiments, but may be more than six or less than six.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

That is, according to the wiring method for a multilayer wiring structure according to the present invention, it is possible to reliably reduce the skew of the clock signal in the clock wiring without increasing the propagation delay time or complicating the circuit structure.

Furthermore, according to the semiconductor device of the present invention, the skew of the clock signal is reliably reduced, the time margin in which the skew is taken into account in the operating cycle can be shortened, and the operating speed is improved.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an example of a wiring method for a multilayer wiring structure according to a first embodiment of the present invention in comparison with a conventional method, and FIG. 2 is a multilayer wiring of a semiconductor device according to a first embodiment of the present invention. A schematic perspective view showing a part of the structure broken away, FIGS. 3(a) to (
d) is a schematic cross-sectional view schematically showing an example of the effect of the wiring method for a multilayer wiring structure according to the second embodiment of the present invention, and FIG. FIG. 5 is a cross-sectional view showing an example of a wiring method for a multilayer wiring structure according to a third embodiment of the present invention, and FIG. 6 is a schematic perspective view showing a semiconductor device according to a third embodiment of the present invention. FIG. 7 is a schematic perspective view showing a partially broken multilayer wiring structure, and FIG. Example 3 of the present invention
FIG. 2 is a schematic perspective view partially cut away of a multilayer wiring structure of a semiconductor device. 10... Semiconductor device, 11... Interlayer insulating film, 12.
...General signal line, 13...Clock wiring, 14...
Power wiring, 20.2. OA, 20B... semiconductor device,
21... Substrate, 22... Metal wiring, 22a... Clock wiring, 23... Interlayer insulating film, 24... Insulating protective film, El, Ej... Vacant area, M... Wiring Layer, M
l...Gate filling layer, M2-M5...Wiring layer,
M6...Power supply flat wiring layer. Agent Patent Attorney Dai Tsutsui Wa 3F27 (a) (b) (C)
(d) 22a: Kuro・
link wiring

Claims (1)

[Scope of Claims] 1. A wiring method for a multilayer wiring structure, characterized by arranging power supply wiring on both sides of a clock wiring in any wiring layer constituting the multilayer wiring structure. 2. Giving priority to each wiring layer constituting the multilayer wiring structure in terms of clock wiring placement according to the type of adjacent wiring layer, and placing the clock wiring in the wiring layer with the highest priority. A wiring method for a multilayer wiring structure characterized by the following. 3. The multilayer wiring structure according to claim 2, wherein the highest priority is given to the wiring layer adjacent to the gate spread wiring layer or the power supply flat wiring layer, and the clock wiring is preferentially arranged in the wiring layer. wiring method. 4. A wiring method for a multilayer wiring structure, characterized in that parallel wiring between different layers is prohibited with respect to clock wirings or between clock wirings and other wirings. 5. A semiconductor device having a multilayer wiring structure, characterized in that power supply wiring is arranged on both sides of a clock wiring in an arbitrary wiring layer. 6. A semiconductor device having a multilayer wiring structure, characterized in that the clock wiring is arranged in a wiring layer where variation in parasitic capacitance between the clock wiring and an adjacent wiring layer is minimized. . 7. A semiconductor device characterized in that a wiring area in another wiring layer parallel to a clock wiring arranged in an arbitrary wiring layer of a multilayer wiring structure is made into an empty area.