JPH04195091A - Display controller - Google Patents

Abstract

PURPOSE:To reduce the electric power consumption of the display controller by providing a frequency difference so as to increase an operating frequency when there is a change in display contents and to lower this frequency when there is no change. CONSTITUTION:A refresh timing generation circuit 33 of the display controller 3 generates a control signal for a low-speed operation by the frequency-divided clock of a basic clock CLOCK when there is not change in the display contents of a display device 1. The display data are written into a video memory 2 by an MEMW signal and a flip-flop 34 is reset when the display contents change. A CLKSEL signal attains a low level and a multiplexer 32 selects the basic clock CLOCK from the outside until a VSYNC signal rises to a high level. A control signal for a high-speed operation is then generated. The electric power consumption when there is no change in the display contents is reduced in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a display control device particularly suitable for use in a portable computer.

(Prior Art) In the field of personal computers, a desktop type display device is called a CRT (cathode).
ray tube) is a lap tube type, L CD (Li,quid Crystal Di
spray), P D P (Plasuia Dis
Flat type devices such as play panels are used as standard. Since these display devices operate dynamically, they obtain a stable display by receiving (refreshing) control signals and display data at a constant frequency.

Therefore, the display control circuit constantly reads content to be displayed from the video memory, generates display data together with a control signal for the display device, and repeats the operation of transmitting the generated display data to the display device.

(Problems to be Solved by the Invention) According to the conventional example described above, the display control circuit always reads the content to be displayed from the video memory even though the display content is not changing, and generates display data together with the control signal. There is a need to. Since these control circuits operate at high speed, they consume relatively large amounts of power. Therefore, laptop-type personal computers and the like that operate on batteries have problems such as a short operating time.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a display control device that achieves low power consumption by providing a difference in operating frequency between when there is a change in display content and when there is no change in display content. purpose.

[Structure of the Invention] (Means for Solving the Problems) A display control device of the present invention includes a display control unit that performs refresh control on a display device according to a plurality of frame frequencies, and a display control device that detects the presence or absence of a change in display content. means for stopping or switching to low-speed operation the reading of display data from the video memory and the generation of display data and control signals for the display device when there is no change in the display content; The present invention is characterized in that it comprises means for resuming or switching to high-speed operation the reading of display data from the video memory and the generation of display data and control signals for the display device.

(Function) With the above configuration, when it is detected that there is no change in the display content, reading and generating display data from the video memory is stopped or switched to low-speed operation, and when there is a change, the display data is read from the video memory. Resume reading or generating data or switch to high-speed operation. According to the present invention, the display circuit stops or operates at low speed when there is no change in the displayed content, resulting in low power consumption and a long battery operation time.

Also, the display data is written from the system to the video memory ε
This time is shared with the video memory read cycle for refreshing. Therefore, when refreshing at a low speed, the share of write cycles from the system increases, so that writing can be completed in a short time.

(Example) Embodiments of the present invention will be described below using the drawings.

FIG. 1 is a block diagram showing an embodiment of a display system to which the present invention is adopted. In the figure, 1 is a static display device, and 2 is a video memory that holds display data.

A display control device 3 generates control signals for reading/writing the video memory 2, generates display data, generates timing control signals for the display device 1, and the like.

FIG. 2 is a block diagram showing the internal configuration of the display control device 3 in the system of FIG. 1. In the figure, numeral 31 is a frequency dividing circuit that divides the basic clock CLOCK supplied from the outside. 32 inputs the basic clock CLOCK and the divided clock output from the frequency dividing circuit 31, and outputs one of them as a clock selection signal CLKSEL (CL
KSEL signal). Reference numeral 33 denotes a timing generation circuit that generates a read timing signal for the video memory 2 and a control signal for the display device 1 shown in FIG. 34.35 is a flip-flop (F/F)
, 36 are AND circuits.

37 is a flip-flop 34, 35 and an AND circuit 3
6, which generates a tally selection signal CLKSEL based on a memory write signal MEMW (MEMW signal) and a vertical retrace signal VSYNC (VSYNC signal).

FIG. 3 is a timing chart showing the operation of the embodiment of the present invention, in which the clock selection signal CLK by the display control device 3 is
3 is a timing chart for explaining generation of SEL. It is assumed that the signal names shown in the figure match those in FIGS. 1 and 2.

The operation of the embodiment of the present invention will be explained below.

First, the reset input terminal (R) of the flip-flop 34
is the memory write signal (memory write command > MEM
W (MEMW signal) is input. Further, the data input (D) of the flip-flop 34 is pulled up to the power supply voltage VDD, and the vertical retrace signal VSYNC is input to the clock input (CK). Normally, the Q output a of this flip-flop 34 is such that the data input (D) is the power supply voltage V.
Since it is pulled up to DD and has a low level of the MEMW times signal of the reset manual input (R input), it is maintained at a high level by the VSYNC signal of the clock input (CK). Therefore, the Q output of the flip-flop 35 which uses the Q output a of the flip-flop 34 as the data input (D)
The output is also at a high level, and flip-flop 3
AND circuit 36 that takes the AND of the Q outputs a and b of 4.35
The CLKSEL signal which is the output of is also at high level.

When the CLKSEL signal is at a high level, the multiplexer 32 selects the output (divided clock) of the frequency dividing circuit 31 and supplies it to the refresh timing generating circuit 33 . The refresh timing generation circuit 33 generates a low-speed operation control signal using a frequency-divided clock (a frequency-divided clock of the basic clock CLOCK).

When the display contents change, the system writes the display data into the video memory 2 according to the memory write signal MEMW. At this time, the flip-flop 34 is M
It is reset by the EMW signal, and its Q output a becomes low level. As a result, the CLKSEL signal output from the AND circuit 36 also becomes low level. When the CLKSEL signal is at a low level, the multiplexer 32 selects the externally applied basic clock CLOCK and supplies it to the refresh timing generation circuit 33.

The refresh timing generation circuit 33 generates a high-speed operation control signal using this basic clock CLOCK.

The flip-flop 35 specifies the next frame after the frame that has been written to the video memory 2, and even if the Q output a of the flip-flop 34 becomes high level, the next VSYNC signal (the next VSYNC signal remains at low level (until it reaches high level). The output (CLKSEL signal) of the AND circuit 36 becomes the opening level. Then, when the Q output of the flip-flop 35 becomes high level, the output of the AND circuit 36 (CLKSEL signal) also becomes high level, and the divided clock from the frequency dividing circuit 31 is again selected by the multiplexer 32 to generate a refresh timing. It is supplied to the circuit 33. The refresh timing generation circuit 33 generates a control signal for low-speed operation using the divided clock from the frequency dividing circuit 31.

In addition, if you want to completely stop the refresh timing,
By eliminating the frequency dividing circuit 31 and using a gate circuit which inputs the basic clock CLOCK in place of the multiplexer 32, the clock (CLOCK) to the refresh timing generation circuit 33 is gated by the CLKSEL signal.
It is sufficient to stop the supply of K).

By the way, according to the present invention, when display data is written from the system to the video memory 2, it is shared with the read cycle of the video memory 2 for refreshing. Therefore, C
By using the Q output of the flip-flop 35 as the LKSEL signal, the share of the write cycle becomes larger than the read cycle of low-speed operation, so that writing can be completed in a short time.

[Effects of the Invention] As described above, according to the present invention, when there is no change in display content, the display control device stops or operates at low speed, resulting in low power consumption and long battery operation time. Furthermore, when display data is written from the system to the video memory, it is shared with the video memory read cycle for refreshing.

Therefore, when refreshing at a low speed, the share of write cycles from the system increases, so that it is possible to finish writing in a short time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a display system to which the present invention is adopted, FIG. 2 is a block diagram showing the internal configuration of the display control device shown in FIG. 1, and FIG. It is a timing chart showing the operation. DESCRIPTION OF SYMBOLS 1... Display device, 2... Video memory, 3... Display control device, 31... Frequency division circuit, 32... Multiplexer, 33... Refresh timing generation circuit,
34, 35...Flip-flop, 36...AND circuit, 37...Clock selection signal generation circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 1 5YNC 2nd mouth

Claims (1)

[Claims] Display control means for performing refresh control on a display device according to a plurality of frame frequencies; means for detecting whether or not there is a change in display content; and means for reading display data from a video memory and displaying when there is no change in display content. Means for stopping or switching to low-speed operation the generation of control signals for data and display devices, reading display data from video memory when there is a change in display content, and controlling signals for display data and display devices; 1. A display control device comprising means for restarting generation or switching to high-speed operation.