JPH04192732A - Video signal transmission system - Google Patents

Abstract

PURPOSE:To prevent a picture from being distorted in the middle even when controlling the picture by slipping the read position of data by execution phase comparison with a video frame pulse in a reproducing system and slipping the read position of picture data for the unit of one picture when phase difference is more than a fixed value. CONSTITUTION:The output of an oscillator 31 in a receiver is inputted to a video frame generation circuit 27, and a frame pulse is generated. In a judgment circuit 30, the frame pulse outputted from this video frame generating circuit 27 and the output of a destuff signal integration circuit 26 are received, the phases of the both outputs are compared and when the phase difference reaches the prescribed value, a frame slip signal is generated and applied to a memory buffer 25. In the case of receiving the frame slip signal, the memory buffer 25 moves the read position to the head position of the next picture and starts reading from here even when the reading of the picture data is in the middle of the picture. Thus, the output of the memory buffer 25 is slipped for the unit of the frame, and the state of out-of-vertical synchronism or the like for the picture caused by enlarging the phase difference can be prevented.

Description

[Detailed Description of the Invention] "Industrial Field of Application of the Invention" The present invention relates to a system for transmitting television video signals using a transmission line, and in particular can eliminate image disturbances on the receiving side. The present invention relates to a video signal transmission system.

(Prior art) For example, a wired transmission line is used as in a videophone [2] As a video signal transmission device for transmitting a television image signal (video signal), the transmitting device, the transmission path, and the receiving device each have an oscillator, There is a device that performs transmitting and receiving operations in accordance with the oscillation clock signal, and also makes each of them asynchronous.

Autumn 1: In videophone systems, the video signal that is the signal to be transmitted by the system consists of image data and blanking, and the transmitting device converts the video signal into image data in order to compress the blanking of the video signal and send it to the transmission path. Transmit in frames. At this time, the image data is transmitted on the transmission line at a slightly faster operating clock than on the transmission side compared to the sending speed of the transmitting device, so the data on the transmission line may contain empty data, which causes a problem. The image data to be transmitted is temporarily held in a memory, and the image data on this memory is read out in accordance with the frame on the transmission path, and where there is insufficient data, stuff bits are multiplexed and output.

The receiving device separates stuff bits and the like from the data received via the transmission path, writes it in a memory, reads it out in accordance with the cycle of video frames during video playback by the receiving device, and reproduces the video signal. At this time, in the receiving device, if the phase between the input side (transmission line side) and the output side (reading side of the receiving device) of the memory shifts and the phase difference increases, the read data may be duplicated or missing, resulting in image information being lost. To protect against this, the data is slipped because it causes quality degradation, but in conventional devices, when the phase difference between writing and reading exceeds a certain amount, the data is slipped by a certain number of bits. In the case of Zunai), if video is played back by television scanning, a certain number of lines of video signals will be skipped.

In this case, it is inevitable that a slip occurs in the middle of the image data that makes up one screen, and in such a case, the middle of the image is missing, resulting in a partially clogged image.
The blanking period ends up in the middle of the screen, causing screen disturbances such as a TV screen when horizontal synchronization is lost (7).

(Problems to be Solved by the Invention) As mentioned above, the transmitting side, the transmission line side, and the receiving side each have their own synchronization systems, and on the transmitting side, video signals are stored in the transmission memory in frame units, and the transmission line -C has its own synchronization system. 1- frame, stuff bits are added to the area where the data is empty, and the data is sent out to the transmission path.The receiving side receives this, removes the stuff bits, and stores it in the receiving memory. There is a video signal asynchronous transmission system in which the video signal is reproduced by reading the image data frame by frame from the reception memory in accordance with the video reproduction system on the receiving side. When sending a video signal from the transmitting side to the receiving side via a transmission line, the video signal is converted into image data and stored in memory in frame units, read out and transmitted at the transmission speed of the transmission line, and the receiving side processes this image data. is read into a memory, read out in synchronization with the video frame in the video playback system on the receiving side, and converted into a video signal.

However, the memory capacity on the receiving side is plentiful (not just a few frames, but only a few frames at most), so the question is whether there is a balance between the amount of data received and the amount of data that can be sent to one hospital.

In general, the transmission rate on the transmission line is higher than the data supply rate on the transmitting side and the memory read rate on the receiving side, so reading on the receiving side is based on the video frame on the transmission line and the memory read rate on the receiving side. This is because when the phase difference with the video frame of the playback system exceeds a certain amount, a slip (skip of the read address) of a certain number of bits is automatically caused when reading from the memory on the receiving side. , avoid that the place where the slip occurs is in the middle of the image data1', t
+-+res, in this case, the received image will be distorted 1.
1 There was a problem called iP.

Therefore, the object of the present invention is to provide a video signal asynchronous transmission system that does not cause (-1 disturbance to the image) even if the phase difference increases and slip occurs.

[Configuration of the Invention (Means for Solving the Problem) In order to achieve the above object, the present invention is configured as follows. In other words, the transmitting/receiving side and the transmission line operate based on the clock signal of each system to exchange data, and the transmission data in the transmitting system is adjusted due to the difference in transmission speed between the transmitting system and the transmission line. In a video signal transmission system in which stuff bits are added to regular positions in the video frame period, the receiving side includes a separation means for separating the stuff bits from the video signal data from the received data, and a means for generating a video frame synchronization signal used for video playback, and a capacity for multiple screens to temporarily hold the video signal data separated by the separation means, and to control the playback speed of the video playback system on the receiving side. and a memory that reads this from the beginning position of the next frame when a slip command is received, and the video frame synchronization signal and the separated stuff pin], the received data and the video of the video playback on the receiving side. The apparatus further includes determining means for determining a frame phase difference and issuing a slip command to the memory when the phase difference exceeds a predetermined amount.

(Function) In such a configuration, the transmitting/receiving side and the transmission line operate based on the clock signal of each system to exchange data, and the transmission data in the transmitting system is transmitted on the transmission line for this transmitting system. Stuff bits for adjustment due to speed differences are added at fixed positions in the video frame period. Then, on the receiving side, the separating means separates the stuff bits and video signal data from the received data [2. The video signal data is temporarily stored in a memory.

Then, the memory reads the video signal data in synchronization with the video frame synchronization signal used for video playback on the receiving side,
On the other hand, the determining means calculates the phase difference between the received data and the video frame of the raw video 11f on the receiving side from the video frame synchronization signal and the separated stuff bits, and if the phase difference exceeds a predetermined amount, a slip occurs. A command is issued and applied to the memory. When the memory receives this slip command, the stored video data is read out from the top position of the next screen.

In the present invention, when stuff bits are multiplexed on the transmitting side, since the positions of the stuff bits are fixed as one frame period, the receiving device reproduces the frame frequency from the separated stuff bits. Then, the phase of this reproduced frame frequency and the video frame pulse generated by the receiving device is compared, and when the phase difference exceeds a certain amount,
When reading the received video signal data from the memory, it is possible to prevent the image from being disturbed by slipping it by one screen in synchronization with the frame normals.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. First, we will explain the transmission system.

FIG. 1 is a block diagram showing the configuration of the transmitting device. In the figure, 1 is a video signal input terminal, and 2 is an analog/digital conversion circuit (hereinafter referred to as an A/D conversion circuit), which is a video signal input terminal. ] An analog video signal inputted from the A/D conversion circuit 2 is converted into a digital signal by the A/D conversion circuit 2. Reference numeral 3 denotes a video synchronization signal separation circuit, which receives the digital signal output from the A/D conversion circuit 2 and separates a video synchronization signal (frame synchronization pulse). 4
is a video frame generation circuit, and the video synchronization f, -3+ separated by the video same period signal separation circuit 3 is
A frame signal is generated based on J.

G is a gate, which allows the output of the A/D conversion circuit 2 to pass through while receiving the frame signal generated by the video frame generation circuit 4. A memory buffer 5 is used to store the output of the A/D conversion circuit 2 received via the gate G.

Reference numeral 6 represents a transmission line CLK input terminal for inputting a transmission line CLK (tallock) signal, and 7 represents a frame counter for MUX (multiplexing). The MUX frame counter 7 receives and counts the transmission line CLK signal used in the transmission line, and generates a signal for frame synchronization for the MUX. Further, IO is a stuff bit insertion circuit, which receives the frame signal generated by the video frame generation circuit 4 and the output of the MUX frame counter 7, compares the difference between the two, and when this reaches a predetermined value, inserts a stuff pulse. This is what is output.

8 is a multiplexing circuit (hereinafter referred to as MUX), which receives the rough pulse and the read image data from the memory buffer 5 and outputs the frame output from the MUX frame counter 7. These are multiplexed in synchronization with a synchronization signal and sent out to the transmission path.

In a transmitting device having such a configuration, when a video signal is input from the video signal input terminal, this video signal is input to the A/D
The conversion circuit 2 converts it into a digital signal. The video signal (image data) converted into a digital signal is input to a video synchronization signal separation circuit 3, where the synchronization signal is separated. The separated synchronization signal is input to the video frame generation circuit 4, and the video frame generation circuit 4 generates a frame signal corresponding to the frame period of the video from the separated input synchronization signal.

On the other hand, the digitized video signal output from the A/D conversion circuit 2 is masked by the frame signal by passing through gates 1-G gate-controlled by the frame signal, and only the image data is transmitted. is output and sent to the memory buffer 5, and written into this memory buffer 5.

Also, since the transmission line CLK (clock signal) input from the transmission line CLK input terminal 6 is given to the MUX frame counter 7, the MUX frame counter 7 performs counting operation using this transmission line CLK. Then, it outputs a synchronization signal synchronized with the transmission frame on the transmission path based on the transmission path clock and a synchronization clock synchronized with the bits of the transmission frame.

This synchronization signal and the output of the video frame generation circuit 4 are sent to the stuff bit insertion circuit 10, where the phase difference between the two is compared. When a predetermined phase difference is reached, stuff bits are output from the stuff bit insertion circuit 10. Ru. The stuff bits and data read from the memory buffer 5 at the timing of the transmission line clock are applied to the MUX 8, multiplexed, and output from the transmission line output terminal 9 to the transmission line.

In this way, while writing image data to the memory, the transmitting side reads and transmits it at the transmission speed of the transmission line. Insert a bit to compensate for the inconvenience.

Next, the receiving system will be explained. FIG. 2 is a block diagram showing an embodiment of the receiving device in the system of the present invention, and 21
is the transmission line CLK input terminal that receives the transmission line CLK, 2
j is a frame counter, 22 is a transmission line manual signal terminal, 2
3 is a demultiplexer (DMUX), 24 is a destuff circuit, 25 is a memory buffer, 26 is a destuff signal integration circuit, 27 is a video frame generation circuit, 28 is a digital/analog conversion circuit, 29 is a video signal output terminal, 3
0 is a judgment circuit.

The frame counter 21 is a circuit that operates according to the transmission line CLK input from the transmission line CLK input terminal 20 and generates a frame synchronization signal.
3 is a circuit that separates the transmission frame received via the transmission line input signal terminal 22 into image data, stuff bits, and the like.

The destuff circuit 24 transfers the image data from the stuff bits separated by the DMUX 23 to the memory buffer 24.
This is a circuit that generates a signal to be written to 5.

The destuff signal integration circuit 26 is a circuit that integrates (integrates) the output of the destuff circuit 24 to generate an integrated output that indicates the position of the stuff bit. This is to generate synchronization pulses for video frames in response to the generated clock.

The determination circuit 30 is a circuit that receives these synchronization pulses and integrated output, compares the phase difference between the two, and generates a frame slip signal when the phase difference reaches a predetermined value.

The memory buffer 25 is an image memory having a capacity for multiple screens (fields or frames), and is a DMU
It has a function of storing the image data separated by X 23 and sequentially reading out the image data in synchronization with the video frame signal output from the video frame generation circuit 27 and in accordance with television scanning.

Also, when the memory buffer 25 receives a frame slip signal, the memory buffer 25 displays the next screen (next field or next frame).
The function of jumping to the first address of the image data and sequentially reading image data from that address in accordance with television scanning is set to H.

The digital/analog conversion circuit 28 is the memory buffer 2
This is a circuit that converts the image data read out from 5 into an analog signal and outputs it as a video signal. This video signal is output from the video signal output terminal 29 as an output of the receiving device.

In such a configuration, the transmission line CL K input terminal 21
The frame counter 21 operates according to the CLK for the transmission path inputted from the frame counter 21 to generate a frame synchronization signal. The D MUX 23 is activated by this frame synchronization signal output, and separates the received data input from the transmission line input signal terminal 22 into image data and stuff bits.

Among these, the stuff bits are reproduced at the frame frequency by the destuffing signal integration circuit 26 at the same time as the destuffing circuit 24 generates a signal for writing the image data into the memory buffer 25. The output of the oscillator 31 of the receiving device is input to the video frame generation circuit 27, and the video frame generation circuit 27 generates a frame pulse from this. The determination circuit 30 receives the frame pulse output from the video frame generation circuit 27 and the output from the destuff signal integration circuit 26, compares the phases of the two, and selects a frame slip signal whose phase difference reaches a predetermined value. generated and provided to the memory buffer 25.

When the frame slip signal is received, the memory buffer 25 moves the image data to the beginning position of the next screen and starts reading from there, even if the image data is read in the middle of the screen.

As a result, the output of the memory buffer 25 is slipped on a frame-by-frame basis, and it is possible to avoid a situation such as vertical out-of-synchronization of the screen (a phenomenon in which the screen moves in the vertical direction) due to an increase in the phase difference.

The image data read from the memory buffer 25 is transferred to D/
It is converted into an analog signal by the A conversion circuit 28 and output as a video signal.

FIG. 3 is a timing chart showing the operation of an embodiment of the present invention, in which (a) is a video signal frame, (b) is a frame of a transmission line signal, and (c) is a timing chart of the video No. 15 and the transmission line signal. phase difference, (d) is the position of the stuff bit, (e) is the second
The product punctuation output by the destuff signal integration circuit 26 in the figure, (f
) is a video frame pulse generated by the video frame generation circuit 27 in FIG.

Video signal frame (a) and transmission line signal frame (b)
The phase difference increases at the image data and decreases at the blanking, so it becomes as shown in (e). Therefore, the positions of stuff bits caused by a phase difference of a certain amount or more are fixed as shown in ([I). When this signal is separated by a receiving device and passed through the destuff signal integration circuit 26 in FIG. 2, a signal at the frame synchronization frequency shown in (e) is reproduced.

This (e) is compared with (f'), which is the output signal of the video frame generation circuit 27 in FIG. , it will be possible to eliminate the phenomenon of screen drift and display a clear screen.

In this way, this system converts the video signal into data and transmits it, and the receiving side sequentially writes the received data into the memory, reads it out at the playback speed of the playback system, and reproduces the image. When multiplexing stuff bits, the position of the stuff bits is fixed as the frame period.The stuff bits separated by the receiving device are integrated in the signal integration unit, and the frame frequency is reproduced. Compare the phase of the video frame pulse generated by the frame frequency with the frame frequency reproduced by the signal integration section, and when the phase difference exceeds a certain amount, reading from the memory is performed for one screen in synchronization with the frame pulse.
By starting from the position of the slip and replaying, it is possible to prevent disturbances from appearing in the image.

The present invention is not limited to the embodiments described above and shown in the drawings, but may be modified as appropriate without changing the gist thereof.
It can be implemented as follows.

[Effects of the Invention] As explained above, in the present invention, the stuff bits are used to reproduce the frame frequency of received data in the receiving system,
The phase is compared with the video frame pulse = 18- in the reproduction system, and when the phase difference exceeds a certain level, the image data readout position is slipped in units of one screen. There is a phase difference between the speed at which the data is captured and the speed at which the captured data is read and played back, and even when the data readout position is adjusted by slipping after a certain period of time, there is no disturbance in the middle of the image. Benefits obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a transmitting device showing an embodiment of the present invention, FIG. 2 is a block diagram of a receiving device showing an embodiment of the present invention, and FIG. 3 is a timing chart showing an example of the operation of the device of the present invention. It is. 1... Video signal input terminal, 2... Analog/digital conversion circuit, 3... Video synchronization signal separation circuit, 4... Video frame generation circuit, 5, 25... Memory buffer,
6, 20... Transmission line CL K input terminal, 7... Frame counter for MUX, 8... Multiplexer circuit (MUX)
, 9 Transmission line output terminal, 10 Stuff bit insertion circuit, 21 Frame counter, 22 Transmission line input signal terminal, 23 Demultiplexer circuit (DMUX
), 24...Destuff signal integration circuit, 26...Destuff signal integration circuit, 27...Video frame generation circuit, 28.Digital/analog conversion circuit, 29...Video signal output terminal, 30... Judgment circuit, 31... oscillator. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] The transmitting/receiving side and the transmission line operate based on the clock signals of each system to exchange data, and the transmission data in the transmitting system is based on the difference in transmission speed between the transmission system and the transmission line. In a video signal transmission system that adds stuff bits for accompanying adjustment at fixed positions in a video frame period, the receiving side includes a separating means for separating the stuff bits and video signal data from received data; means for generating a video frame synchronization signal used for video playback on the receiving side, and having a capacity for multiple screens to temporarily hold the video signal data separated by the separation means and used for video playback on the receiving side. A memory that reads this in accordance with the playback speed of the system and reads from the beginning of the next frame when a slip command is received, and a memory that reads the received data and video playback on the receiving side from the video frame synchronization signal and the separated stuff bits. 1. A video signal transmission system, comprising: determining means for determining a video frame phase difference between and issuing a slip command to the memory when the phase difference exceeds a predetermined amount.