JPH04192051A - Asynchronous serial transmission/reception circuit - Google Patents

Abstract

PURPOSE:To batch process the accumulated reception data by providing an error flag buffer. CONSTITUTION:When the serial reception is over, a FIFO stores automatically the data on a reception register 1 in a data buffer 2 of the FIFO and also stores the contents of an error flag set in a flag register 4 in a FIFO data buffer 5. Meanwhile a CPU can reads out successively the contents of the buffer 2 via a data bus 3. In this case, the data received first is read out first. In the same way, the CPU can reads out successively the contents of the buffer 5 via the bus 3. In this case, the error flag set when the first data is received is read out first. Thus the reception data group accumulated in the FIFO and their corresponding error flags can be decided and batch-processed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an asynchronous serial transmitting/receiving circuit belonging to a semiconductor device.

[Prior Art] FIG. 2 is a block diagram of an asynchronous serial transmitting/receiving circuit (hereinafter referred to as UART) having a conventional first-in, first-loading buffer memory (hereinafter referred to as FIFO). In the figure, (1) is a reception register of [1ART, (2) is an 8-byte F'○, (3) is a data bus, and (4) is an error flag register.

Next, the operation will be explained. When the UART inputs serial data bit by bit from the outside, the data in the reception register (1) is sequentially shifted and stored as 8-bit data. In addition to the parity error flag, error flags such as an overrun error flag and a framing error flag are set or reset in the flag register (4) in 0ART.

Next, when the serial reception is completed, the FIFO automatically stores the data in the reception register (1) in the data buffer (2) within the FIFO. In this way, serially received data is transferred to the data buffer (
2). In the one shown in FIG. 2, the data buffer has an 8-byte structure, so up to 8 bytes can be stored.

On the other hand, from CPt1, via the data bus (3),
The contents of the data buffer (2) can be read, and the data to be read is read from the first received data.

[II problem that the invention seeks to solve]

The conventional asynchronous serial transmitter/receiver circuit having a first-in, first-out buffer memory is configured as described above.
Several bytes of serially received data can be stored and processed in batches. However, it is impossible to determine whether the received data was transmitted and received correctly without checking the parity error flag each time one piece of data is received.
There was a problem in that it required processing of U.

This invention was made to solve the above-mentioned problems, and it is possible to receive a data buffer for error flags in a FIFO, and check the error contents of each received data at the time of reception. The purpose is to obtain an asynchronous serial transmitter/receiver circuit.

[Means for Solving the Problems] t]ART having F'IFO according to the present invention is tr
The Iro has a separate data buffer for error flags, and in addition to the received serial data, the F-flag etc. can also be read easily [Function] DART with FIFO in this invention By providing a buffer for error flags, the stored received data can be processed all at once. [Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1st
In the figure, (1) is the 0ART reception register, (2)
is an 8-byte data buffer (FIFO), and (3
) is the data bus, (4) is the register for error flags during DART reception, including parity, error overrun F, framing F, etc., and (5) is the contents of the flag registers. This is a data buffer (FIFO) for storing.

Next, the operation will be explained. When the DART inputs serial data one bit at a time from the outside, the reception register (
The data in 1) is sequentially shifted and stored as 8-bit data. Also, the flag register in 0ART (
4), error flags such as an overrun error flag and a framing error flag are set or reset in addition to the parity-F flag.

Next, when serial reception is completed, the F/E"O automatically stores the data in the receive register (1) in the data buffer (2) in the FIFO, and flags the contents of the error flag in the flag register (4). FIl'O data buffer for (
5) Store.

In this way, serially received data and the contents of the error flag are transferred to the data buffer (
2) and (5).

On the other hand, the content of the data buffer (2) can be sequentially read from the CPU via the data bus (3), but successive data are read from the first received data. Similarly, the contents of the data buffer (5) can be sequentially read from the CPU via the data bus (3),
The data to be read is read from the error flag when first received.

In addition, in the above embodiment, data buffers (2) and (5)
However, if the number of buses is sufficient, it is also possible to read the received data and error flag at the same time.

Further, in the embodiment described above, the error flag is also readable, but it is also possible to switch between only the received data or both the received data and the flag using a control bit or the like.

[Effects of the Invention] As described above, according to the present invention, since the FIFO is provided with a data buffer for flags, the received data group stored in the FIFO and the error flag corresponding thereto can be collectively judged and processed. It becomes possible to do so.

[Brief explanation of the drawing]

FIG. 1 shows an 0ART with FIFO according to an embodiment of the present invention.
FIG. 2 is a block diagram of a conventional UART with FIFO. In the figure, (1) is the UART reception register, (2)
is a data buffer (FIFO), (31 is a data bus, (41 is a vanilla graph type register, (5Nd
This is a data buffer for error graphs. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1

Claims (1)

[Claims] An asynchronous serial transmitting/receiving circuit having a first-in, first-out buffer memory, characterized in that an area for storing data received by the asynchronous serial transmitting/receiving circuit and error flags such as a parity flag is provided in the first-in, first-out buffer memory. .