JPH0418738B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a transmission device in a multiplex transmission system.

[Prior art]

Fig. 1 shows a system in which a central processing unit centrally monitors and controls a plurality of terminals that are scattered far away. Control data (upstream)
are collected via the transmission device 2. The collected data is judged by the central processing unit 1 and given to the terminal 3 via the transmission device 2 as control data (downlink).

In the centralized monitoring and control system configured as described above, if the data between the central processing unit 1 and the transmission device 2 is mutually operated periodically, the following problems may occur when data is transferred between the two devices. occurs. For example, as shown in the time chart shown in FIG. 2A, the central processing unit 1 periodically takes in controlled data at an IN timing, makes a judgment, and outputs control data at an OUT timing. On the other hand, assuming that the transmission device 2 operates as shown in the time charts shown in FIGS. 2B and 2C, the controlled data "Z" shown in FIG. The data is fetched from IN, and the controlled data "Z" is determined there. The judgment result is shown in Figure 2A.
The control data "Z" (FIG. 2B) is sent from the OUT of the time chart to the transmission device 2. When the controlled data is processed in this way, a delay occurs between the central processing unit 1 and the transmission device 2 by α time in the case of uplink and β time in the case of downlink, as shown in FIG. 2C. Note that in the case of the delay time α, the maximum delay on the central processing unit side is one cycle of that device. Similarly, on the transmission device side, the delay time β is a delay of one cycle of that device.

In addition, since the central processing unit and the transmission device operate independently of each other, when the central processing unit imports the controlled data “Z”, if there is a change in the controlled data such as data update of the transmission device, the data will be updated. Another disadvantage is that the operation time becomes longer because the data is fetched after waiting for one cycle.

[Purpose of the invention]

In order to eliminate the above-mentioned drawbacks, this invention makes the operating time difference between the central processing unit and the transmission device constant,
It is an object of the present invention to provide a transmission device that eliminates waiting time, improves response time, and prevents failure even when transmission changes.

[Summary of the invention]

This invention forcibly controls the timing signal generator provided in the downlink transmission section using a timing signal from the central processing section so that the downlink waiting time is minimized. The timing at which uplink controlled data arrives is corrected so that the waiting time for data acquisition on the side is minimized.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 3, 11 is a central processing unit, and 12 is a transmission device.
5 and a control data output section 16.

On the other hand, the transmission device 12 transmits the control data from the central processing unit 11 to the first transmitter 17 and the first receiver 18.
It is configured to transmit the controlled data from the terminal to a terminal (not shown) via the second transmitter 19 and the second receiver 20 to the central processing unit 11 . Also, 21 and 22 are the first,
In the second timing signal generation section, these generation sections 2
The details of 1 and 22 will be described later. 23 and 24 are the first,
These are first and second timing signal detection sections that detect timing signals from the second timing signal generation sections 21 and 22. Note that 26 is a manual timing signal setter for manually providing the second timing signal generating section 22 with a timing signal that takes waiting time into consideration.

Here, the specific configuration of the first timing signal generating section 21 will be described with reference to FIG. 5. Fifth
In the figure, 31 is a clock signal generator, and the output signal of this clock signal generator 31 is sent to a counter 32.
is counted. For convenience of explanation, the counter 32
will be described taking as an example the case of counting from "0" bit to "23" bit. The counter 32 counts the clock signal output from the clock signal generator 31 from "0" to "23" bits, and starts the operation of the first transmitter 17 at the "0" bit. However, if the timing signal (*2) is given to the counter 32 when the counter 32 is at the 8th bit of "0" to "23" bit, the counter 32
is forcibly returned to the "0" bit. That is,
It is configured to be reset.

Next, the operation of the above embodiment will be described. The central processing unit 11 judges the data taken in via the controlled data input unit 15 in the central processing unit 13, stores it in a storage unit (not shown) and sends it to a monitoring device (not shown), etc., and then outputs the data to the timing signal generation unit 1.
Control data is supplied to the first transmitter 17 via the control data output section 16 using the timing signal (*1) sent out by the control data output section 16. As described above, the first transmitter 17 starts data transmission at the "0" bit of the first timing signal generator 21. Now, if the counter 32 is counting the "8" bit as described above, the counter 32 is reset by the timing signal (*2) outputted from the output section 16 together with the control data, and the first transmission is started. Part 1
7 is forcibly set to the operation start point. Since the time point at which the operation starts is well known, a description thereof will be omitted. In this way, the waiting time of the downlink transmission device is minimized, and the control data is transmitted to the first receiving unit 1 via the transmission path.
7. The first receiving section 18 uses the transmitted control data to the first timing signal detecting section 2.
3 detects the timing signal (*3).

When the first receiving section 18 has finished receiving all the captured control data, the control data is output to the terminal side at that point, and at the same time, the second timing signal generating section 22 of the second transmitting section 19 receives the control data. A signal (*4) indicating completion is sent out, and the second timing signal generator 22 knows the transmission delay time between the central processing unit side and the transmission device side using a well-known method, so this delay time A signal corresponding to the timing is set through the manual timing signal setter 26.

When such a delay time is set, the second timing signal generating section 22 performs a predetermined counting operation, and when the count value returns to "0" (*5)
The desired controlled data is transmitted from the second transmitter 19 to the second transmitter 19.
It is transmitted to the receiving section 20. In the second receiving unit 20, the second timing signal detecting unit 24 detects a timing signal (*6) from the captured controlled data, and when the data is finished receiving, the timing signal (*6) is detected.
In step 6), the controlled data is passed to the input unit 15 of the central processing unit 11.

When the controlled data filled in the input section 15 is taken into the central processing section 13 at the timing of *7, the fourth
As shown in the figure, the delay time set by the second timing signal generating section 22 is determined so that there is no delay between the timing of sending from the second receiving section 20 and the timing of outputting from the input section 15 to the central processing section 13. There is. Note that FIG. 4A shows the reset signal of the first timing signal generator 21, and FIG. 4B shows the reset signal of the output part 1.
6 is a timing signal (*2) supplied to the first timing signal generation section 21.

FIG. 6 is a block diagram showing another embodiment of the present invention, in which the timing signal correction means in the previous embodiment is implemented by a manual timing signal setter 2.
6 is automatically corrected using the output of the second receiving section 18.
Note that the same parts as in FIG. 3 are indicated with the same reference numerals. In FIG. 6, 27 is a comparison section, which compares the timing signals (*X) and (*Y) of the timing signal generation sections 14 and 21 and outputs a comparison output (*8) as described later. It is given to the first transmitter 17. The operation of the embodiment configured as described above will be described with reference to FIG.

As shown in Figure 7, X is a signal (*X) obtained by dividing one period of bits "0" to "23" in half, and Y is a signal (*X) obtained by dividing one period of bits "0" to "23". Both signals (*
X) and (*Y) are compared by a comparator 27. As a result of the comparison, for example, depending on whether the signal (*X) is a mark or a space at the falling edge of the signal (*Y), if it is a mark, the central processing unit side will be delayed, and if it is a space, it will be determined that it is advanced. In the former case, the comparison output (*8) is given to the first transmitter 17 as a delayed signal. The first transmitter 17 inserts the delay or lead signal into a desired bit of the control data of bits "0" to "23" and transmits it to the first receiver 18. In the first receiving section 18, the first
The timing signal detection unit 23 detects a timing signal, uses the signal (*4) to reset the second timing signal generation unit 22, and after the reset, the delay signal (*9) is set in the second timing signal generation unit 22. be done. The subsequent operations are performed in the same manner as in FIG.

Note that, in order to reduce the impact caused by data switching during transmission, correction may be performed, for example, in 1/100 increments.

〔Effect of the invention〕

As described above, according to the present invention, a transmission section is provided between a remote terminal and the central processing section,
In a device that transmits and receives data transmission signals between the transmission section and the central processing section, the upstream data transmission signal is Since the timing of incoming calls is corrected, there is an advantage that the operating time difference between the central processing section and the transmission section is kept constant, thereby minimizing waiting time and improving response time.

[Brief explanation of drawings]

Figure 1 is a schematic configuration diagram of a remote monitoring and control device;
Figures 2A, B, and C are time charts of the central processing and transmission equipment, Figure 3 is a block diagram showing one embodiment of the present invention, and Figures 4A to 4G explain the operation of the above embodiment. Figure 5 is a specific block diagram of the timing signal generation section.
FIG. 6 is a block diagram showing another embodiment of the invention, and FIG. 7 is a waveform diagram for explaining the operation of FIG. 6. 11...Central processing unit, 12...Transmission device, 1
3... Central processing section, 14... Timing signal generation section, 15... Input section, 16... Output section, 17, 1
9...first, second transmitter, 18,20...first,
Second receiving section, 21, 22...first and second timing signal generating sections, 23, 24...first and second timing signal detecting sections.

Claims (1)

[Scope of Claims] 1. A transmission unit is provided between a remote terminal and a central processing unit, and when transmitting and receiving data transmission signals between the transmission unit and the central processing unit, downlink and uplink signals are transmitted and received. A transmission unit is provided with a correction device that corrects the arrival timing of uplink data transmission signals using a manual timing signal setter so as to minimize data waiting time in the central processing unit, wherein the correction device is installed in the central processing unit. A first timing signal generation section that is reset by a timing signal from a processing section, a first timing signal detection section that detects a timing signal of this first timing signal generation section, and a first timing signal detection section that is reset by a detection signal of this detection section and outputs data. 1. A transmission device comprising: a second timing signal generating section to which a timing value of an incoming signal is input; and a second timing signal detecting section detecting a timing signal of the second timing signal generating section. 2. A transmission section is provided between a remote terminal and a central processing section, and when transmitting and receiving data transmission signals between the transmission section and the central processing section, data transmission in the downlink and uplink central processing sections The transmitting section is provided with an automatic correction device that automatically corrects the arrival timing of the uplink data transmission signal so as to minimize the waiting time of the data transmission signal, and the automatic correction device is installed in the timing signal generation section of the central processing section. and a first timing signal generation section of the transmission section; a first timing signal detection section that detects the comparison output of this comparison section and the output of the first timing signal generation section; and this detection section. a second timing signal generating section which is reset by the timing signal detected by the second timing signal generating section and into which the timing value of data arrival is inputted according to the value of the comparison output signal; and detecting the timing signal of this second timing signal generating section. A transmission device comprising: a second timing signal detection section.