JPH0418470B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to large scale integrated circuit chips for multichip configurations.

An integrated circuit (IC) consists of an IC chip mounted on the pedestal of a package, connected to the terminal pins of the package by wire bonding, etc., and sealed with a lid or the like. The scale of integrated circuits, that is, the number of memory cells in the case of memory and the number of gates in the case of logic circuits, continues to increase.Large-scale integrated circuits are called LSIs, and the increase in scale is achieved by miniaturizing the elements. Therefore, the chip size usually remains unchanged. This is because pattern accuracy cannot be maintained if the chip is made larger. However, assuming the element size is constant, the chip area is doubled or tripled...
If we do this, the scale of the integrated circuit will double, triple, etc.
It is also true that further scale-up can be easily achieved. Therefore, it has been considered to install two, three, etc. LSI chips in one LSI package, and this is called a multi-chip configuration.

[Conventional technology]

Large-scale integrated circuits with a multi-chip configuration include two types: multiple LSI chips are installed in one package, each chip is wired to a terminal pin, and any wiring between chips is routed through the terminal pins. There is a method in which wiring between chips is done directly between chips without passing through terminal pins. The former is not much different from using multiple LSIs (the area occupied on the printed board is smaller), but the latter is
The inter-chip wiring is not much different from the intra-chip wiring in terms of wiring length and parasitic capacitance, so it has advantages such as high-speed driving and the output stage transistors needing low driving capacity.

[Problem that the invention seeks to solve]

However, if inter-chip wiring is performed directly between chips without passing terminal pins, problems will arise during final testing after multiple chips are attached to a package and wire bonded. In other words, if a signal is transmitted directly from chip to chip through the inter-chip wiring without passing through the terminal pin, the signal cannot be captured by the terminal pin, so a complex test program must be prepared to detect the signal. It is necessary to be able to test the operation of the multichip without it, which is troublesome. Furthermore, even if abnormal operation is detected, it is difficult to identify the defective chip.

Therefore, the present invention aims to make it possible to easily output and input inter-chip signals to and from the outside, thereby facilitating final testing after assembly.

[Means for solving problems]

The present invention provides a shift register along a side adjacent to an adjacent chip in a multi-chip large-scale integrated circuit chip in which a plurality of chips are mounted in one package and the chips are interconnected by wire bonding. Each stage of the shift register is connected to a bonding pad for inter-chip wiring, and the input/output and control terminals of the shift register are connected to other bonding pads. The structure and operation will be explained in detail.

〔Example〕

FIG. 1 shows an embodiment of the present invention, 10A, 10
B is an LSI chip, which is attached to the common package 12 to form a multi-chip configuration. The power supply wiring of each chip and the input/output signal wiring to/from the outside are connected to terminal pins via bonding pads etc. around the chip, and inter-chip signal wiring is constituted by bonding wires 14. A gate array or master slice type LSI chip has an internal gate in the center and external input/output gates around it, and numeral 16 indicates the external input/output gate. Bonding wire 14
is bonded to a bonding pad 20 around the chip, which is connected to an external input/output gate 16. As mentioned above, inter-chip signals cannot be monitored from the outside in this state, so in the present invention, a shift register 18 is provided on the side opposite to the adjacent chip where inter-chip wiring is made, and this register has parallel input and serial output. each stage is connected to a bonding pad that is interconnected between chips. In addition, appropriate bonding pads around the chip, preferably bonding pads 20A to 20D on the side not facing the adjacent chip 10B near the shift register 18, are used for control; for example, 20A is used for scan-out, and 20B is used for scan-in. 20C is used for scan control, and 20D is used for scan clock.

FIG. 2a shows an overview of the shift register 18, and FIG. 2b shows details. In figure b, FF1, FF2, . . . are flip-flops constituting each stage or each bit of the shift register, and the number of stages is selected to be equal to (or greater than) the number of interconnections between chips. G1~G3,G4
~G6, . . . are gates that control input/output to each flip-flop. To take the inter-chip signal into the shift register 18, the scan control signal CNT applied to the pad 20C is set to low level to open the AND gates G1, G4, . . . and the scan clock CLK is input to the pad 20D. As a result, the output signal of the input/output gate 16 connected to the wire bonding 14 is taken into each flip-flop FF1, FF2, . . . through the AND gates G1, G4, .

To take out the inter-chip signals taken into the shift register 18, set the scan control signal CNT to H (high).
level and input the scan clock CLK continuously. As a result, AND gates G2, G5,...
is opened, the output of the front-stage flip-flop is input to the rear-stage flip-flop, and the inter-chip signal thus taken into the shift register is taken out from the scan-out pad 20A. In other words, parallel in and series out are performed. By slightly changing the input/output gates of the flip-flops, series-in and parallel-out are possible. In this case, test data for the next stage LSI chip 10B is input in the form of a serial signal to the scan input pad 20B, and each flip-flop in the shift register 18 is After storing the test data, switch to parallel output and input the test data in parallel to the next stage LSI chip through the bonding wire 14.

Providing the shift register 18 in this manner facilitates the input/output of signals between chips, which is extremely effective in testing chip operation. Control pads 20A to 20D
Since it is not connected to the terminal pin, the above test cannot be performed after the package cage is sealed by closing the lid, but at the final test stage after assembly, the package cage is not yet sealed, so the above test is possible. Of course, if the control pads 20A to 20D are connected to the terminal pins, the above test can be performed even after the package is sealed. However, this method has a problem in that a limited number of terminal pins are occupied for testing purposes.

When two LSI chips are installed in one package, one LSI chip is 10A as shown in Figure 1.
It is sufficient to provide a shift register on the opposite side of , but 3
If installed, the next stage LSI of LSI chip 10B
A shift register is also provided on the opposite side to the chip.
In addition, if a plurality of such columns are provided, for example, chips are provided on the upper or lower sides of chips 10A and 10B in FIG. It is a good idea to provide When transmitting and receiving signals between the chips 10A and 10B, the signals received by the shift register 18 include a mixture of output signals from the chips 10A to 10B and output signals from the chips 10B to 10A.

The input/output gates of LSI chips 10A and 10B are
Those connected to the terminal pins to drive external circuits need to have a large driving capacity, but those that drive the inter-chip wiring 14 need only have a small driving capacity.
The driving capacity can be easily changed by changing the base current of the output stage transistor, for example by changing the value of the resistance of the base current circuit.

It is also possible to incorporate the shift register into the chip. That is, as shown in Fig. 3, the LSI chip 10
By configuring the shift registers 16A and 16B in the shape of a + character, signals from various parts within the chip can be input in parallel to these shift registers, shifted by a clock, and output in series from one end. In this way, the LSI chip 10 becomes the same as if it were divided into four equal parts, and the internal signal state can be clearly understood. It has been considered to interconnect flip-flops scattered within a chip to form a shift register and input/output test data, but this method would complicate the configuration of the flip-flops and create a shift register by interconnecting them. It's not easy to do either. Third
In the system shown in the figure, the shift registers 16A and 16B are constructed independently of the flip-flops scattered within the chip, so the flip-flops are not complicated and the design is easy.

〔Effect of the invention〕

As explained above, in the present invention, signals transmitted through inter-chip wiring in a multi-chip configured LSI can be easily taken out to the outside, and it is extremely effective for testing after LSI chips are mounted on a package.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of a shift register section thereof, and FIG. 3 is an explanatory diagram showing an example of arrangement of the shift register. In the drawing, 12 is the package, 10A, 10B are
14 is a wire bonding, 18 is a shift register, and 20 is a bonding pad.

Claims (1)

[Scope of Claims] 1. In a multi-chip large-scale integrated circuit chip in which a plurality of chips are mounted in one package and the chips are interconnected by wire bonding, a shift register is provided along the side adjacent to the adjacent chip, A large-scale integrated circuit characterized in that each stage of the shift register is connected to a bonding pad on which inter-chip wiring is provided, and input/output and control terminals of the shift register are connected to other bonding pads. Chip.