JPH04184388A - Display controller - Google Patents

Abstract

PURPOSE:To attain high-speed access and to save electric power by rapidly receiving the access from a main device and activating a character memory pattern only during this access period at the time of making urgent access from a main device. CONSTITUTION:The output of flip-flop F1 rises to a HIGH level when the instruction for a low-current consumption mode is written into the flip-flop F1 from the main device. The output of the flip-flop F2 rises to the HIGH level at the fall of the next signal TMGS tuned to the display access of the character pattern memory and, therefore, the same state as the state of forcibly raising the signal HACH to the HIGH level is obtd. in an OR gate G1 and the output of an AND gate G2 falls to the LOW level only when the output of a selector S1, i.e., the signal HST, falls to the LOW level and, therefore, the control signal of the character pattern memory which is the output of an OR gate G3 attains the LOW level active only when the request for the memory access form the main device is detected. The signal attains the HIGH level (inert) in the periods exclusive of the above-mentioned period. The unnecessary currents are thus controlled.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention provides a display control device having a character pattern memory that can read character pattern data for display by accessing from a text memory and also being accessible from a main device. It is related to.

[Prior Art] FIG. 3 is a block diagram of a conventional display control device, in which (1) is a display timing generator that generates various timing signals for display based on settings from the main device;
2) is a text memory that stores display data (character code data and color code data) sent from the main device;
3) is a character pattern memory that stores character pattern data sent in advance and from the main device, (4) is a text memory control unit that controls the text memory (2), and (5) is an address for the character pattern memory (3). (6) is a character pattern memory control unit that controls the character pattern memory (3); (7) is character pattern data that controls writing/reading of character pattern data to and from the character pattern memory (3). The control unit (8) is an image data generation unit that generates image data for display.

Next, the operation will be explained. First, text memory (2)
When displaying the contents of the text memory (2), the character code data read from the text memory (2) is sent to the address generator (5).
is converted to the address for character pattern memory (3),
Furthermore, in accordance with this converted address, the character pattern memory control section (6) generates a corresponding control signal (chi knob select signal, etc.). The character pattern data read out from the character pattern memory (3) in this way is passed through the character pattern data control unit (7) to the image data generation unit (
8), and the image data generation unit (8) combines this character pattern data with the color code data sent from the text memory (2) to generate image data for display and supplies it to the display device. .

Next, when writing character pattern data from the main device to the character pattern memory (3), the character code data sent from the main device is first converted into an address for the character pattern memory (3) by the address generation section (5). Furthermore, the character pattern memory control unit (6) generates a control signal (chip select signal, etc.) for the character pattern memory (3) according to this converted address, and in this state, the character pattern data is transmitted from the main device. Character pattern data is sent to the control section (7) and written into the character pattern memory (3).

Thus, in such a character pattern memory (3), memory accesses from the text memory (2) and from the main device compete, but conventionally, the conflict was adjusted in the address generator [5] as follows. .

FIG. 4 is a block diagram showing a part of the conventional address generation unit (5) and its surroundings. In the figure, ('Sl), (S2)
is a selector, and (51) is a character pattern address generation logic.

Also, Figure 5 is a timing chart of each signal in Figure 4.
In the figure, CDl5P) is the display/representation for each rask scan of the screen.
The signal (CCLK) that determines the non-display period is a character clock signal (TMG) that is generated in synchronization with each character displayed.
S) is a signal obtained by dividing the signal (CCLK) by 2, (H5T)
is a detection signal for a character pattern memory access request sent from the main device. When an access request from the main device occurs, this signal goes to LOW level at the subsequent fall of the signal (TMGS), and When there is no access request from TMGS, this signal becomes HIGH at the subsequent fall of the signal (TMGS).

In FIG. 4, in the "low speed mode" in which the main device does not request emergency memory access, the signal (HACH) is set to LOW level by the main device, and as a result, the signal (DISP) is selected in the selector Sl and the selector S2
input to the S terminal of Therefore, during the display period, that is, while the signal (DISP) is at HIGH level, the display character code from the text memory (2) is input to the character pattern address generation logic (51), and during the non-display period,
That is, while the signal (DISP) is at the LOW level, the character code from the main device is input to the character pattern address generation logic (51). However, since the display period is longer than the non-display period, access from the main device is forced to wait in such a "low speed mode".

Therefore, when the main device performs an emergency memory access, the signal (HACH) is set to the F (IGH level) to enter the "high speed mode" and the signal (H5T) is applied to the S terminal of the selector S2. Since the signal (H5T) goes to LOW level as soon as it detects that there is a request for access from the main device, the character code data from the main device is input to the character pattern memory address generation logic (51) in selector S2 each time. and like this “
``Fast mode'' allows emergency memory access by the main device.

However, in the above-mentioned "high-speed mode", access from the main device is performed even while the screen is being displayed, so
If there are many accesses from the main device like this, not only will the displayed image become distorted, but also the character pattern data for display that is useless for the entire screen may end up being read from the character pattern memory (3). .

[Problems to be Solved by the Invention] The conventional display control device as described above is configured as described above, and even when the displayed image is disturbed as described above, the character Bakun memory (3) is activated. Moreover, since the character pattern data for display is being read out, power is wasted.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a display control device that can perform memory access from a main device at high speed and save power.

[Means for Solving the Problems] A display control device according to the present invention has a character pattern memory that can read character pattern data for display by accessing from a text memory and can also be accessed from a main device. an access mode setting section that can be set from the outside; a signal generating means that generates a control signal that becomes true only during an access period from the main device when the access mode is true; and a character pattern memory according to the control signal. and a character pattern memory control unit that activates/deactivates the character pattern memory.

[Function] The display control device according to the present invention has an access mode that can be set from the outside, and although this access mode is not normally set as true, when it is desired to perform emergency access, preferably from the main device, this access mode can be set. In addition to setting the mode to true, the signal generation means generates a control signal that becomes true only during the access period from the main device, and the character pattern memory control section activates/reacts the character pattern memory according to this control signal.
It is inactive to achieve high speed access and save power.

[Example] An example of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a part of the address generation section (5') and its surroundings in a display control device according to an embodiment of the present invention. In the figure, the same reference numerals as in FIG. 4 indicate the same or equivalent parts, and ( Fl).

(F2) is a flip-flop, (Gl), (G3
) is a two-person OR gate, and (G2) is a two-person AND gate. The entire display control device of this embodiment is the same as that shown in FIG. 3 except for the parts replaced in FIG. 1.

Also, Figure 2 is a timing chart of each signal in Figure 1,
In addition to the signals shown in FIG. 5, an access request signal from the main device and a character pattern memory control signal are shown here.

Next, the operation will be explained. First, when power is applied to the device, a signal (Reset) is generated, and a flip-flop (Fl) is generated.
) and (F2) are both reset. The LOW level output of this flip-flop (F2) has no effect on the output of OR gate 1-(Gl), and the output of AND gate (G2) is fixed at LOW level. It does not affect the output of the OR gate (G3) either. Therefore, in such a state, the operation is the same as that of the conventional configuration described with reference to FIG.

Next, when a low current consumption (power save) mode command is written to the flip-flop (Fl) from the main device, the output of the flip-flop (Fl) becomes HIGH level. Next, the output of the flip-flop (F2) goes to HIGH level at the fall of the next signal (TMGS) synchronized with the display access of the character pattern memory (3), and this causes the OR gate (Gl) to The high-speed mode signal (HACH) is set to the same state as if it were forced to the HIGH level, and the AND gate (G2)
In this case, its output becomes LOW only when the output of the selector (Sl), that is, the signal (H5T) becomes LOW level.
As a result, the output of the OR gate (G3), that is, the character pattern memory control signal goes to the LOW level (
It becomes HIGH level (inactive) during other periods (that is, during display access). Therefore, since the text memory (2) is not accessed for display, unnecessary current flowing to the character pattern memory (3) is suppressed during this period, and power is saved.

In the above embodiment, the transition to the power save mode was performed by data control from the main device, but other mechanical means such as a switch may also be used.

In addition, the above embodiment describes power saving control of the character pattern memory (3) in which character pattern data for display can be read by accessing from the text memory (2) and character pattern data can be written by accessing from the main device. However, there are other cases in which, for example, there is a character pattern memory that reads out character pattern data for display by accessing from the text memory and reading out character pattern data for display by accessing from the main device. , to access from the main device.

Therefore, since the display from the text memory is disturbed, the power save control of the present invention can be applied in the same way as in the above embodiment, and the character pattern memory is inactivated except when accessed from the main device. It's good.

[Effects of the Invention] As explained above, the present invention is capable of quickly accepting access from the main device when a group of emergency accesses is desired from the main device, and changing character patterns only during the period of access from the main device. Since the memory is activated, high-speed access can be achieved and power can be saved.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram of a part of the address generation unit (5') and its surroundings in a display control device according to an embodiment of the present invention, and FIG. 2 is a timing diagram of each signal in FIG. 1. 3 is a block diagram of a conventional display control device, FIG. 4 is a block diagram showing a part of the conventional address generation section (5) and its surroundings, and FIG. 5 is a timing diagram of each signal in FIG. 4. It is a chart. In the figure, (1) is a display timing generation section, (2) is a text memory, (3) is a character pattern memory, (4) is a text memory control section, (5) and (5') are an address generation section, and (6) is a text memory control section. ) is a character pattern memory control section, (7) is a character pattern data control section, (8) is an image data generation section,
(S own, (S2) is a selector, (51) is a character pattern address generation logic, (Fl). (F2) is a flip-flop, (Gl), (G3) are O
The R gate (G2) is an AND gate. In addition, the same reference numerals in each figure represent the same or corresponding parts.
′)′! ″1″8° Agent Masuo Oiwa ST 2nd vA Procedural amendment (voluntary) 1991 3 n5 Nippa

Claims (1)

[Scope of Claim] A display control device having a character pattern memory that reads character pattern data for display by accessing from a text memory and also being accessible from a main device, comprising: an access mode setting unit that can be set from the outside; , signal generating means for generating a control signal that becomes true only during the access period from the main device when the access mode is true; and a character pattern memory that activates/deactivates the character pattern memory according to the control signal. A display control device comprising: a control section.