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JPH0418399A - Ic module - Google Patents

Ic module

Info

Publication number
JPH0418399A
JPH0418399A JP2119718A JP11971890A JPH0418399A JP H0418399 A JPH0418399 A JP H0418399A JP 2119718 A JP2119718 A JP 2119718A JP 11971890 A JP11971890 A JP 11971890A JP H0418399 A JPH0418399 A JP H0418399A
Authority
JP
Japan
Prior art keywords
wiring pattern
pattern
resin
chip
shape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2119718A
Other languages
Japanese (ja)
Other versions
JP3148218B2 (en
Inventor
Toshiharu Ichikawa
市川 俊治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP11971890A priority Critical patent/JP3148218B2/en
Publication of JPH0418399A publication Critical patent/JPH0418399A/en
Application granted granted Critical
Publication of JP3148218B2 publication Critical patent/JP3148218B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Credit Cards Or The Like (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent the overflow of a molding resin at the time of the sealing with said resin and to enhance the adhesive strength in the process succeeding to the sealing process by providing a linear (comb-like) pattern parallel to the edge of the shape of a molding resin seal to the wiring pattern on a printed circuit board at the position corresponding to the edge of the shape of the molding resin seal. CONSTITUTION:An IC chip 3 and a wiring pattern 6 are sealed by a molding resin 9 composed of an epoxy resin so as to cover a part on the side of the IC chip 3 of the wiring pattern 6. In this case, a wiring pattern 15 is provided in a comb-like pattern at the position corresponding to the edge part of the shape (generally a square) of the molding resin 9 almost in parallel to said edge part. This pattern is not especially limited to the comb-like shape and may be a linear pattern almost parallel to the edge part. This pattern is formed from a copper foil simultaneously with the original wiring pattern 6 and, therefore, the thickness thereof becomes same to that of the wiring pattern. That is, the shape of the wiring pattern just achieves the function of a weir (stopper) when the molding resin is injected to prevent the overflow of the resin.

Description

【発明の詳細な説明】 本発明はICモジュール、その中でも特にICカードに
使用されるICモジュールの配線パターンに関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an IC module, and particularly to a wiring pattern for an IC module used in an IC card.

(従来の技術) 第2図(a)(b)に従来のICモジュールの構成図を
示す。(a)図はICチップを搭載した側つまり上面の
平面図であり、(b)図は断面図である。
(Prior Art) FIGS. 2(a) and 2(b) show configuration diagrams of a conventional IC module. The figure (a) is a plan view of the side on which the IC chip is mounted, that is, the top surface, and the figure (b) is a cross-sectional view.

近来とみに携帯可能な記憶媒体としてICカードが普及
してきている。このICカードはクレジットカードやキ
ャッシュカードサイズのカード基体にメモリやマイクロ
コンピュータ等のICチップを搭載したICモジュール
を組み込んでいる。
In recent years, IC cards have become popular as portable storage media. This IC card has an IC module equipped with an IC chip such as a memory or a microcomputer built into a card base of the size of a credit card or cash card.

そのICモジュールは、第2図のようにガラスエポキシ
積層板等からなる回路基板lの一方の面(図では裏面)
に複数の外部接続端子2が設けられており、他方の面(
表面)にはICチップ3が搭載されている。このICチ
ップ3を搭載する面にはその部分にそれを搭載するザグ
リ部分5が設けられておりそこへICチップ3を固着す
る。またその面にはそのICチップ30周辺に該ICチ
ップ3の外部接続端子(ポンディングパッド)と接続す
る配線パターン6(一般に銅箔等からなりその上に金メ
ツキ等が施されている)が形成されている。即ちプリン
ト基板と同様の構造である。
As shown in Figure 2, the IC module is installed on one side (the back side in the figure) of a circuit board l made of a glass epoxy laminate, etc.
A plurality of external connection terminals 2 are provided on the other side (
An IC chip 3 is mounted on the front surface). The surface on which the IC chip 3 is mounted is provided with a counterbore portion 5 on which the IC chip 3 is mounted, and the IC chip 3 is fixed thereto. Further, on that surface, a wiring pattern 6 (generally made of copper foil or the like and plated with gold or the like) is provided around the IC chip 30 to connect with the external connection terminal (ponding pad) of the IC chip 3. It is formed. In other words, it has a structure similar to that of a printed circuit board.

勿論前記ICチップ3の外部接続端子とその配線パター
ン6のICチップ側先端部とは金属細線7で接続されて
いる。その配線パターン6の他方の一端はスルーホール
8を介して前記外部接続端子2に接続されている。そし
て前記ICチップ3と配線パターン6のICチップ3側
の一部を覆うようにエポキシ樹脂等からなるモールド樹
脂9で封止されており、その形状は一般に四角形である
Of course, the external connection terminal of the IC chip 3 and the tip of the wiring pattern 6 on the IC chip side are connected by a thin metal wire 7. The other end of the wiring pattern 6 is connected to the external connection terminal 2 via a through hole 8. The IC chip 3 and a part of the wiring pattern 6 on the IC chip 3 side are sealed with a mold resin 9 made of epoxy resin or the like, and the shape thereof is generally a square.

(図の斜線の部分) (発明が解決しようとする課題) しかしながら、前述のICモジュールではモールド樹脂
9によって封止するときに、そのモールド樹脂9縁辺部
の回路基板1の表面の配線パターン6の周辺部分(そこ
には段差があり、主にその部分)からモールド樹脂が外
側に溢れ出し易いという問題点があった。
(Shaded area in the figure) (Problem to be solved by the invention) However, in the above-mentioned IC module, when sealing with the mold resin 9, the wiring pattern 6 on the surface of the circuit board 1 at the edge of the mold resin 9 is There was a problem in that the mold resin easily overflowed to the outside from the peripheral area (mainly at that area where there was a step).

その段差は一般に40〜60μmあり、モールド樹脂で
封止するときの注入圧力によりこの間隙から樹脂が流れ
出し、ICカード等の製作ではその後の接着力の低下を
招いていた。
The level difference is generally 40 to 60 μm, and the resin flows out from this gap due to the injection pressure when sealing with mold resin, resulting in a subsequent decrease in adhesive strength in the production of IC cards and the like.

この問題に対して配線パターン上にソルダーレジストを
施しモールド樹脂注入時の間隙を小さくする対策等が考
えられているが、それもソルダーレジストとICカード
との接着力が弱いことや部分的なソルダーレジストにす
ることが基板作製時の工程増加になり好ましいものでは
なかった。
Countermeasures have been considered to solve this problem, such as applying a solder resist on the wiring pattern to reduce the gap when injecting the molding resin, but this also has problems such as weak adhesive strength between the solder resist and the IC card, and partial solder resist. Using a resist increases the number of steps required for manufacturing the substrate, which is not desirable.

(課題を解決するための手段) niミノの課題を解決するために本発明では、回路基板
上の配線パターンにモールド樹脂封止の形状の縁辺に対
応した位置に、その縁辺に平行な線状((シ状)のパタ
ーンを設けたものである。
(Means for Solving the Problems) In order to solve the problems of NiMino, the present invention provides a wiring pattern on a circuit board at a position corresponding to the edge of the molded resin sealing shape, and a line parallel to the edge. (It has a (shi-shaped) pattern.

(作用) 上記パターンを配線パターンに設けたため、そのパター
ンが樹脂の溢れ出すことの堰止めになり前記問題を防止
することができる。
(Function) Since the above-mentioned pattern is provided in the wiring pattern, the pattern acts as a dam against overflowing of the resin, thereby making it possible to prevent the above-mentioned problem.

(実施例) 第1図に本発明のICモジュールの構成図を示す。(a
)図はICチップ側(上面)の平面図であり、(b)図
は断面図である。従来の技術の説明おための第2図と同
一の部分は同一の記号を付した。
(Example) FIG. 1 shows a configuration diagram of an IC module of the present invention. (a
) is a plan view of the IC chip side (top surface), and (b) is a cross-sectional view. The same parts as in FIG. 2 for explaining the prior art are given the same symbols.

構成は配線パターン15.18以外は従来の構成と同一
なので説明を割愛する。
The configuration is the same as the conventional configuration except for the wiring patterns 15 and 18, so a description thereof will be omitted.

配線パターン15の、モールド樹脂9の形状(一般に四
角形)の縁辺部に対応した位置に該縁辺にほぼ平行に図
に示すように(し状のパターンを設けた。これは特にく
し状でなくても前記辺にほぼ平行な線状のパターンであ
ればよい。(図(a)の上部、下部はそれに近い) このパターンは従来のパターンと同様、銅箔等で本来の
配線パターン(第2図での6)と同時に形成できること
は自明であろう。従って本パターンの厚さはその配線パ
ターンと同じ厚さになる。
As shown in the figure, a comb-shaped pattern is provided in the wiring pattern 15 at a position corresponding to the edge of the molded resin 9 (generally rectangular) and approximately parallel to the edge. It suffices if the pattern is a linear pattern that is almost parallel to the side. (The upper and lower parts of Figure (a) are close to that.) This pattern is similar to the conventional pattern and can be made of copper foil etc. to form the original wiring pattern (see Figure 2). It is obvious that it can be formed simultaneously with step 6). Therefore, the thickness of this pattern is the same as that of the wiring pattern.

つまりこの配線パターンの形状はモールド樹脂を注入す
る際、丁度層(ストッパー)の役割を果しその樹脂の溢
れ出るのを防ぐ。
In other words, the shape of this wiring pattern serves as a layer (stopper) when molding resin is injected, and prevents the resin from overflowing.

(発明の効果) 前述したように本発明のような配線パターンを設けたの
で、モールド樹脂封止時その溢れがな(なりその後の工
程での接着力の向上が図れ、信頼性の高い製品を実現で
きる。
(Effects of the Invention) As mentioned above, since the wiring pattern of the present invention is provided, there is no overflow when sealing with mold resin, which improves the adhesion strength in the subsequent process, resulting in a highly reliable product. realizable.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のICモジュール構成図、第2図は従来
の1 6.15 Cモジュール構成図を示す。 回路基板、 ICチップ、 配線パターン、 くし状パターン。
FIG. 1 shows a configuration diagram of an IC module according to the present invention, and FIG. 2 shows a configuration diagram of a conventional 16.15C module. Circuit boards, IC chips, wiring patterns, comb patterns.

Claims (1)

【特許請求の範囲】 ICチップを搭載し、該ICチップの外部接続端子と接
続する配線パターンを有し、該ICチップ全部と該配線
パターンの一部を樹脂封止してなるICモジュールにお
いて、 前記樹脂封止の形状の縁辺に対応する位置の周辺の配線
パターンに該辺にほぼ平行な線状のパターンを設けたこ
とを特徴とするICモジュール。
[Scope of Claims] An IC module mounted with an IC chip, having a wiring pattern connected to an external connection terminal of the IC chip, and in which the entire IC chip and a part of the wiring pattern are sealed with resin, An IC module characterized in that a wiring pattern around a position corresponding to an edge of the shape of the resin sealing is provided with a linear pattern substantially parallel to the edge.
JP11971890A 1990-05-11 1990-05-11 IC module Expired - Fee Related JP3148218B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11971890A JP3148218B2 (en) 1990-05-11 1990-05-11 IC module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11971890A JP3148218B2 (en) 1990-05-11 1990-05-11 IC module

Publications (2)

Publication Number Publication Date
JPH0418399A true JPH0418399A (en) 1992-01-22
JP3148218B2 JP3148218B2 (en) 2001-03-19

Family

ID=14768397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11971890A Expired - Fee Related JP3148218B2 (en) 1990-05-11 1990-05-11 IC module

Country Status (1)

Country Link
JP (1) JP3148218B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653994U (en) * 1992-12-28 1994-07-22 リズム時計工業株式会社 Circuit board pattern structure
EP0772232A1 (en) * 1995-11-03 1997-05-07 Schlumberger Industries Electronic module assembly for electronic memory cards and associated manufacturing process
US6484394B1 (en) * 1999-01-11 2002-11-26 Hyundai Electronics Industries Co., Ltd. Encapsulation method for ball grid array semiconductor package
WO2003050869A1 (en) * 2001-12-11 2003-06-19 Motorola, Inc. Packaged integrated circuit and method therefor
US6930042B1 (en) * 1999-05-11 2005-08-16 Infineon Technologies Ag Method for producing a semiconductor component with at least one encapsulated chip on a substrate
KR100651796B1 (en) * 2000-10-11 2006-11-30 삼성테크윈 주식회사 IC chip module
US7217579B2 (en) * 2002-12-19 2007-05-15 Applied Materials, Israel, Ltd. Voltage contrast test structure

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653994U (en) * 1992-12-28 1994-07-22 リズム時計工業株式会社 Circuit board pattern structure
EP0772232A1 (en) * 1995-11-03 1997-05-07 Schlumberger Industries Electronic module assembly for electronic memory cards and associated manufacturing process
FR2740935A1 (en) * 1995-11-03 1997-05-09 Schlumberger Ind Sa METHOD FOR MANUFACTURING A SET OF ELECTRONIC MODULES FOR ELECTRONIC MEMORY CARDS
US5740606A (en) * 1995-11-03 1998-04-21 Schlumberger Industries Method of manufacturing a set of electronic modules for electronic memory cards
US6484394B1 (en) * 1999-01-11 2002-11-26 Hyundai Electronics Industries Co., Ltd. Encapsulation method for ball grid array semiconductor package
US6930042B1 (en) * 1999-05-11 2005-08-16 Infineon Technologies Ag Method for producing a semiconductor component with at least one encapsulated chip on a substrate
KR100651796B1 (en) * 2000-10-11 2006-11-30 삼성테크윈 주식회사 IC chip module
WO2003050869A1 (en) * 2001-12-11 2003-06-19 Motorola, Inc. Packaged integrated circuit and method therefor
US6617524B2 (en) 2001-12-11 2003-09-09 Motorola, Inc. Packaged integrated circuit and method therefor
US7217579B2 (en) * 2002-12-19 2007-05-15 Applied Materials, Israel, Ltd. Voltage contrast test structure

Also Published As

Publication number Publication date
JP3148218B2 (en) 2001-03-19

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