JPH04183043A - Digital information detector - Google Patents

Abstract

PURPOSE:To stably detect source digital information by detecting not an envelop amplitude but an amplitude at data time. CONSTITUTION:An output signal 121 of an equalizing circuit 20 is inputted to an amplitude detection circuit 25. The amplitude detection circuit 25 is composed of a sample/hold circuit 26, absolute value circuit 27 and LPF 28. The sample/hold circuit 26 samples the signal 121 at time having no interference between codes at the timing of a clock signal 103 and for the output of the sample/hold circuit 26, the absolute value of the amplitude is obtained by the absolute value circuit 27. Then, the signal is smoothed by the LPF 28 and by removing unnecessary fluctuating components caused by noise, amplitude information 123 showing the amplitude at the data time is obtained. Thus, since not the envelop amplitude but the amplitude at the data time is detected, the digital information can be stably detected without degrading a code error rate even when changing the envelop amplitude corresponding to the contents of a digital information sequence.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to PCM (Pulse Code Module) transmitted via a communication transmission line or reproduced from a recording medium.
The present invention relates to a digital information detection device that detects original digital information from an ation) signal.

Conventional technology A known method for detecting a PCM signal from a PCM signal transmitted or reproduced from a recording medium is to perform partial response equalization so that a predetermined specific intersymbol interference occurs, and then detect the original digital information. . This method enables detection with a lower code error rate than a method of equalizing to suppress intersymbol interference, especially in cases where intersymbol interference is large, such as in magnetic recording. From this point of view, an example of applying this method to a digital recording/reproducing apparatus is Japanese Patent Laid-Open No. 1-102777.

A conventional example will be described below with reference to the drawings.

FIG. 5 shows a conventional example of a digital information detection device using partial response equalization in a digital magnetic reproducing device. PCM recorded on a magnetic medium is reproduced by a magnetic head 1. The reproduced signal is sent to head amplifier 2.
The equalization circuit 3 amplifies the intersymbol interference by (
1, -1).

The frequency characteristic E(w) of the equalization circuit 3 is expressed as follows: H(w) is the frequency characteristic of the system from recording to the output of the head amplifier, and L(w) is the frequency characteristic of the roll-off filter that satisfies the Nyquist criterion. In addition, the frequency characteristic of partial response equalization where the intersymbol interference is (1, -1) is P (w
), the following formula is satisfied.

E(w)=L(w) ・P(w)/H(w) Now, the equalized signal is input to the clock regeneration circuit 4 (:) to obtain a clock signal 101 synchronized with digital information. , equalization circuit 31: The more equalized signal is
The signal is input to the C circuit 5. The AGC circuit 5 includes an envelope detector 6 and a variable gain amplifier 7, and maintains the envelope amplitude at a constant value. The signal 100 thus obtained is the sixth
The eye pattern shown in the figure will be obtained. However, FIG. 6 illustrates the case where no noise component is included, and the data time kT (
T is the data period, k is an integer), the amplitude is +A, O
, -A. This signal 100 is inputted by eight three-value discrimination circuits. Further, a clock signal 101 is also input to the three-value discrimination circuit 8 at the same time.

Here, the configuration of the three-value discrimination circuit 8 is shown in FIG.

The three-value discrimination circuit 8 includes a three-value comparison circuit 9 and a latch circuit 10.
It consists of In addition to the signal 100, the ternary comparison circuit 9 receives a signal 111 and a signal 112 indicating a predetermined fixed threshold amplitude. Signal 111. Signal 112 is connected to Al1. -A
The amplitude values of l1 are shown respectively. From these, the ternary comparison circuit 9 calculates a signal 1 indicating whether the amplitude of the signal 100 is smaller than the amplitude A,/2 indicated by the signal 111 and larger than the amplitude -A1 indicated by the signal 112, or otherwise.
Outputs 13. The signal 113 is applied to the latch circuit 10 at the timing of the clock signal 101 (time k in FIG.
T) and outputs the original digital information 102.

As described above, digital information is detected from the partial response equalized signal.

Problems to be Solved by the Invention As is clear from the eye pattern in FIG. 6, the bit error rate is lowest when the threshold level is set near 1/2 of the signal amplitude at time kT. Therefore, as shown in FIG. 7, the signal 111.
If ±A/2 is input as the threshold level to signal 112, the error rate will deteriorate if the amplitude at kT in FIG. 6 varies from ±A. Therefore, in the conventional configuration shown in FIG. 5, the AGC circuit 5 controls the signal amplitude to a target value. However, the AGC circuit 5
The 0 envelope amplitude is configured to be the target value, and the envelope amplitude does not necessarily indicate the signal amplitude at time kT of data, but also includes amplitudes at other times. For example, the envelope amplitude at time to in FIG. 6 varies greatly depending on the content of the digital information series.

Therefore, the envelope amplitude detected by the envelope detector 6 in FIG. 5 also changes. As a result, the amplitude of the output signal of the AGC circuit 5 also changes depending on the content of the digital information series, and the amplitude at data time kT varies from +A or -A shown in FIG. 2, causing the bit error rate to deteriorate. There was an issue with the problem.

Furthermore, since the clock is regenerated from the ternary eye pattern signal shown in FIG. 6, a stable lock cannot be easily regenerated, resulting in a problem in that the code error rate deteriorates.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a digital information detection device that can stably detect data without deteriorating the code error rate even if the envelope amplitude changes depending on the content of a digital information sequence. It is said that

Another object of the present invention is to provide a digital information detection device that can easily stabilize and reproduce lock and has a low error rate due to clock reproduction errors.

Means for Solving the Problems In order to achieve the above object, the digital information detection device of the present invention includes first equalization means for equalizing a PCM signal transmitted or reproduced from a recording medium so as to suppress intersymbol interference. and a clock reproducing means for reproducing a clock signal from the output signal of the equalizing means, and a second equalizing means for performing partial response equalization on the output signal of the first equalizing means.
amplitude detection means for detecting amplitude from the output of the first equalization means; digital information from the output signal of the second equalization means and the amplitude information obtained from the amplitude detection means at the timing of the clock signal; and discriminating means for discriminating.

Effect of the Invention With the above-described configuration, the present invention detects the amplitude at the clock point and controls the discrimination means, so even if the envelope amplitude changes depending on the content of the digital information series, the code error rate will deteriorate accordingly. It is possible to stably detect digital information without any problems.

In addition, since the clock is regenerated from a signal that has been equalized to suppress intersymbol interference, stable lock can be easily regenerated and the error rate due to clock regeneration errors is low.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment in which a digital information detecting device of the present invention is applied to a digital magnetic recording/reproducing device. A PCM signal recorded on a magnetic medium is reproduced by a magnetic head 1. The reproduced signal is amplified by the head amplifier 2 and equalized by the equalization circuit 20. The frequency characteristic F(w) of the equalization circuit 20 is the frequency characteristic of the system from recording to the output of the head amplifier 2, expressed as H(
w ) and the frequency characteristic of a roll-off filter that satisfies the Nyquist criterion is L(w), the following equation is satisfied.

F(w)-L(w)/H(w) This equalizes the reproduced signal to reduce intersymbol interference. As a result, the output signal 120 of the equalization circuit 2o
is a signal that can be expressed by a binary eye pattern as shown in FIG. 2. However, the eye pattern in FIG. 2 illustrates the case where no noise component is included.

Next, the signal 120 is input to the clock recovery circuit 21,
A clock signal 103 synchronized with digital information is obtained.

Here, since the signal 120 is a binary 1-eye pattern signal that has been equalized so that intersymbol interference is suppressed as described above, it is a normal P
The LL circuit makes it easy to stabilize and regenerate lock.

Now, the signal 120 is input to the amplitude detection circuit 25 on the other hand. The amplitude detection circuit 25 includes the sample hold circuit 2
6. It is composed of an absolute value circuit 27 and an LPF 28.

The sample and hold circuit 26 samples the signal 120 at time kT in FIG. 2 at the timing of the clock signal 103 and holds the value. As is clear from FIG. 2, since sampling is performed at a time when there is no intersymbol interference, the amplitude is determined to be +A or -A regardless of the content of the digital information. The output of the sample hold circuit 26 is output to the absolute value circuit 2.
7 obtains the absolute value of the amplitude, and LPF 28 smoothes the signal to remove unnecessary fluctuation components due to noise (thereby obtaining amplitude information 123. In this way, the amplitude information 123 is obtained instead of the envelope amplitude (
, in order to detect the amplitude at the data time, accurate amplitude information at the data time 1 is obtained regardless of the content of the digital information series.
23 is obtained. That is, when the signal 120 is shown by the eye pattern in FIG. 2, the amplitude information 123 indicates the value of A.

On the other hand, the signal 121 is also input to the partial response equalization circuit 23. The partial response equalization circuit 23 performs equalization so that the intersymbol interference becomes (1, -1). The configuration of the partial response equalization circuit 23 is shown in FIG. A delay circuit 30 that delays the signal 121 by one data period T to obtain the signal 130. signal 121
a subtraction circuit 31 for subtracting signal 130 from . and a coefficient circuit 32 which obtains a signal 122 by halving the amplitude of the output signal of the subtraction circuit 31. As a result, the signal 122 becomes a signal equalized so that the intersymbol interference becomes (1, -1), and becomes a signal shown by the eye pattern shown in FIG.

Now, the equalized signal 122 is input to the ternary discrimination circuit 24. The three-value discrimination circuit 24 also includes amplitude information 123 indicating the amplitude at the data time and a clock signal 103.
are also input at the same time. The three-value discrimination circuit 24 is configured as shown in FIG. In other words, the threshold signal 124 is obtained by multiplying the partial response equalized signal 122 and the amplitude information 123 by 1/2 in the coefficient circuit 40. A threshold signal 125 obtained by multiplying the amplitude information 123 by 1 1/2 in the coefficient circuit 41 is input to the three-value comparison circuit 42, respectively. The ternary comparison circuit 42 outputs a signal 126 indicating whether the amplitude of the signal 122 is smaller than the amplitude indicated by the signal 124 and greater than the amplitude indicated by the signal 125, or otherwise. The signal 126 is latched in the latch circuit 43 at the timing of the clock signal 103 (time kT in FIG. 6), and the original digital information 102 is output.

As described above, digital information is detected from the partial response equalized signal.

As described above, in this embodiment, the amplitude at the data time is detected and the threshold amplitude is controlled accordingly, so that even if the signal amplitude fluctuates, the original digital information can be detected accurately. In addition, since the amplitude at the data time is detected instead of the envelope amplitude, it is not affected even if the envelope amplitude changes depending on the contents of the digital information series (the original digital information can be detected stably). is possible.

In addition, since the clock is regenerated from a signal that has been equalized to suppress intersymbol interference, it is possible to easily regenerate a stable lock, and the error rate due to clock regeneration errors is low.

Note that in this embodiment, partial response equalization is performed so that the intersymbol interference becomes (1, -1), but the present invention is not limited to this, and can be applied to any partial response method. It can also be applied to Also,
Although the embodiments described above apply the present invention to a digital magnetic recording/reproducing device, the present invention is not limited thereto, and can be applied to detection of digital information from a communication transmission path or an optical recording/reproducing device. It can also be applied to digital information detection, etc.

Effects of the Invention As described above, the digital information detection device of the present invention detects the amplitude at the data time and controls the discrimination means, so that the original digital information can be accurately detected even if the signal amplitude fluctuates. In addition, since the amplitude at the data time is detected instead of the envelope amplitude, it is not affected even if the envelope amplitude changes depending on the content of the digital information series, and the original digital information can be detected stably. It is possible.

In addition, since the clock is regenerated from a signal that has been equalized to suppress intersymbol interference, stable lock can be easily regenerated and the error rate due to clock regeneration errors is low.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a digital information detection device of the present invention, FIG. 2 is an eye pattern diagram explaining the operation of the embodiment, and FIG. 3 is a configuration of a partial response equalization circuit in the embodiment. 4 is a configuration diagram of a three-value discrimination circuit in the embodiment, FIG. 5 is a configuration diagram showing a conventional digital information detection device, FIG. 6 is a configuration diagram of a three-value discrimination circuit in a conventional example, and FIG. is an eye pattern diagram explaining the operation of the conventional example. 20...Equalization circuit, 21...Clock regeneration circuit, 23...Partial response equalization circuit, 25...Amplitude detection circuit, 26...・・・
...Sample, hold circuit, 27...Absolute value circuit, 28...LPF. Name of agent: Patent attorney Haruaki Ogata Two people Figure 2 Figure 6 kT t.

Claims (2)

[Claims] (1) a first equalization means for equalizing a PCM signal transmitted or reproduced from a recording medium so as to suppress intersymbol interference; and a clock reproduction means for reproducing a clock signal from the output signal of the equalization means; a second equalization means for performing partial response equalization on the output signal of the first equalization means; an amplitude detection means for detecting an amplitude from the output of the first equalization means; and a second equalization means for detecting an amplitude from the output of the first equalization means. A digital information detecting device comprising discriminating means for discriminating digital information from an output signal of the means and amplitude information obtained from the amplitude detecting means at the timing of the clock signal. (2) The digital device according to claim 1, wherein the amplitude detection means comprises absolute value means for obtaining the absolute value of the output signal amplitude of the first equalization means and smoothing means for smoothing the output of the absolute value means. Information detection device.