JPH04180263A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable small-quantity multi-kind products to be manufactured more easily with manufacture conditions kept constant regardless of contents of mount circuits by arranging cells having metallized patterns connected to neither in-chip elements nor other wirings and by substantially uniforming the total wiring length of each wiring layer regardless of mount circuits. CONSTITUTION:Basic cells 11-15 are arranged in a plural array form, and wiring channels 16 are provided between these basic cell arrays. A basic cell 14 contains only a dummy wiring connected to neither in-chip elements nor wirings. In the case of a large scale of a mount circuit with a long total length of wiring, dummy wiring cells 14 are arranged in a small number; reversely in the case of a small scale of a mount circuit with a short length of wiring, they are arranged in a large number, whereby the total wiring length of each wiring layer is substantially uniformed. This design makes manufacture conditions constant regardless of the scale of mount circuits and enables easy manufacture of small-quantity multi-kind products.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a gate array type semiconductor integrated circuit device (hereinafter simply referred to as "gate array").
(referred to as ).

[Prior Art] In a conventional gate array of this type, a plurality of elements arranged to form a basic circuit, such as a two-man NAND circuit or a four-man NOR circuit, are grouped together (
(Hereinafter, a group of such elements will be referred to as a "cell")
A desired circuit is formed by arranging a plurality of such cells in parallel on an array rod and wiring only necessary elements among the plurality of elements in a wiring process. FIGS. 3(a) and 3(b) show the arrangement of a conventional gate array,
A partial configuration example of each wired cell array is schematically shown. The basic cells 31 to 35 are arranged in a plurality of rows, and a wiring channel 36 is provided between the basic cell rows constituted by the basic cells 31 to 35 arranged in these rows. The basic cell 31 has an inverter circuit, the basic cell 32 has a two-man power NOR circuit, the basic cell 33 has a two-man power AND circuit, and the basic cell 34 has a two-man power NAN circuit.
A D circuit is configured within each cell. Basic cell 35 is an unused cell. The gate array shown in FIG. 3(a) has a large circuit scale and no unused cells, and the gate array shown in FIG. 3(b) has a small circuit scale and no unused cells. This is an example of a gate array in which a large number of cells 35 are used.

In gate arrays, the number of elements on a chip is constant regardless of the content of the circuits installed, but the number of cells used and the total wiring length of each wiring layer depend on the circuits installed. . In other words, as shown in Fig. 3(a), in a chip with a large circuit scale and almost no unused cells, a large number of wirings are required within the cells and between the cells, and as a result, each wiring The total wiring length of the layer becomes longer. On the other hand, as shown in Figure 3(b), in a chip with a small circuit scale and a large number of cells left unused, a large number of intra-cell and inter-cell wiring is not required. As a result, the total wiring length of each wiring layer becomes shorter.

On the other hand, when manufacturing products such as gate arrays in small quantities and in a wide variety of products, it is easier to manufacture products by standardizing manufacturing methods and manufacturing conditions as much as possible. For this reason, for gate arrays, the manufacturing method and manufacturing conditions are completely standardized up to the wiring process, regardless of the content of the mounted circuit, and even in the wiring process, apart from the mask for wiring formation, there is no dependence on the mounted circuit. First, the manufacturing method and manufacturing conditions are the same.

[Problems to be Solved by the Invention] As mentioned above, in conventional gate arrays, the number of elements on a chip is constant regardless of the mounted circuit, but the position of the cells used and the total number of each wiring layer are The wiring length depends on the circuit to be mounted.

On the other hand, when wiring is formed by plating, the thickness of the wiring layer is proportional to the plating time and inversely proportional to the surface area of the wiring in the wiring layer to be plated. Therefore, if the total wiring length of each wiring layer, that is, the surface area of the wiring, differs depending on the circuit mounted, in order to make the wiring thickness constant regardless of the mounted circuit, the plating time must be adjusted according to the total wiring length of each wiring layer. It must be changed in proportion to the length, and manufacturing conditions must be changed depending on the content of the mounted circuit. Therefore, in the manufacture of a wide variety of products in small quantities, such as gate arrays, there is a problem in that the manufacturing process becomes complicated. Conversely, if the manufacturing conditions are constant regardless of the mounted circuit, the wiring layer will be determined in inverse proportion to the total wiring length of each wiring layer, that is, the surface area of the wiring, so the wiring layer will differ depending on the content of the mounted circuit. There was a problem with it being put away.

In addition, if the total wiring length of each wiring layer is short, the probability that signal lines in different layers will cross each other is low (as a result, the wiring capacitance is reduced by the amount of cross wiring capacitance. Conversely, each wiring layer The longer the total wiring length, the higher the probability that signal lines in different layers will cross each other, which increases the wiring capacitance by the amount of cross wiring capacitance.Therefore, the method for estimating delay time is If the delay time is set constant without considering the content, there is a problem that a difference occurs between the estimated delay time and the actual delay time depending on the scale of the installed circuit.

The present invention has been made in view of such problems, and includes:
To make the total wiring length of each wiring layer uniform regardless of the content of the mounted circuit, to make manufacturing conditions constant regardless of the content of the mounted circuit, and to more easily manufacture products of a wide variety of products in small quantities. It is an object of the present invention to provide a gate array that allows a method for estimating delay time to be constant regardless of the content and scale of the mounted circuit.

[Means for Solving the Problems] The gate array according to the present invention has a structure in which cells mounted on the chip are arranged in a chip with a metallized pattern that is not connected to any element in the chip or connected to any other wiring. It is characterized in that the total wiring length of each wiring layer is made substantially uniform regardless of the content of the wiring.

[Function] In the gate array of the present invention, cells having a metallized pattern that is not connected to any element in the chip and not connected to any other wiring are arranged in the chip, so that each wiring layer can be connected regardless of the mounted circuit. The total wiring length can be made substantially uniform. Therefore, it is possible to keep the manufacturing conditions constant regardless of the content of the mounted circuit, and it is possible to more easily manufacture a wide variety of products in small quantities. Furthermore, even if the method for estimating the delay time is constant regardless of the content of the mounted circuit, it is possible to estimate the delay time independent of the scale of the mounted circuit.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 schematically shows the layout of a gate array and the configuration of a part of a wired cell array in a first embodiment of the present invention.

The basic cells 11 to 15 are arranged in a plurality of columns, and a wiring channel 16 is provided between the basic cells arranged in the columns. The basic cell 11 has an inverter circuit,
The basic cell 12 has a two-man power NOR circuit, and the basic cell 13 has a two-man power AND circuit. In the basic cell 14, only dummy wiring is formed, in which wiring that is not connected to any element in the chip or connected to any other wiring is routed to all the wiring channels in the cell. This is a cell (hereinafter referred to as a "dummy wiring cell") that does not take up much space or consumes power. Basic cell 15 is an unused cell. The dummy wiring cell 14 is appropriately placed in a portion that should originally be an unused cell 15.

If the scale of the mounted circuit is large and the total wiring length required to realize the circuit is long, reduce the number of dummy wiring cells 14. Conversely, if the scale of the mounted circuit is small and the total wiring length required to realize the circuit is When the wiring length is short, by arranging a large number of dummy wiring cells 14, it is possible to make the total wiring length of each wiring layer substantially uniform regardless of the scale of the mounted circuit. By doing this, the surface area of the wiring in each wiring layer is constant regardless of the scale of the mounted circuit, so even when wiring is formed by plating, the manufacturing conditions can be kept constant regardless of the scale of the mounted circuit. and
It is possible to manufacture a wide variety of products in small quantities more easily. Note that the wiring of the dummy wiring cell 14 in this embodiment does not have to be on the wiring channel within the cell, and even if the wiring has an arbitrary width, there is no functional problem as long as it is within the cell area.

FIG. 2 schematically shows the layout of a gate array and the structure of a part of a wired cell array according to a second embodiment of the present invention.

The basic cells 21 to 25 are arranged in a plurality of columns, and wiring channels 26 are provided between the basic cells arranged in the columns. The basic cell 21 includes an inverter circuit, the basic cell 22 includes a two-person NOR circuit, and the basic cell 23 includes a two-person AND circuit. The basic cell 24 is a dummy wiring cell configured by forming a dummy wiring, which is not connected to any element in the chip or to any other wiring, in a part of the wiring channel in the cell, and is configured to perform logic. It does not consume electricity. The dummy wiring cell 24 is placed in a portion that should originally be an unused cell.

In the dummy wiring cell 14 in the first embodiment described above, wiring that is not connected to any element or to any other wiring is wired in all the wiring channels in the cell, so that the inter-cell wiring is is this dummy wiring cell 14
The inter-cell wiring is dummy wiring cell 1.
4, the wiring length may become longer and the delay time may increase. On the other hand, in this second embodiment, a wiring that is not connected to any element or to any other wiring is only wired in a part of the wiring channel in the cell, so a dummy wire is used as necessary. Intercell wiring can be provided to pass through the wiring cells. Therefore, it is not necessary to provide inter-cell wiring by detouring the dummy wiring cell portion, and it is possible to shorten the wiring length and shorten the delay time. Therefore, in this embodiment, not only can the total wiring length of each wiring layer be made uniform, but also the inter-cell wiring can be provided so as to pass over the dummy wiring, which is different from the conventional example. Compared to the first embodiment of the present invention, the probability that signal lines in different layers intersect with each other tends to be uniform regardless of the scale of the mounted circuit. Therefore, since the cross capacitance of the wiring becomes uniform, the wiring capacitance becomes constant regardless of the circuit scale. Furthermore, even if the delay time estimation method is constant regardless of the mounted circuit, there is an advantage that there is no difference in estimation depending on the mounted circuit.

[Effects of the Invention] As described above, according to the present invention, a dummy wiring cell having a metallized pattern that is not connected to any element in the chip or connected to any other wiring is arranged, and the content of the mounted circuit is Regardless, by making the total wiring length of each wiring layer uniform, it is possible to keep the manufacturing conditions constant regardless of the content of the mounted circuit, making it easier to manufacture a wide variety of products in small quantities. Furthermore, even if the method for estimating delay time is constant regardless of the mounted circuit, it is possible to provide a gate array in which delay time can be estimated without depending on the scale of the mounted circuit.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the layout of a gate array and the configuration of a part of a wired cell array according to a first embodiment of the present invention;
The figure is a schematic diagram showing the layout of a gate array according to the second embodiment of the present invention and the configuration of a part of the wired cell array, and FIG. 3 is the layout of a conventional gate array and the configuration of a part of the wired cell array. It is a schematic diagram showing an example.

Claims (1)

[Claims] (1) In a gate array type semiconductor integrated circuit device,
A semiconductor integrated circuit characterized by arranging cells having metallized patterns that are not connected to any of the elements or other wiring within the chip, and making the total wiring length of each wiring layer substantially uniform regardless of the mounted circuit. Device.