JPH04177861A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable an input protection circuit which matches the purpose of use by forming a needed wiring pattern at an NMOS transistor region of an external cell region and a PMOS transistor region. CONSTITUTION:A signal wire 7 for connecting a pad, a first N<+>-type diffusion layer 3A of an NMOS transistor region, and a first P<+>-type diffusion layer 4A of a PMOS transistor region with a contact 8, a ground wire 9 which connects a second N<+>-type diffusion layer 3B of the NMOS transistor region and a first polysilicon layer 2A with the contact 8, and a power supply wiring 10 which connects a second P<+>-type diffusion layer 4B of PMOS transistor region and a second polysilicon layer 2B with the contact 8 are formed, thus constituting a diode 11 where a junction surface between a P-type substrate 5 and a second N<+>-type diffusion layer 3B grounds an anode and a diode 12 where a junction surface between an N well 6 and the P<+> diffusion surface 4B allows a cathode to be connected to the power supply for constituting an input protection circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of an input protection circuit for a gate array.

[Conventional technology]

As shown in FIG. 7, a conventional gate array has a structure in which an internal cell region 22 is disposed on a semiconductor substrate 20, an external cell region 21 forming an input/output interface, and a pad 1 outside the internal cell region 22. As shown in the plan view of FIG. 10 and the equivalent circuit diagram of FIG. A resistor 15 made of polysilicon wiring 20 and P
It consisted of a type substrate 5 and a diode 11 consisting of an N++ diffused layer 30, and was connected between the pad 1 and the internal cell region buffer 13.

That is, the polysilicon wiring 20 in the external cell area constitutes the resistor 15, the N+ type diffusion layer 30 in the P type substrate 5 connected to the ground potential constitutes the diode 11 whose anode is grounded, and these are The pad 1 and the internal cell area buffer 13 are connected by a signal wiring 7.

In addition, as shown in the plan view of FIG. 11 and the equivalent circuit diagram of FIG. The junction plane connects the diode 11 whose anode is grounded, and the N well 6 and P+ connected to the power supply (VDD).
The junction surface of the type diffusion layer 40 constitutes a diode 12 whose cathode is connected to the power supply, and these are connected between the pad 1 and the internal cell area buffer 13 via the signal wiring 7 to constitute an input protection circuit. There is also.

In this manner, the conventional gate array input protection circuit is fixed by elements configured in the input protection circuit area within the external cell area.

[Problems to be Solved by the Invention] In the conventional gate array input protection circuit described above, the circuit is fixed by elements configured in the input protection circuit area, and the semiconductor having the input protection circuit shown in FIG. When the device is mounted, if you perform hot-swapping to insert or remove the gate array from the device while the power is on, the power supply (VDD)
Alternatively, a signal enters with the ground line (GND) floating, causing a large current to flow between the signal line and the input protection diode, causing it to malfunction.

Further, in the case of a semiconductor device having the protection circuit shown in FIG. 9, it can withstand hot insertion and removal, but has a low breakdown voltage and is slow in speed.

Therefore, there is a problem in that the method of use is limited depending on which input protection circuit is selected.

Furthermore, in order to enable selective formation of two input protection circuits by wiring, the area of the input protection circuit region must be increased, which reduces the degree of integration.

[Means to solve the problem]

The semiconductor device of the first invention includes an internal cell region formed in the center of a P-type substrate, a first polysilicon layer formed around the internal cell region, and a first polysilicon layer for the P-type substrate and a gate electrode. A transistor region, an N well, a second polysilicon layer for a gate electrode, and a second polysilicon layer for a gate electrode. It is equipped with an external cell region having a PMOS transistor region consisting of first and second P1 type diffusion layers aligned with each other by a silicon layer, and a pad provided around this external cell region, and has a wiring. In the semiconductor device in which an input protection circuit is formed between the buffer in the internal cell region and the pad by forming a first N+ of the pad and the NMOS transistor region.
A type diffusion layer is formed in the first P+ region of the PMOS transistor region.
a signal wiring connecting the type diffusion layer, a ground wiring connecting the second N+ type diffusion region of the NMOS transistor region and the first polysilicon layer, and a second P+ type diffusion layer of the PMOS transistor region. A power supply wiring connecting the first polysilicon layer and the second polysilicon layer is formed.

The semiconductor device of the second invention includes an internal cell region formed in the center of a P-type substrate, a polysilicon layer formed around this internal cell region, and a polysilicon layer for the P-type substrate and a gate electrode. It includes an external cell region having an NMOS (NMOS) transistor region consisting of first and second N+ type diffusion layers aligned with each other by a polysilicon layer, and a pad provided around the external cell region. In the semiconductor device in which an input protection circuit is formed between the buffer in the internal cell region and the pad by forming a signal wiring connecting the pad and the first and second N+ type diffusion layers in the NMOS transistor region. It was formed.

A semiconductor device according to a third aspect of the invention includes an internal cell region formed in the center of a P-type substrate, a first polysilicon layer formed around the internal cell region, and a first polysilicon layer for the P-type substrate and a gate electrode. A transistor region, an N well, a second polysilicon layer for a gate electrode, and a second polysilicon layer for a gate electrode. It includes an external cell region having a PMOS transistor region consisting of first and second P+ type diffusion layers aligned with each other by a silicon layer, and a pad provided around this external cell region, and has a wiring. In the semiconductor device in which an input protection circuit is formed between the buffer in the internal cell region and the pad, the first and second N+ type diffusion layers in the pad and the NMOS transistor region are connected to the first and second N+ type diffusion layers in the PMOS transistor region. A signal wiring is formed to connect the first and second P+ type diffusion layers.

A semiconductor device according to a fourth aspect of the present invention includes an internal cell region formed in the center of a P-type substrate, a first polysilicon layer formed around the internal cell region, and a first polysilicon layer for the P-type substrate and a gate electrode. A transistor region, an N well, a second polysilicon layer for a gate electrode, and a second polysilicon layer for a gate electrode. It includes an external cell region having a PMOS transistor region consisting of first and second P+ type diffusion layers aligned with each other by a silicon layer, and a pad provided around this external cell region, and has a wiring. In the semiconductor device in which an input protection circuit is formed between the buffer in the internal cell region and the pad by forming an input protection circuit between the pad and one end of the second polysilicon layer in the PMOS transistor region and the second polysilicon layer. A signal wiring is formed to connect the other end to the first and second N- type diffusion regions of the NMOS transistor region.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan view of a buffer area in an external cell area for explaining the present invention in detail, FIG. 2 is a plan view of a buffer area for explaining a first embodiment of the present invention, and FIG. 8
This shows a case where the input protection circuit shown in the figure is configured by wiring.

In FIG. 1, a P-type substrate 5 includes a first polysilicon layer 2A for a gate electrode, and first and second N-type substrates provided in alignment with each other by this first polysilicon layer 2A.
An NMOS transistor region consisting of a + type diffusion layer 3A3B, an N well 6, a second polysilicon layer 2B for a gate electrode, and first and second polysilicon layers aligned with each other by this second polysilicon layer 2B. An external cell region having a PMO3) runcisor region consisting of P" type diffusion layers 4A and 4B, and a pad 1 provided around this external cell region are formed.

As shown in FIG. 2, pads 1 and N
The first N+ type diffusion layer in the MOS transistor region is 3AP
A signal wiring 7 that connects the first P+ type diffusion layer 4A in the MOS transistor region with the contact 8, and a ground that connects the second ON+ type diffusion region 3B of the NMOS transistor region and the first polysilicon layer 2A with the contact 8. A wiring 9 and a power supply wiring 10 connecting the second P" type diffusion layer 4B and the second polysilicon layer 2B in the PMO3 transistor region with a contact 8 are formed.

The junction surface of the P type substrate 5 and the second N'' type diffusion layer 3B connected to the ground F' (GND) wiring connects the diode 11 whose node is grounded to the N well 6 connected to the power supply (VDD). The junction surface between P+ diffusion layer 4B connects the cathode to the power source (V
DD), and the pad 1 and the first N+ type diffusion layer are connected by the signal wiring 7 between the first P+ type diffusion layer 4A and the internal cell area buffer 13. shows. The first N of the NMOS transistor region
One end of the + type diffusion layer 3A and the pad 1 are connected by the signal wiring 7A via the contact 8, and the N+ type diffusion layer is connected to the pad 1 through the contact 8.
The other end of A and one end of the second N" type diffusion layer 3B are the signal wiring 7B.
The other end of the second N+ type diffusion layer 3B and one end of another first N++ diffusion layer 3A are connected by a signal wiring 7C, and the other end of the N'' type diffusion layer 3A and the internal cell area are connected by a signal wiring 7C. Buffer 13 is connected by wiring 7D.

NMO3) The diffusion layer resistance from one end to the other end of the first and second N++ diffused layers 3A and 3B of the Lancistor region is resistance 15.
The first and second N+ type diffusion layers are made up of a diode 1 whose anode is grounded and whose junction surface with the P type substrate 5 is grounded to 3A3B.
5 and constitutes an internal upper protection circuit.

FIG. 5 is a plan view of a buffer area according to a third embodiment of the present invention, showing a case in which the input protection circuit of FIG. 8 is configured.

A diode 12 is formed by the N well 6 connected to the power supply and the first and second P+ type diffusion layers 4A and 4B, and the P type substrate 5 and the first and second N+ type diffusion layers are connected to the ground wiring. 3A3B to form a diode 11, and these are connected to pad l and internal cell area buffer 13 by signal wiring 7.
The input protection circuit is configured by connecting between the two terminals.

FIG. 6 is a plan view of a buffer area according to a fourth embodiment of the present invention. The resistor 15 is connected to the wiring resistance of the second polysilicon layer 2B in the PMOS transistor region, and the junction surface between the grounded P-type substrate 5 and the first and second N+ type diffusion layers 3A3B is a diode 11 whose 7 nodes are grounded. constitutes the ninth
Configure the input protection circuit shown in the figure.

〔Effect of the invention〕

As explained above, the present invention provides an input protection circuit suitable for the purpose of use by forming a necessary wiring pattern in a buffer region of the same base having an NMOS transistor region and a PMOS transistor region in an external cell region of a gate array. It has the effect of being able to configure.

[Brief explanation of the drawing]

FIG. 1 is a plan view of the buffer area for explaining the present invention in detail, FIG. 2 is a plan view of the buffer area of the first embodiment of the invention, and FIGS. 3 and 4 are the plan views of the buffer area of the first embodiment of the invention. Plan view and equivalent circuit diagram of the buffer area of the second embodiment, FIGS. 5 and 6
The figure is a plan view of the buffer region of the third and fourth embodiments of the present invention, FIG. 7 is a plan view of the semiconductor chip for explaining the gate array, and FIGS. 8 and 9 are for explaining the embodiments. 10 and 11 are plan views of a buffer region of a conventional semiconductor device. ■...Pad, 2A...First polysilicon layer, 2B...Second polysilicon layer, 3A...
...First N" type diffusion layer, 3B... Second N+ type diffusion layer, 4A... First P+ type diffusion layer, 4B...
・Second P+ type diffusion layer, 5...P type substrate, 6.
...N Wenope 7゜7A~7F...Signal wiring, 8...Contact, 9...Cland wiring, 10...Power supply wiring, 11°11A
... Diode, 12 ... Diode, 13 ... Internal cell area buffer, 15.15A
...Resistor, 20...Semiconductor substrate, 21...
...External cell area, 22...Internal cell area, 30...N" type diffusion layer. Agent Patent attorney Uchihara Oto 3A First N+ type expansion counterfeit OtsujN Well 38
12's N+ type kaikishiki eyebrows Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 7E, 7F: Ci'Je & Figure 6 Figure 7 Figure 8 Figure 7 20, 't:') し' ) Core fAIK 30', N
"131-rJFigure 10Figure 11

Claims (1)

[Claims] 1. An internal cell region formed in the center of a P-type substrate, a first polysilicon layer formed around this internal cell region, and a first polysilicon layer for the P-type substrate and a gate electrode; An NMOS transistor region consisting of first and second N^+ type diffusion layers provided in alignment with each other by a first polysilicon layer, an N well, a second polysilicon layer for a gate electrode, and this second polysilicon layer. first and second P aligned with each other by a silicon layer;
An external cell region having a PMOS transistor region consisting of a ^+ type diffusion layer, and a pad provided around this external cell region, and by forming a wiring, a connection between the buffer in the internal cell region and the pad is provided. In a semiconductor device in which an input protection circuit is formed in a semiconductor device, the pad and the NM
The first N^+ type diffusion layer in the OS transistor region and the P
a signal wiring connecting the first P^+ type diffusion layer of the MOS transistor region; a ground wiring connecting the second N^+ type diffusion region of the NMOS transistor region and the first polysilicon layer; A semiconductor device characterized in that a power supply wiring connecting the second P^+ type diffusion layer in the PMOS transistor region and the second polysilicon layer is formed. 2. An internal cell region formed in the center of the P-type substrate and a polysilicon layer formed around this internal cell region and aligned with the P-type substrate and the polysilicon layer for the gate electrode. an external cell region having an NMOS transistor region including first and second N^+ type diffusion layers;
A pad provided around this external cell area,
In a semiconductor device in which an input protection circuit is formed between a buffer in the internal cell region and the pad by forming a wiring, the pad is connected to the first and second N^+ type diffusion layers in the NMOS transistor region. A semiconductor device characterized by forming signal wiring. 3. An internal cell region formed in the center of the P-type substrate, a first polysilicon layer formed around this internal cell region, and formed by the P-type substrate and the first polysilicon layer for the gate electrode. An NMOS transistor region consisting of first and second N^+ type diffusion layers provided in alignment, an N well, a second polysilicon layer for gate electrode, and an NMOS transistor region formed in alignment with each other by this second polysilicon layer. The first and second P provided
An external cell region having a PMOS transistor region consisting of a ^+ type diffusion layer, and a pad provided around this external cell region, and by forming a wiring, a connection between the buffer in the internal cell region and the pad is provided. In a semiconductor device in which an input protection circuit is formed in a semiconductor device, the pad and the NM
The first and second N^+ type diffusion layers in the OS transistor region and the first and second P^ type diffusion layers in the PMOS transistor region.
A semiconductor device characterized in that a signal wiring is formed to connect to a + type diffusion layer. 4. An internal cell region formed in the center of the P-type substrate, a first polysilicon layer formed around the internal cell region, the P-type substrate, a first polysilicon layer for a gate electrode, and this first polysilicon layer. An NMOS transistor region consisting of first and second N^+ type diffusion layers provided in alignment, an N well, a second polysilicon layer for gate electrode, and an NMOS transistor region formed in alignment with each other by this second polysilicon layer. The first and second P provided
An external cell region having a PMOS transistor region consisting of a ^+ type diffusion layer, and a pad provided around this external cell region, and by forming a wiring, a connection between the buffer in the internal cell region and the pad is provided. In the semiconductor device in which an input protection circuit is formed in the semiconductor device, the pad and the PM
Forming a signal wiring connecting one end of the second polysilicon layer in the OS transistor region, the other end of the second polysilicon layer, and the first and second N^+ type diffusion regions in the NMOS transistor region. A semiconductor device characterized by: