JPH04177738A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a fine gate having a T-shaped cross section by forming the opening of an upper electrode by optical exposure by using a negative resist for electron beams. CONSTITUTION:After an active layer 2 is formed on a semi-insulating GaAs substrate 1, a lower opening 10 is formed by applying a negative resist 7 for electron beams, exposing an electron beam exposure section 12 which is an area for supporting an upper electrode and has a certain width to an electron beam, and developing the exposed section 12. Then an upper opening 11 is formed by applying a resist 8 to the entire surface, subjecting the pattern of the upper electrode to optical exposure, and developing the exposed pattern. Since the negative resist 7 for electron beam is formed unsoluble, the resist does not melt at the time of development and a resist pattern having a T-shaped cross section can be formed at a gate pad section. Accordingly, the gate pad section can be formed with the resist 8. Therefore, a fine gate electrode having a T-shaped cross section can be formed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and in particular, a method of forming a low resistance fine gate of a high frequency field effect semiconductor device such as a high electron mobility transistor (HEMT). It is related to.

[Conventional technology]

In order to improve the characteristics of potassium arsenide (GaAs) high-frequency field effect transistors, a particularly short gate length and low resistance are required for the gate electrode.Therefore, research has been carried out on technology for forming gate electrodes with a T-shaped cross section. is being done.

FIG. 4 shows a conventional method of forming a gate electrode having a T-shaped cross section, as disclosed in, for example, Japanese Patent Laid-Open No. 6177370. In the figure, 21 is a semi-insulating GaAs substrate, 22 is a non-doped GaAs buffer layer, and 23 is an n-GaAs active layer (n-
1×1017 to 2×10”/cnf), 24 is the lower resist film, 25 is the double layer resist film, 26 is the line indicating gate pattern electron beam exposure, 27 is the line indicating electron beam auxiliary exposure, 28 is the upper layer 29 is an opening in the resist, 30 is a gate recess, 31 is a gate metal material, and 32 is a gate.

The conventional manufacturing method will be explained below with reference to FIG.

First, as shown in FIG. 4(a), a non-doped GaAs buffer layer 22 and an n-GaAs active layer 23 are epitaxially grown in this order on a semi-insulating substrate 2, and then a resist l-
Lower resist film 24 of CMR (CMR is resist l- described in JP-A No. 54-66829), resist EBR=
Upper layer resist 25 of 9 (product name of resist manufactured by Toshikukiki)
Form by applying. Next, these resists are coated as shown in Fig. 4(b).
The electron beam is irradiated to achieve the irradiation amount shown in . In this graph, the horizontal axis shows the position of the upper resist film 25, and the vertical axis shows the irradiation intensity, and the irradiation amount D is indicated by 27.
The symbol a indicates the auxiliary exposure for exposing only the upper resist layer 25, and the dose DO indicated by 26 indicates the dose for exposing the lower layer resist as well.

Electron beam exposure was performed at the dose shown in Figure 4(b), and then the resist film was developed with a mixture of methyl isobutyl ketone (MIBK) and isopropyl alcohol (IPA), as shown in Figure 4(C). Obtain a pattern.

Next, as shown in FIG. 4(d), a gate recess 30 is formed by wet etching using the resist film in the opening 29' as a mask. This gate recess is n-GaA
The active layer 23 is formed so as to leave a layer with an appropriate thickness that can block the current flowing through it.

Next, a gate metal material 31 such as Aff, Ti, or Au is deposited, and when the gate metal material 31 below the gate 32 is removed by lift-off, the gate has a length Lg and an upper dimension Lh as shown in FIG. 4(e). A gate 32 having a T-shaped cross section is obtained.

[Problem to be solved by the invention]

The conventional method for manufacturing T-shaped cross-sectional gates uses a two-layer resist structure and forms openings in the upper and lower resists by electron beam exposure. However, when a pattern is formed by electron beam exposure, the cross-sectional shape of the resist becomes inversely tapered. It is difficult to lift off the gate metal, and it is difficult to lift off the gate metal.
However, this method still required the use of electron beam exposure technology, which caused problems such as low mass production and low yields.

Furthermore, since a positive resist is used for the lower layer, it has poor resistance to wet etching for forming the gate recess, and the shape and controllability of the gate recess is poor, which hinders high performance.

In addition, a method has been proposed in which an opening is formed using a single-layer resist I-structure by changing the irradiation amount of the upper and lower gate electrode parts using electron beam exposure technology. The reproducibility of the resist shape corresponding to the pattern is poor, the irradiation amount of the lower gate electrode part is larger than the irradiation amount of the upper part, the exposure time is long, and as mentioned above, the pattern shape of the opening of the upper electrode is reversed. Since it does not have a tapered shape, there are problems such as the inability to stably form a gate with a T-shaped cross section using the lift-off method.

This invention was made to solve the above-mentioned problems, and it is possible to shorten the exposure time of electron beam exposure, stably form the resist pattern in the upper opening into a reverse taper shape, and use the lift-off method. An object of the present invention is to obtain a method for manufacturing a semiconductor device that can stably form a fine gate having a T-shaped cross section.

[Failure to solve the problem]

In order to solve the above problems, the present invention uses a two-layer resist structure. First, a negative resist for electron beam is used as the lower layer to support the upper electrode at a distance equal to the width of the gate length on both sides of the gate finger part. A region with a certain width is formed by electron beam exposure, then a resist is applied to the entire surface, and an opening corresponding to the upper electrode is formed on the resist pattern by optical exposure to form a resist shape with a T-shaped cross section. A fine gate having a T-shaped cross section is formed by depositing a gate electrode material and using a lift-off method.

[Effect]

In order to form a fine gate with low resistance, the method for manufacturing a semiconductor device according to the present invention uses a negative resist, which is spaced apart by the width of the gate length on both sides of the gate finger part, and has a certain width to support the upper electrode. The area was exposed to an electron beam, and then the entire surface was coated with resist 1, and a pattern corresponding to the upper gate electrode was formed on both sides of the gate finger part of the negative resist using optical exposure.''To partially support the electrode. Since the resist pattern is formed on the pattern, it is possible to form a resist pattern with a T-shaped cross section, where the second part dimension is in a reverse taper shape and the bottom dimension corresponding to the gate length is small. After the gate recess is formed, a gate metal material is deposited, By performing lift-off, a fine gate with a T-shaped cross section can be formed with good reproducibility, at low cost, and with high precision.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a cross-sectional view of a semiconductor device formed by an embodiment method of the present invention. In the figure, 1 is semi-insulating GaA
a substrate (semiconductor substrate), 2 is an active layer, 3 is a source electrode,
Reference numeral 4 indicates a drain electrode, 5 indicates a gate electrode, and 6 indicates a gate electrode.

The current flows through the active layer 3 in the left and right directions in the figure, and the length of the portion of the gate electrode 5 that is in contact with the active layer 2 that controls the current flows.
That is, it is possible to obtain a semiconductor with good characteristics, whether it is long or small.

FIG. 2 is a process flow diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the figure, 1 is a semi-insulating GaAa substrate, 2 is an active layer, 5 is a gate recess, and 6
is a gate electrode, 7 is a negative resist for electron beam, 8 is a resist I, 9 is a gate electrode material, 10 is a lower opening, 11
” respectively indicate a two-part opening.

Further, FIG. 3 shows a graph showing the position of a pattern subjected to electron beam exposure and its irradiation amount. In the figure, 12 is the electron beam exposure area, the vertical axis of the graph is the intensity of the irradiation amount, and the horizontal axis is the electron beam The positions of the negative resists 7 are shown.

Hereinafter, the manufacturing method will be explained using FIG. 2.

First, as shown in FIG. 2(a), after forming an active layer 2 by epitaxial growth on a semi-insulating GaAS substrate 1, a negative resist 1-7 for electron beam, for example, 5AL6
The film thickness was reduced to 0. ]~0.3 μm coating is formed. Next, the negative resist 7 for electron beam is subjected to electron beam exposure using the irradiation ff1o+ shown in the graph shown in FIG. For example, the electron beam exposure area 12, which is a region having a certain width to support a part of the electrode, is exposed to light at a distance of 0.2 μm from the gate length, and developed with an alkaline developer, resulting in the state shown in FIG. 2(b). get. Is the irradiation amount D1, for example, 5 to 20 μC/cn? The lower opening 10 is formed to have a thickness of 0.2 μm.

Next, as shown in FIG. 2 (FC), a resist 8 is coated on the entire surface. The resist at this time was positive type.

Either negative type may be used, and the thickness is 1 μm.

Next, a two-part electrode pattern with a width of, for example, 0.8 μm is formed on the resist pattern by optical exposure and development to form an upper opening 11, resulting in the state shown in FIG. 2(d). At this time, since the electron beam negative resistors I to 7 are negative, they are hardly dissolved by development. In this way, the gate finger portion can be formed with a resist pattern having a T-shaped cross section, and the gate pad portion can be formed using the resist 8.

Next, through the lower opening 010, using the negative resist 7 for electron beam as a mask, the gate recess 5 is etched by wet etching.
is formed, and a gate metal material 9, for example Aj?, is formed on the entire surface. , T
I, Au, etc. are deposited to obtain the state shown in FIG. 2(e). As shown in Figure 2), unnecessary gate metal phase material 9. Resist 8. The negative resist I-7 for electron beam is removed by a lift-off method to form a fine gate electrode with a T-shaped cross section.

According to the present invention, when forming a conventional two-layer resist structure using a positive resist for electron beams, the irradiation dose is 5 to 300 μC/crd, which was used to obtain a gate length of 0°2 μm. Since it can be performed at ~20 μC/cnr, it can be formed in 1/2 to 1/3 of the conventional exposure time, and is effective for mass production. Note that the source and drain electrodes are omitted in FIG.

As described above, according to this embodiment, in order to reduce the area to be exposed to the electron beam by coating a negative type resist for electron beam which has excellent resistance to web I and etching,
A resist film is applied to the entire surface, separated by the width of the gate length on both sides of a part of the finger, and exposed and developed to cover an area with a width sufficient to support the upper electrode. The exposed area was exposed to light, developed, and then a resist film was applied to the entire surface, and an opening corresponding to the two-part electrode was formed on the resist pattern by optical exposure. The Ga
It is effective in manufacturing As MESFETs and GaAs low-noise HEMTs.

〔Effect of the invention〕

As described above, according to the method of manufacturing a semiconductor device according to the present invention, a negative resist for electron beam is applied, and using electron beam exposure, the upper electrode A region with a certain width to support the upper electrode is exposed and developed to form a pattern to support the upper electrode and a fine gate I/groove opening, then a resist film is applied to the entire surface, and a resist film is formed on the resist pattern by optical exposure. By using an electron beam negative resist to form an opening for the upper electrode, the electron beam exposure time can be significantly shortened, and since it has excellent wet etching resistance, it is easy to form a gate recess. In addition, since the opening of the upper electrode is formed by optical exposure, it is easy to make the cross-sectional shape of the resist into a reverse taper shape, which has the effect of making it possible to stably create a fine gate with low resistance and excellent mass production. .

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a GaAs FET formed by a manufacturing method according to an embodiment of the present invention, FIG. 2 is a process diagram of an embodiment of the present invention, and FIG. 3 is a diagram showing the position of a pattern for electron beam exposure. A diagram showing the relationship with the irradiation amount, and FIG. 4 is a diagram showing the conventional manufacturing method. In the figure, I is a semi-insulating GaAs substrate, 2 is an active layer,
3 is a source electrode, 4 is a drain electrode, 5 is a gate recess, 7 is a negative resist for electron beam, 8 is a resist, 9
is the gate metal material, 1o is the lower opening, 11 is the upper opening,
12 is an electron beam exposure section, 21 is a semi-insulating GaAs substrate, 22 is a non-doped GaAs buffer layer, and 23 is an n-G
aAs active layer, 24 is a lower resist film, 25 is an upper resist film, 26 is a line indicating gate pattern electron beam exposure, 27 is a line indicating electron beam auxiliary exposure, 28 is an opening in the upper resist film, 29 is a lower resist film 30 is a gate recess, 31 is a gate metal material, and 32 is a gate. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a method of manufacturing a semiconductor device having a fine gate with a T-shaped cross section on a semiconductor substrate, there is a step of coating a negative electron beam resist on the substrate, and a step of forming a negative electron beam resist on both sides of the gate finger portion corresponding to the gate length. a step of exposing regions of the resist with an electron beam that are separated by a width corresponding to the upper electrode and having a width sufficient to support the upper electrode; a step of developing and removing the unexposed resist by electron beam exposure; and forming a resist film on the entire surface. A method for manufacturing a semiconductor device, comprising: forming an opening for an upper electrode on the resist pattern by optical exposure; and forming a gate recess, depositing a gate metal material, and lifting off.