JPH04177724A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive the improvement of the punch through-resistance characteristics of a MOS transistor without making large the total area of elements by a method wherein impurity ions are implanted in a semiconductor substrate using a deposited matter, whose side surfaces are respectively covered with each sidewall, as a mask and contact regions are formed in the substrate. CONSTITUTION:A LOCOS oxide film 2 consisting of an SiO2 film is formed on a silicon substrate 1 and after a deposited matter 5 consisting of Si3N4 or the like is formed on the film 2, sidewalls 8 are respectively formed of an insulating film, such as an SiO2 film or the like, on the side surfaces of the deposited matter 5. Impurity ion implantation is performed as shown by arrows using the matter 5 and the sidewalls 8 as masks, whereby a contact region 7 of an element A and a contact region 6 of an element B are formed. Thereby, an effective isolation length can be increased without making large the total area of the elements, in short, without making large the area of the film 2 and a dielectric isolation of a MOS transistor, which is superior in punch through-resistance characteristics, at an element isolation region can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a method for manufacturing an element isolation region.

[Conventional technology]

Regarding element isolation of MO3 type transistors, as a conventional method for manufacturing a semiconductor device, for example, there is a method shown in Ultra High Speed MOS Device (Baifukan) P, 121. In this manufacturing method, as shown in FIG. 4, after forming a LOCO8 oxide film 22, which is a field insulating film, on a semiconductor substrate 21,
Ion implantation is performed to form a contact region 23 of element (for example, MO3I-7 transistor) A and a contact region 24 (in this case, source/drain regions, respectively) of element (MO3I-transistor) B.

[Problem to be solved by the invention]

In the conventional manufacturing method of a semiconductor device using LOGO3 isolation in particular, (i) When impurity ions are implanted into the contact regions 23 and 24, they penetrate through the hearth F-shaped portion of the LOGO3 oxide film 22 and ion-implant impurities into the LOGO3 oxide film 22. It is also injected into the layer.

(n) After ion implantation into the contact regions 23 and 24,
Contact area 23.24 or LOG due to heat treatment process etc.
This will diffuse to the bottom of the OS oxide film 22.

For these reasons, the effective separation length becomes short, and especially under the design rules of ZAFMICRON, the punch-through resistance deteriorates, causing a serious problem in terms of reliability.

FIG. 5 shows the flake-down state of P channel LOGO3 separation. The horizontal axis shows the train-north voltage V D
S is taken, and the vertical axis is the rain current ■.

and source current Is. Compliance is applied at 0.2μA to protect the device. From this Figure 5, it seems that there is no problem in a semiconductor device with a separation length (=OD space) of 1.2 μm, and in a semiconductor device with a separation length (OD space) of 0.8 μm, the magnitudes of the drain current I and the north current ■8 are almost the same. . This means that the drain current does not flow to the substrate,
Since all of it is flowing to the source, it is considered that there is punch-through, and it can be seen that the insulation isolation characteristics have deteriorated significantly.

An object of the present invention is to provide a method for manufacturing a semiconductor device with excellent punch-through resistance without deteriorating the contact I/margin or increasing the total device area.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of forming a deposit on a field insulating film formed in a portion of the surface of a semiconductor substrate that will become an element isolation region, and forming an insulator to cover the side surfaces of the deposit. a step of forming a sidewall;
A contact region is formed in the semiconductor substrate by ion-implanting impurities into the semiconductor substrate using the deposit covered by the sidewall as a mask.

In this case, a step of oxidizing the semiconductor substrate may be included before the step of forming the deposit on the field insulating film, and a low concentration It may also include a step of ion-implanting impurities to form a low concentration contact region.

[For production]

After forming a deposit on the field insulating film on the semiconductor substrate and forming sidewalls to cover the sides of the deposit, in some cases the semiconductor substrate may be oxidized before the deposit is formed. Since a contact region is formed in the semiconductor substrate by ion-implanting impurities into the semiconductor substrate using the object and the sidewall on its side as a mask, the edge of the contact region must be a predetermined distance from the edge of the insulating film. become. As a result,
To obtain a semiconductor device in which the effective isolation length can be increased without increasing the element area of the I-tal, that is, without increasing the area of the field insulating film, and which has excellent punch-through resistance in the element isolation region. I can do it.

In fact, in the case of heat treatment after the formation of the contact region during ion implantation, the contact region diffuses into the side of the deposit, below the Idwi/L.
If the thickness of the sidewall is appropriately set, there will be no effect on the margin of contact with the contact region formed by metal wiring such as β.

In addition, by ion-implanting low-concentration impurities into the region under the sidewall to form a low-concentration contact region, the lateral electric field under the field insulating film is relaxed, making punch-through even more difficult to occur. can.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 118) to 118(d) show step-by-step sectional views of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

This embodiment corresponds to the configuration described in claim (1), and MO
This figure shows a manufacturing method applied to LOCOS separation of a 3I-transistor.

The manufacturing method in this example will be explained below.

First, as shown in FIG. 1(a), for example, a LOGO3 made of a SiO2 film with a thickness of 400 to 600 nm is placed on a P-type silicon substrate 1 with an impurity concentration of ~IE16 cm-3.
An oxide film 2 is formed.

Therefore, as shown in Figure 1 (1)), r, o c
Si:+Nt with a film thickness of about 250 nm on the o s oxide film 2
A deposit 5 such as the like is formed.

Next, as shown in FIG. 1(C), a Zite wall width of 200 nm is formed on the side surface of the deposit 5 using an insulating film such as 8102.
A sidewall 8 of about m is formed.

For example, after forming a gate electrode made of 8102 film with a film thickness of about 10 to 20 nm and a gate electrode with a gate length of about 0.6 to 0.8 μm in the transistor region, which is not shown in the figure, ), using the deposit 5 and sidewall 8 as a mask, impurity ions (P or As, 20 to 60
f(eV, IE15~IE16 cm-2
) to produce the contact region 7 to the device and the contact region 6 of the device B (which will become the source and train of the MO3+- transistor, respectively).

As described above, according to this embodiment, a deposit 5 is formed on the ocos oxide film 2, which is a field insulating film, and a sidewall 8 made of an insulating film is formed on the side surface of the deposit 5. After that, ion implantation is performed using the deposit 5 and the sidewall 8 as a mask to form a contact region 6.
, 7 are formed, the penetration of the bird's beak portion during ion implantation for forming the contact regions 6, 7 is prevented, and the contact regions 6, 7 are made of LOCO3 oxide film which is a field insulating film. 2, i.e. the edge of the contact area 6.7 is offset from L
It is separated from the edge of the OCO3 oxide film 2 by a predetermined distance. As a result, the effective isolation length can be increased without increasing the element area of the LOCO8 oxide film 2, and the MOS has excellent punch-through resistance in the element isolation region. It is also possible to isolate and isolate transistors.

In fact, in the heat treatment step after the formation of the contact regions 6.7 by ion implantation, the contact regions 6, 7 are either diffused to the bottom of the Zyte layer 8 on the side surface of the deposit 8, or If the thickness of 8 is appropriately set, it will not affect the margin of contact with contact regions 6 and 7 by metal wiring such as A1.

(Second Embodiment) FIGS. 2(a) to 2(d) show step-by-step sectional views of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

This embodiment corresponds to the configuration described in claim (2L (3)) and is an LDD (Lightly Doped Dray).
n) LOG of P-channel MO3 type transistor with structure
This shows a manufacturing method when applied to O3 separation.

The manufacturing method in this example will be explained below.

' First, as shown in Fig. 2(a), for example, a LOG is made of an SiO2 film with a thickness of about 400 to 600 nm on an N-type silicon substrate l with an impurity concentration of ~IE16 cm''.
An O3 oxide film 2 is formed.

Therefore, as shown in FIG. 2(b), by oxidizing the silicon substrate 1, a film thickness of 10 to 20 mm is formed in the transistor region.
After applying the gate oxide film 3 made of 8102 nm film, the gate length is 0.6 to 1.2 μm to the gate oxide film 3”.
At the same time as forming the gate electrode 4 made of a polysilicon film with a thickness of approximately
A deposit 5 made of a polysilicon film of the same thickness is formed on top, and then a low concentration impurity ion implantation (B or BF) is performed.
2゜2 (1~60KeV, I E l 3~l E
14cm-2) to form the first source 6A and first drain IOA of device A and the first source IIA of device B.

Next, as shown in FIG. 2 (C1), sidewalls 12 and 8 having a sidewall width of about 200 nm are formed on the side surfaces of the gate electrode 4 and the deposit 5 using an insulating film such as a SiO□ film.
are formed at the same time.

Next, as shown in FIG. 2(d), using the gate electrode 4° deposit 5 and sidewalls 12 and 8 as a mask,
Ion implantation of high concentration impurities (B or BF2,2(]
~60 KeV, IE]5~IE16 cm-2) to form the second source 9B and second I-twin IOB to the device, and the second source IIB (-contact region) of the device B.

As described above, according to the second embodiment, in addition to the effectiveness of the first embodiment, the first drain IOA to the element and the first source IIA of the element B, which are low concentration contact regions, can be connected to each other. Since the second train of element A and the second source of element B are formed on both sides of the LOGO3 oxide film 2, and the second train of element A and the second source of element B are formed on the outside thereof, the lateral electric field under the LOGOS oxide film 2 is relaxed. , punch-through becomes even less likely to occur.

FIG. 3 shows the breakdown characteristics of the P-channel MOS transistor manufactured according to this example.

The horizontal axis shows the drain-source voltage V. 8, and the vertical axis shows the drain current I and the source current I8. Compliance is applied at 0.2μA to protect the device. From this Figure 3, it can be seen that in the conventional example, 0.8
It can be seen that the punch-through that occurs at the separation length (=OD space) of μm, which does not occur at all in this example, is due to the excellent insulation isolation characteristics.

Also, the first drain IOA to the element, which is a low concentration contact region, and the first source IIA of element B are connected to LOGO3.
By providing it on both sides of the oxide film 2, the contact margin becomes large.

Moreover, it is applied to an MO3I-transistor with an LDD structure, and the gate electrode 4 and the deposit 5 on the LOGO3 oxide film 2 are simultaneously formed, and the sidewall 1 on the side surface of the gate electrode 4 is formed.
2 and the side wall 8 on the side surface of the deposit 5 on the LOGO 3 oxide film 2 are formed at the same time, so the number of processes can be carried out without increasing the number of processes at all.

In these embodiments, the transistor is an N-channel or P-channel MO3+- transistor, but the invention is not limited to this, and the present invention can be applied to a bipolar transistor as well.

In addition, as a field insulating film, LOGO3 oxide film 2
is taken as an example, but it is not limited to the LOGO3 oxide film 2. Also,
The deposit on the field insulating film is 313N4. Although polysilicon and the like are used as an example, the material is not limited to this and any material may be used.

Furthermore, although SiC2 is used as an example of the deposit (sidewall) on the side surface of the deposit, any material other than this may be used.

〔Effect of the invention〕

According to the manufacturing of the semiconductor device of the present invention, the edge of the contact region in the semiconductor substrate can be separated by a predetermined distance from the edge of the field insulating film formed on the semiconductor substrate. Therefore, the effective separation length can be increased without increasing the element area of 1.-tal, so that insulation isolation of a semiconductor device with excellent punch-through resistance can be realized.

After this, in a heat treatment process, etc., the contact region can be diffused to below the sidewall on the side of the deposit, or if the sidewall length is set appropriately, the margin of contact with the contact region by metal wiring such as AA will not be affected. do not have.

In addition, if a low concentration contact region is created under the sidewall on the side of the deposit on the field insulating film, this region will increase the contact margin and alleviate the lateral electric field under the field insulating film. Punch-through is even less likely to occur.

In addition, it can be applied to LDD structure MOS) transistors,
If the sidewalls on the sides of the gate electrode and the sidewalls on the sidewalls of the deposit on the field insulating film are formed at the same time, the process can be carried out without increasing the number of processes at all.

[Brief explanation of drawings]

FIG. 1 shows a semiconductor device (LOG) according to a first embodiment of the present invention.
2 is a step-by-step sectional view showing a method for manufacturing a semiconductor device (MOS transistor with an LDD structure that performs LOCO3 isolation) according to a second embodiment of the present invention. 3 is a characteristic diagram showing the breakdown characteristics of the P channel of the MO3+- transistor with the LDD structure shown in FIG. 2, and FIG. 4 is a process diagram showing a conventional method for manufacturing a semiconductor device that performs element isolation. A forward sectional view, FIG. 5 is a cross-sectional view of P in the semiconductor device shown in FIG.
FIG. 3 is a characteristic diagram showing breakdown characteristics of a channel. 1...Silicon substrate (semiconductor substrate), 2...LOGO
8 Oxide film (field oxide film), 3 - K-I oxide film, 4... Gate electrode, 5... Deposit, 6, 7 Contact region, 8... Side wall, 9A... First Source (contact region), 9B second source (contact l-region), I OA・* l l' rain (contact l-region), l0B-[2 drain (contact region), IIA... first source ( contact area), 1
1B...second source (contact region), 12...
Sidewall patent applicant: Matsushita Electric Industrial Co., Ltd.
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Claims (3)

[Claims] (1) A step of forming a deposit on a field insulating film formed on a portion of the surface of a semiconductor substrate that will become an element isolation region, and a step of forming a sidewall made of an insulating film to cover the side surface of the deposit. and forming a contact region in the semiconductor substrate by ion-implanting an impurity into the semiconductor substrate using the deposit whose side surface is covered with the sidewall as a mask. (2) The method for manufacturing a semiconductor device according to claim (1), further comprising the step of oxidizing the semiconductor substrate before the step of forming a deposit on the field insulating film. (3) Claim (1) or (2) includes the step of ion-implanting a low concentration impurity into a region below the sidewall on the side surface of the deposit on the field insulating film to form a low concentration contact region. A method for manufacturing a semiconductor device.