JPH04171921A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04171921A JPH04171921A JP2301541A JP30154190A JPH04171921A JP H04171921 A JPH04171921 A JP H04171921A JP 2301541 A JP2301541 A JP 2301541A JP 30154190 A JP30154190 A JP 30154190A JP H04171921 A JPH04171921 A JP H04171921A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- film
- contact hole
- polysilicon film
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は半導体装置に関し、特に、半導体装置中の導体
パターンに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a conductor pattern in a semiconductor device.
［従来の技術］
近年、ＤＲＭＡ （ランダムアクセスメモリ）などの半
導体装置の集積度を高めるために、コンタクトホールの
サイズが縮小されている。コンタクトホールの縮小は、
コンタクト抵抗値の増大やコンタクト不良を発生させる
原因となる。[Prior Art] In recent years, the size of contact holes has been reduced in order to increase the degree of integration of semiconductor devices such as DRMA (random access memory). The reduction of the contact hole is
This causes an increase in contact resistance value and contact failure.
特開昭６２−２０４５２３において、微小なコンタクト
ホールにおけるコンタクト抵抗値の改善やコンタクト不
良の発生防止が試みられている。Japanese Patent Laid-Open No. 62-204523 attempts to improve the contact resistance value in minute contact holes and to prevent the occurrence of contact failures.
第４八図ないし第４Ｄ図は、特開昭６２−２０４５２３
に開示された半導体装置中の導体パターンの形成過程を
示す概略的な断面図である。Figures 48 to 4D are from Japanese Patent Application Laid-Open No. 62-204523.
FIG. 3 is a schematic cross-sectional view showing a process of forming a conductor pattern in a semiconductor device disclosed in .
第４Ａ図を参照して、シリコン基板１上に、シリコン酸
化膜２がＣＶＤ （化学気相析出）によって形成される
。シリコン酸化膜２の上表面からシリコン基板１まで貫
通するコンタクトホール２ａがエツチングによって開け
られる。Referring to FIG. 4A, a silicon oxide film 2 is formed on a silicon substrate 1 by CVD (chemical vapor deposition). A contact hole 2a penetrating from the upper surface of silicon oxide film 2 to silicon substrate 1 is opened by etching.
第４Ｂ図を参照して、コンタクトホール２ａの内表面と
シリコン酸化膜２の上表面を覆うように、ポリシリコン
膜３がＣＶＤによって堆積される。Referring to FIG. 4B, polysilicon film 3 is deposited by CVD so as to cover the inner surface of contact hole 2a and the upper surface of silicon oxide film 2. Referring to FIG.
このポリシリコン膜３は、上方からの異方性エツチング
によって、コンタクトホール３の側壁上にのみ残される
。This polysilicon film 3 is left only on the side wall of the contact hole 3 by anisotropic etching from above.
第４Ｃ図を参照して、タングステン膜４が選択ＣＶＤに
よってコンタクトホール２ａの内表面上にのみ堆積され
る。タングステンは、ＣＶＤにおいて、シリコン上にの
み選択的に堆積されるので、タングステン膜４は、コン
タクトホールの底において露出されたシリコン基板１上
と側壁シリコン膜３上にのみ堆積され得る。したがって
、コンタクトホール２ａのサイズが小さくても、コンタ
クトホール２ａはタングステン膜４によって完全に埋め
ることができる。Referring to FIG. 4C, tungsten film 4 is deposited only on the inner surface of contact hole 2a by selective CVD. Since tungsten is selectively deposited only on silicon in CVD, tungsten film 4 can be deposited only on silicon substrate 1 and sidewall silicon film 3 exposed at the bottom of the contact hole. Therefore, even if the size of the contact hole 2a is small, the contact hole 2a can be completely filled with the tungsten film 4.
第４Ｄ図を参照して、コンタクトホール２ａがタングス
テン膜の電極４によって埋められた後に、シリコン酸化
膜２上にアルミニウム膜が堆積される。このアルミニウ
ム膜をパターニングすることによって、配線パターン５
が形成される。Referring to FIG. 4D, after contact hole 2a is filled with tungsten film electrode 4, an aluminum film is deposited on silicon oxide film 2. Referring to FIG. By patterning this aluminum film, the wiring pattern 5
is formed.
［発明が解決しようとする課題］
上述の先行技術による半導体装置においては、コンタク
トホール２ａ内のタングステン電極４とシリコン酸化膜
２上のアルミニウム配線パターン５が個別に形成される
ので、半導体装置の製造プロセスが複雑になる。また、
電極４と配線パターン５との界面に含まれた酸化物によ
って、電極４と配線パターン５との間の電気的接続が不
良になることがある。[Problems to be Solved by the Invention] In the semiconductor device according to the above-mentioned prior art, the tungsten electrode 4 in the contact hole 2a and the aluminum wiring pattern 5 on the silicon oxide film 2 are formed separately, so that manufacturing of the semiconductor device is difficult. The process becomes more complicated. Also,
The oxide contained in the interface between the electrode 4 and the wiring pattern 5 may cause poor electrical connection between the electrode 4 and the wiring pattern 5.
このような先行技術の課題に鑑み、本発明の目的は、簡
略化されたプロセスで製造し得る半導体装置を提供する
ことである。In view of the problems of the prior art, an object of the present invention is to provide a semiconductor device that can be manufactured using a simplified process.
本発明のもう１つの目的は、絶縁膜上の導体パターンが
コンタクトホール下の導電性領域へ電気的に確実に接続
された半導体装置を提供することである。Another object of the present invention is to provide a semiconductor device in which a conductive pattern on an insulating film is electrically reliably connected to a conductive region under a contact hole.
［課題を解決するための手段］
本発明による半導体装置は、半導体基板と、その半導体
基板上に形成された絶縁膜と、絶縁膜内に形成されたコ
ンタクトホールと、コンタクトホールの内表面および絶
縁膜の上表面上にＣＶＤによって形成されたポリシリコ
ン膜のパターンと、ポリシリコン膜パターンのみを覆う
ように選択的にＣＶＤによって堆積された金属膜のパタ
ーンとを含むことを特徴としている。[Means for Solving the Problems] A semiconductor device according to the present invention includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, a contact hole formed in the insulating film, an inner surface of the contact hole, and an insulating film formed on the semiconductor substrate. It is characterized by including a pattern of a polysilicon film formed by CVD on the upper surface of the film, and a pattern of a metal film selectively deposited by CVD so as to cover only the polysilicon film pattern.
［作用コ
本発明による半導体装置に関しては、絶縁膜の上表面上
とコンタクトホールの内表面上に形成されたポリシリコ
ン膜のパターン上にのみ選択的ＣＶＤによって金属膜パ
ターンが堆積されるので、前述の先行技術におけるよう
に付加的アルミニウム層を堆積させてそのアルミニウム
層をホトリソグラフィでパターニングする必要がない。[Function] Regarding the semiconductor device according to the present invention, since the metal film pattern is deposited by selective CVD only on the polysilicon film pattern formed on the upper surface of the insulating film and the inner surface of the contact hole, the above-mentioned There is no need to deposit an additional aluminum layer and pattern it photolithographically as in the prior art.
すなわち、本発明の半導体装置は、先行技術におけるよ
り少ないステラブ数で製造することができる。また、金
属膜パターンは、コンタクトホール内の部分から絶縁膜
上の部分まで連続しているので、先行技術におけるよう
にコンタクトホール内の電極と絶縁膜よの配線パターン
との間に含まれる酸化物によって電気的接続不良が生じ
る恐れがない。That is, the semiconductor device of the present invention can be manufactured with fewer stellabs than in the prior art. Furthermore, since the metal film pattern is continuous from the part inside the contact hole to the part on the insulating film, oxides contained between the electrode in the contact hole and the wiring pattern on the insulating film, as in the prior art, There is no risk of electrical connection failure.
［実施例］
本発明の一実施例による半導体装置の製造過程が、第１
Ａ図ないし第１Ｃ図の概略的な断面図と第２Ａ図ないし
第２Ｃ図の概略的な平面図とによって示されている。[Example] The manufacturing process of a semiconductor device according to an example of the present invention is as follows.
It is illustrated by schematic cross-sectional views in FIGS. A to 1C and schematic plan views in FIGS. 2A to 2C.
第１Ａ図を参照して、半導体基板１１上に絶縁膜１２が
ＣＶＤ法などによって形成される。絶縁膜１２には、コ
ンタクトホール１２ａが開けられる。Referring to FIG. 1A, an insulating film 12 is formed on a semiconductor substrate 11 by a CVD method or the like. A contact hole 12a is opened in the insulating film 12.
第１Ｂ図と第２Ａ図を参照して、絶縁膜１２の上表面と
コンタクトホール１２ａの内表面を覆うように、ポリシ
リコン膜１３がＣＶＤによって堆積される。ポリシリコ
ン膜１３上にはレジストパターン１４が形成される。ポ
リシリコン膜１３は、レジストパターン１４をマスクと
してエツチングによってパターニングされる。第１Ｂ図
は、ポリシリコン膜１３のパターニング後における第２
Ａ図中の線ＩＢ−ＩＨに沿った断面を示している。Referring to FIGS. 1B and 2A, polysilicon film 13 is deposited by CVD so as to cover the upper surface of insulating film 12 and the inner surface of contact hole 12a. A resist pattern 14 is formed on the polysilicon film 13. Polysilicon film 13 is patterned by etching using resist pattern 14 as a mask. FIG. 1B shows the second pattern after patterning the polysilicon film 13.
A cross section taken along line IB-IH in figure A is shown.
第２Ｂ図を参照して、レジストパターン１４が除去され
、ポリシリコン膜パターン１３が露出される。Referring to FIG. 2B, resist pattern 14 is removed and polysilicon film pattern 13 is exposed.
第１Ｃ図と第２Ｃ図を参照して、コンタクトホール１２
ａを埋めかつポリシリコン膜パターンのみを覆うように
金属膜パターン１５が選択的ＣＶＤによって形成される
。たとえば、タングステン。With reference to FIG. 1C and FIG. 2C, contact hole 12
A metal film pattern 15 is formed by selective CVD to fill the area a and cover only the polysilicon film pattern. For example, tungsten.
モリブデン、銅などは、ＣＶＤによってシリコン上にの
み選択的に堆積させることができる。すなわち、シリコ
ン上にのみ選択的ＣＶＤによって堆積させ得る金属膜の
パターン１５が、なんらのマスクやエツチングを用いる
ことなく、ポリシリコン膜パターン１３上にのみ形成さ
れ得るのである。Molybdenum, copper, etc. can be selectively deposited only on silicon by CVD. That is, the metal film pattern 15, which can be deposited only on silicon by selective CVD, can be formed only on the polysilicon film pattern 13 without using any mask or etching.
第３図を参照して、本発明を応用したＤＲＡＭの一部が
概略的な断面図で示されている。シリコン基板２１の主
面上には、フィールド酸化膜２２が形成されている。フ
ィールド酸化膜２２によって囲まれた半導体回路素子領
域内において、ＦＥＴ（電界効果トランジスタ）のソー
ス／ドレーンとなる不純物領域２１ａが基板２１の表面
層内に形成されている。基板２１の主面上には、さらに
、ゲート絶縁膜２３を介してポリシリコンのワード線２
４が形成されている。ワード線２４は、第１の層間絶縁
膜２５によって覆われている。キャパシタ下電極２６は
、対応するソース／ドレーン２１ａに接続されている。Referring to FIG. 3, a part of a DRAM to which the present invention is applied is shown in a schematic cross-sectional view. A field oxide film 22 is formed on the main surface of the silicon substrate 21 . In the semiconductor circuit element region surrounded by the field oxide film 22, an impurity region 21a which becomes the source/drain of a FET (field effect transistor) is formed in the surface layer of the substrate 21. A polysilicon word line 2 is further formed on the main surface of the substrate 21 via a gate insulating film 23.
4 is formed. Word line 24 is covered with first interlayer insulating film 25 . The capacitor lower electrode 26 is connected to the corresponding source/drain 21a.
キャパシタ下電極２６は、キャパシタ誘電体膜２７によ
って覆われている。The capacitor lower electrode 26 is covered with a capacitor dielectric film 27.
キャパシタ誘電体膜２７は、キャパシタ上電極２８によ
って覆われている。キャパシタ上電極２８は、第２層間
絶縁膜２９によって覆われている。Capacitor dielectric film 27 is covered with capacitor upper electrode 28 . The capacitor upper electrode 28 is covered with a second interlayer insulating film 29.
第２層間絶縁膜２９の上表面からソース／ドレーン２１
ａの１つまで貫通するコンタクトホール２９ａが開けら
れている。コンタクトホール２９ａの内表面上および第
２層間絶縁膜２９の上表面上には、ポリシリコン膜のパ
ターン３０がＣＶＤとホトリソグラフィを用いて形成さ
れており、そのポリシリコン膜パターン３０のみを覆う
ように金属膜パターン３１が選択的ＣＶＤによって形成
されている。これらのポリシリコン膜パターン３０と金
属膜パターン３１がＤＲＡＭのビット線として働く。Source/drain 21 from the upper surface of second interlayer insulating film 29
A contact hole 29a penetrating up to one point a is opened. A polysilicon film pattern 30 is formed on the inner surface of the contact hole 29a and on the upper surface of the second interlayer insulating film 29 using CVD and photolithography, and is made to cover only the polysilicon film pattern 30. A metal film pattern 31 is formed by selective CVD. These polysilicon film patterns 30 and metal film patterns 31 function as bit lines of the DRAM.
［発明の効果］
以上のように、本発明によれば、半導体装置において絶
縁膜の上表面上とコンタクトホールの内表面上に形成さ
れたポリシリコン膜のパターン上にのみ選択的ＣＶＤに
よって金属膜パターンが堆積されるので、先行技術にお
けるように付加的にアルミニウム層を堆積させてそのア
ルミニウム層をホトリソグラフィでパターニングする必
要がない。すなわち、本発明によれば、半導体装置は先
行技術におけるより少ないステップ数で製造することが
できる。また、金属膜パターンはコンタクトホール内の
部分から絶縁膜上の部分まで連続しているので、先行技
術におけるようにコンタクトホール内の電極と絶縁膜上
の配線パターンとの間に含まれる酸化物によって電気的
接続不良が生じる恐れがない。[Effects of the Invention] As described above, according to the present invention, a metal film is formed by selective CVD only on the pattern of a polysilicon film formed on the upper surface of an insulating film and on the inner surface of a contact hole in a semiconductor device. Since the pattern is deposited, there is no need to additionally deposit an aluminum layer and pattern it photolithographically as in the prior art. That is, according to the present invention, a semiconductor device can be manufactured with fewer steps than in the prior art. In addition, since the metal film pattern is continuous from the part inside the contact hole to the part on the insulating film, the oxide contained between the electrode in the contact hole and the wiring pattern on the insulating film, as in the prior art, There is no risk of electrical connection failure.
第１Ａ図ないし第１Ｃ図は、本発明の一実施例による半
導体装置の製造過程を示す概略的な断面図である。
第２Ａ図ないし第２Ｃ図は、第１Ａ図ないし第１Ｃ図に
示された実施例における製造過程を示す概略的な上面図
である。
第３図は、本発明を応用したＤＲＡＭの一例を示す概略
的な断面図である。
第４八図ないし第４Ｄ図は、先行技術による半導体装置
における導体パターンの形成過程を示す概略的な断面図
である。
図において、１１は半導体基板、１２は絶縁膜、１２ａ
はコンタクトホール、１３はポリシリコン膜パターン、
１４はレジストパターン、１５は金属膜パターン、２１
はシリコン基板、２９は層間絶縁膜、２９ａはコンタク
トホール、３０はポリシリコン膜パターン、そして３１
は金属膜パターンを示す。
なお、各図において、同一符号は同一内容または相当部
分を示す。
代 理 人 大台 増雄1A to 1C are schematic cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. 2A to 2C are schematic top views showing the manufacturing process of the embodiment shown in FIGS. 1A to 1C. FIG. 3 is a schematic cross-sectional view showing an example of a DRAM to which the present invention is applied. FIGS. 48 to 4D are schematic cross-sectional views showing the process of forming a conductor pattern in a semiconductor device according to the prior art. In the figure, 11 is a semiconductor substrate, 12 is an insulating film, and 12a
13 is a contact hole, 13 is a polysilicon film pattern,
14 is a resist pattern, 15 is a metal film pattern, 21
29 is a silicon substrate, 29 is an interlayer insulating film, 29a is a contact hole, 30 is a polysilicon film pattern, and 31
indicates a metal film pattern. In each figure, the same reference numerals indicate the same contents or corresponding parts. Agent Masuo Odai
Claims (1)
ンタクトホールの内表面および前記絶縁膜の上表面上に
ＣＶＤによって形成されたポリシリコン膜のパターンと
、 前記ポリシリコン膜パターンのみを覆うように選択的に
ＣＶＤによって堆積された金属膜のパターンと を含むことを特徴とする半導体装置。[Scope of Claims] A semiconductor substrate, an insulating film formed on the semiconductor substrate, a contact hole formed in the insulating film, and a CVD film formed on the inner surface of the contact hole and the upper surface of the insulating film. 1. A semiconductor device comprising: a pattern of a polysilicon film formed by the method; and a pattern of a metal film selectively deposited by CVD so as to cover only the polysilicon film pattern.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2301541A JPH04171921A (en) | 1990-11-06 | 1990-11-06 | Semiconductor device |
| DE4113741A DE4113741C2 (en) | 1990-11-06 | 1991-04-26 | Conductor structure of a semiconductor device and method for its production |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2301541A JPH04171921A (en) | 1990-11-06 | 1990-11-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04171921A true JPH04171921A (en) | 1992-06-19 |
Family
ID=17898179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2301541A Pending JPH04171921A (en) | 1990-11-06 | 1990-11-06 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH04171921A (en) |
| DE (1) | DE4113741C2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015519750A (en) * | 2012-05-07 | 2015-07-09 | マイクロン テクノロジー， インク． | Resistive memory with limited filament formation |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2885616B2 (en) * | 1992-07-31 | 1999-04-26 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62204523A (en) * | 1986-03-04 | 1987-09-09 | Nec Corp | Forming method for contact electrode |
| JPH0218950A (en) * | 1988-07-07 | 1990-01-23 | Toshiba Corp | Semiconductor device and its manufacture |
-
1990
- 1990-11-06 JP JP2301541A patent/JPH04171921A/en active Pending
-
1991
- 1991-04-26 DE DE4113741A patent/DE4113741C2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015519750A (en) * | 2012-05-07 | 2015-07-09 | マイクロン テクノロジー， インク． | Resistive memory with limited filament formation |
| US9406880B2 (en) | 2012-05-07 | 2016-08-02 | Micron Technology, Inc. | Resistive memory having confined filament formation |
| US9722178B2 (en) | 2012-05-07 | 2017-08-01 | Micron Technology, Inc. | Resistive memory having confined filament formation |
| US10153431B2 (en) | 2012-05-07 | 2018-12-11 | Micron Technology, Inc. | Resistive memory having confined filament formation |
Also Published As
| Publication number | Publication date |
|---|---|
| DE4113741C2 (en) | 1996-05-02 |
| DE4113741A1 (en) | 1992-05-07 |
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