JPH04170219A - Duty correction circuit - Google Patents

Abstract

PURPOSE:To select duty ratio of an output signal to an optional value by receiving a reference voltage whose voltage level is adjustable for using reference voltage inputted to an operational amplifier. CONSTITUTION:A frequency of an input signal 101 inputted from a terminal 51 is divided into two at a frequency divider 1 and the resulting signal 102 is fed to an EXOR circuit 3 and a delay line 2. The signal 102 whose phase is delayed by D is inputted to the EXOR circuit 3 as a delay signal 104. Its output signal 105 is outputted from a terminal 52 and inputted to an operational amplifier 4 via a loop filter 8. An integration signal 106 resulting from integrating the output signal 105 is outputted from the loop filter 8 and inputted to a noninverting input terminal of the operational amplifier 4. A control signal 103 corresponding to a voltage difference of the integration signal 106 with respect to a variable reference voltage 5 is generated by the operational amplifier 104 and fed to the delay line 2, in which the delay time is controlled.

Description

[Detailed description of the invention] [Industrial application field 1 The present invention relates to a duty correction circuit.

[Conventional technology]

An example of a conventional Tuesday correction circuit is shown in FIG. Third
As shown in the figure, the conventional duty correction circuit includes a frequency divider 9 that divides the frequency of an input signal by two, a delay line 10,
The circuit includes an I-,

In FIG. 13, input signal 1 input manually from terminal 53
．． 07 has its frequency divided by two in the frequency divider 9 and is sent as a 5 signal 108 to the EXOR [Ulii' 811 and the delay line 10. The signal +08 delayed by the time phase I] by the delay line 10 is used as the delayed signal O for EXOR times #! It is input to IJ. EX, OR circuit]
At I, the exclusive OR of the signal 108 and the delayed signal 110 is performed, and an output signal Ill is output. This output signal III is output from the terminal 54, and
On the one hand, it is input to the operational amplifier 12 via the loop filter 15 . The loop and filter 15 have an integration function, and the output signal 111 is integrated by the loop filter 15 and output as an integrated signal 112, which is input to the positive phase input terminal of the operational amplifier 12. Further, a voltage of 1/2 of the power supply voltage, that is, a voltage of 1/2 VDD is input to the negative phase input terminal of the operational amplifier 12 as a reference voltage 7. 2 A control signal 109 corresponding to the voltage difference of the integral signal 112 with Von as a reference is generated, and the delay line ■0
sent to. That is, the delay line 10, the EXOR circuit 11
, the loop filter 15 and the operational amplifier 12 form one automatic control system, and the duty ratio of the output signal Il+ is equal to the power supply voltage VD+) and the reference voltage 1/2 Voo.
The delay time I] in the delay line 10 is controlled and adjusted so that the voltage ratio between T and T is equal to 50%. : X Output signal output from OR circuit 11]
The duty ratio of 11 is supplemented to 50%.

The second rA(aL(ti, (c) and (d>) are shown respectively the input signal 107, the signal 108, the delayed signal 111'l' and the output signal I1. I1-
where 1) indicates the delay time in the delay line 10,
) and F indicate the high-level force time in the output signal 111, respectively. Therefore, when the duty ratio of the output signal is 50% lJ, E/F is 0.5.

[Problems to be solved by the invention] The above-mentioned conventional technique! --In the day correction circuit, the duty ratio of the output signal is necessarily fixed at 50% because the reference voltage input to the negative phase input terminal of the operational amplifier is fixed to I/2VLID. It's on the shore.
The disadvantage is that it is not possible to select the desired data ratio.

[Means to solve the problem]

The duty correction circuit of the present invention includes a frequency divider that divides the frequency of an input signal to be corrected for tearnity pressure by two, a delay line that delays and outputs the output signal of the frequency divider, and an output of the frequency divider. The signal and the output signal of the direct delay line are manually
．． an EX, OR circuit that outputs the exclusive logical phase signal of both signals as a signal with its duty ratio corrected; a loop filter that integrates the output signal of the EXOR circuit; and a loop filter that integrates the output signal of the EXOR circuit. an integral output signal;
an operational amplifier that inputs a predetermined reference voltage and outputs a control signal for the delay line; and an operational amplifier that generates a variable reference voltage whose level can be adjusted over a predetermined voltage range and functions as a power supply for the reference voltage. a variable reference voltage source that outputs;
It is composed of:

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a 71912 diagram of one embodiment of the present invention.9 As shown in FIG. , l Possible X OR circuit 3
, an operational amplifier 4 , and a loop filter 8 consisting of a resistor 6 and a capacitor 7 .

In FIG. 1, the frequency of a large signal 101 inputted from a terminal 51 is divided by 2 in the frequency divider 1, and then sent as a signal 102 to the I to X OR circuit 3 to the extension line 2. Sent. The signal 102 delayed by the time phase D by the delay line 2 is EXORed as a delayed signal 104.
It is input to M path 3. g] In the XOR circuit 3,
The exclusive OR of the signal 102 and the delayed signal 104 is taken, and an output signal 105 is output.7 This output signal 105 is output from the terminal 52, and also passes through the loop filter 8 to the operational amplifier 4. is man-powered. The loop filter 4 has an integration function, and the Louvu filter 4 outputs an integral signal 106 obtained by integrating the output signal 105 and inputs it to the positive phase input of the operational amplifier 4. In addition, a predetermined variable reference voltage is manually inputted from the variable voltage power supply 5 to the negative phase input terminal of the operational amplifier 4, and in the operational amplifier 4, the voltage of the integrated signal 106 with the direct variable base ipr, the voltage as a reference. A control signal 103 corresponding to the difference ~° is generated and sent to the delay line 2. That is, delay line 2, EXOR circuit 3, loop filter 8
and the operational amplifier 4 form one automatic control system, and the delay time A in the delay line 2 is controlled in accordance with the level of the variable reference voltage d supplied from the variable voltage power supply 5. , an arbitrary duty ratio is set in the output signal 105.

2(a), <b), (c) and (d) show the input signal 101, the signal 102, the delayed signal 104 and the output signal 105, respectively, where A is the input signal in the delay line 2. The delay time is shown, and B and C show the high level time and one cycle time in the output signal 105, respectively. Therefore, as described above, the duty ratio B/C of the output signal is arbitrarily set depending on the level setting of the variable reference voltage.

〔Effect of the invention〕

As explained above, the present invention includes a frequency divider, a delay line,
The output signal is applied to a duty ratio correction circuit including an F, This has the effect that the Tuday ratio of can be selected to an arbitrary value.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
>, <b), (c) and (d) are signal waveform diagrams in the above embodiment, Figure 3 is a block diagram of the conventional example, and Figures 4 (a), (b), (c) and (d). ) is a signal waveform diagram in the conventional example. In the figure, 1, 9... frequency divider, 2, 10...
...Delay line, 3, 11...E', X O
R circuit, 4, 12... operational amplifier, 5...- variable voltage source, 6, 13-... resistor, 7.14... capacitance, 8, 15... Loop filter.

Claims (1)

[Scope of Claims] A frequency divider that divides the frequency of an input signal to be subjected to duty ratio correction by two; a delay line that delays and outputs the output signal of the frequency divider; and an output signal of the frequency divider. , an EXOR circuit that inputs the output signal of the delay line and outputs an exclusive OR signal of both signals as an output signal with a corrected duty ratio; and a loop filter that integrates the output signal of the EXOR circuit. , an operational amplifier that inputs the integral output signal of the loop filter and a predetermined reference voltage and outputs a control signal for the delay line; A duty correction circuit comprising: a variable reference voltage source that generates and outputs an adjustable variable reference voltage;