JPH04166984A - Control device for panel display - Google Patents

Abstract

PURPOSE:To obtain two-screen division type panel display which is rich in compatibility without increasing the cost of parts by performing forcible synchronization with panel timing, and providing a 1/2 frame buffer. CONSTITUTION:A CRT controller 12 operates in accordance with a fundamental clock for panels and also repeats weight action in accordance with weight signals output from a panel timing controller 13 whereby forcible synchronization with panel timing is carried out. A 1/2 frame buffer 17 is provided and display data fed from the controller 12 and display data read from the buffer 17 are alternately selected so as to supply data in the order that agrees with two-screen division type panel display; i.e. the control of the two-screen division type panel display can be made following an application program without changing the order of display data output from the controller 12 nor preset timing data.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a display control device that controls the display of a panel display having a display timing different from that of a CRT display using an application program created for a CRT display. In particular, the present invention relates to a panel display control device that controls a single drive type panel display divided into two screens.

[Prior Art] In recent years, with the miniaturization of various OA devices such as personal computers and word processors, the displays used in these devices have changed from conventional CRT displays to panel types such as liquid crystal displays and plasma displays. have come into widespread use.

In addition, as the above-mentioned panel type display becomes larger, in order to reduce the electrode capacity, the panel 21 is divided into, for example, two screens, upper and lower, as shown in FIG. 5, and each screen is connected to the shift register 22°. A two-sided, single-drive type CD panel display with a 23-speed drive has also been developed. In this display, as shown in the display timing diagram in Figure 6,
240 lines of panel display data PDA and 241 to 480 lines of panel display data PDA constituting the lower divided screen are alternately supplied line by line.

On the other hand, panel type displays and CRT displays usually have different display timings.

Therefore, in order to drive the above-mentioned conventional two-sided single drive type panel display with an application program created for CRT displays, the following method has conventionally been adopted.

That is, according to the initial setting program, the contents of the timing control register of the existing CRT controller are set to the same timing as the panel timing.

Then, the display memory (VRAM) managed by the CRT controller 1-roller is accessed alternately between the upper and lower screens. Therefore, the memory address generation circuit for that purpose is divided into upper and lower parts.
I'm trying to provide enough space for the screen.

[Problems to be Solved by the Invention] However, as described above, when the contents of the control register are set to match the timing of the panel display, when the display mode is changed by the application program, the CRT controller Because the contents of the timing control register are rewritten,
There is a problem in that the set timing for the panel is lost and the display operation is hindered. Therefore, in this case, a calculation means such as a local CPU is required to convert the contents of the register set for the CRT into timing data for the panel, which poses a problem of increasing component costs.

Furthermore, in the above method, since memory addresses for the upper and lower two screens are generated alternately, there is a problem in that a special address generation circuit including two counters with different preset values is required.

This invention was made to solve these problems, and without causing a significant increase in parts costs,
It is an object of the present invention to provide a panel display control device with excellent compatibility that can control the display of a two-screen panel display without any trouble using timing data set for a CRT display.

[Means for Solving the Problems] A panel display control device of the present invention includes a clock generation unit that generates a basic clock that is the basis of the display timing of a two-screen split panel display whose display is to be controlled; A CRT controller that operates and outputs display timing signals and display data for the panel display based on internally stored timing setting values and externally applied wait signals; A panel data conversion circuit that converts into display data for the panel, and a 1/2 frame that stores 1/2 frame of display data for the panel output from this panel data conversion circuit.
a panel timing controller that operates according to the basic clock and outputs the wait signal for synchronization, a panel up/down switching signal synchronized with the wait signal, and a display control signal for the panel display; A data control circuit that alternately selects display data output from the panel data conversion circuit and display data output from the 1/2 frame buffer according to a switching signal and outputs the selected display data to the panel display. shall be.

[Operation] According to the present invention, the CRT controller operates according to the basic clock for the panel, and the wait operation is repeated according to the wait signal output from the panel timing controller, thereby forcibly synchronizing the panel timing. be exposed. Further, according to the present invention, a 2-screen split type is provided with a 1/2 frame buffer and alternately selects display data supplied from the CRT controller and display data read from the 1/2 frame buffer. Data can be supplied in an order that matches the panel display.

Therefore, according to the present invention, without any manipulation of the order of display data output from the CRT controller,
Display control of a two-screen split panel display can be performed according to an application program intended for a CRT display without changing timing data set inside the CRT controller.

Therefore, it is possible to provide a panel display control device with excellent compatibility.

[Embodiment] An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a display controller 1 according to this embodiment and a display memory (hereinafter referred to as VRAM) connected to it.
2 and a flat panel display 3.

The display controller 1 is constructed as follows.

That is, the CRT clock signal CCK that defines the display timing of the CRT display and the panel clock signal PCK that defines the display timing of the panel display are selected by the clock select circuit 11 and sent as the clock signal CLK to the CRT controller 12 and panel timing controller 13. is supplied to. These controllers 12 and 13 use a CRT clock signal C when controlling the display of a CRT display (not shown).
CK, and when controlling the display of the Furano 1-panel display 3, it operates using the panel clock signal PCK.

The CRT controller 12 is internally equipped with a timing control register (not shown) and an external synchronization circuit 14. It outputs various timing signals such as a synchronization signal, supplies a display timing signal DTMG to the panel timing controller 13, and weights the display timing signal DTMG based on the weight signal output from the panel timing controller 13. match the timing of the event. Also, CRT:
The +on I-roller 12 receives display data VD from the VRAM2.
A is sequentially read out and supplied to the panel data conversion circuit 15 as CRT display data CDA.

On the other hand, the panel timing controller 13 generates a wait signal WT based on the timing signal DTMG from the CRT controller 12 and the clock signal CLK from the clock select circuit II.

Generates a panel top/bottom switching signal SW1, a panel control signal LC, and a shift I/clock signal SCK, and sends these signals to the external synchronization circuit 14, frame buffer interface 16, and flat panel display 3, respectively.
and is supplied to the panel data conversion circuit 15.

The panel data conversion circuit 15 includes the CRT controller 12
For CRT display data ODA supplied from
For example, processing such as adding gradation is performed and the data is converted into display data PDA I for the panel.

The frame buffer interface 16 connects the 1/2 frame buffer 1 based on the panel upper/lower screen switching signal SW.
Read/Lie 1 giving 7 read/write timing
- Supply signal R/W to I/2 frame buffer 17. Then, the display data PDAI for the panel output from the panel data conversion circuit 15 is written to the 1/2 frame buffer 17 in accordance with this read/write signal R/W, and is /2 frame buffer 17 is read out as display data PDA2.

The data control circuit 18 alternately selects the display data PDAI output from the panel data conversion circuit 15 and the display data PDA2 read from the 1/2 frame buffer 17 for each line, and outputs the display data PDA to the flat panel display 3. supply.

Next, the operation of the display controller configured as described above will be explained.

First, when controlling the display of a CRT display (not shown), the clock select circuit 11
Select the clock signal CCK for. As a result, CR
As shown in FIG. 2, the T controller 12 controls the C control based on timing data such as horizontal synchronization time, horizontal synchronization start/end timing, and blanking period start/end timing set in an internal timing control register.
It outputs a horizontal synchronizing signal H3YNC and a vertical synchronizing signal VSYNC that provide the display timing of the RT display.

In addition, the display data VDA read out from the VRAM 12
is output as display data CDA from the CRT controller 12 in accordance with the various timing signals mentioned above. Note that in the figure, the numbers written in the display data CDA indicate line numbers, and in this example, one frame of screen is composed of 480 lines.

On the other hand, when controlling the display of the flat panel display 7, the clock select circuit 11 selects the panel clock signal PCK, so that not only the panel timing controller 13 but also the CRT controller 12 also selects the panel clock signal PCK. It operates according to The display timing at this time is shown in FIG. In this figure, the numbers attached to the timing diagrams of the panel data PDAI and PDA2°PDA indicate the line numbers of the flat panel display 3. In the flat panel display 3, lines 1 to 240 constitute a main screen, and lines 241 to 480 constitute a sub screen.

As shown in FIG. 3, first, the display timing signal DTM
When G becomes active, the display data CD of the first line that constitutes the main screen of the panel is sent from the CRT controller 12.
A is output. This display data CDA is converted into panel display data PDA by the panel data conversion circuit 15.
It is converted to I.

At this time, since the panel upper and lower screen switching signal SW is at the "l" level, the data control circuit 18 selects the display data PDAI and outputs it to the flat panel display 3.

When the display data of the first line is supplied to the flat panel display 3, the display timing signal DTMG becomes inactive, and in response to this, the panel timing controller 13 outputs the wait signal WT to the CRT controller 12. As a result, the CRT controller 12 stops operating and maintains the state before the wait signal WT was generated.

During this wait operation, the panel timing controller 13 switches the read/write signal to the 1/2 frame buffer 17 and reads the data on the 241st line of the child screen stored in the 1/2 frame buffer 17. . At this time, the panel upper and lower screen switching signal SW is "0"
level, so the data control circuit 18
selects the display data PDA2 read from the frame buffer 17 and outputs it to the flat panel display 3.

When the 241st line display data is supplied to the flat panel display 3, the output of the wait signal WT from the panel timing controller 13 is stopped, and in response to this, the CRT controller 13 activates the display timing signal DTMG. At the same time as restarting the operation, the display operation for the next second line is forcibly started.

Thereafter, by repeating the same procedure, the CRT controller 12 and 1/2 is attached to the flat panel display 3.
The display data PDA is alternately supplied from the frame buffer 17.

Here, by setting the pulse interval of the wait signal WT to an appropriate value, the CRT controller 12 can be synchronized with the panel timing.

FIG. 4 is a schematic diagram, not showing the flow of display data PDA supplied from the CRT controller 1 to roller 12 and 1/2 frame buffer 17 to the flat panel display.

First, when the CRT controller 12 is scanning one screen of the panel, as shown in FIG.
The T controller 12 sends data to the first line row of the flat panel display 3 according to the scan, and at the same time stores the data of the first line in the frame buffer 17. After scanning all the data of 1 line 1, the 241 data already stored in the frame buffer 17 is scanned.
The data on the first line is sent to the lower surface of the flat panel display 3. Similarly, CRT controller 1
2 scans up to the 240th line of data, the display operation for one frame is completed. At this point, 1 to 240 lines of data will be stored in the 1/2 frame buffer 17.

Note that, for example, when writing the first line data to the area where the 241st line data is stored,
Prior to the write operation, data for the 241st line may be stored in the line buffer. This can prevent the display data PDA2 to be read from disappearing due to the write operation of the display data RDA1.

On the other hand, when the CRT controller 12 is scanning the lower surface of the panel, first, as shown in FIG. 4(b),
1 already stored in 1/2 frame buffer 17
The data for line 1 is sent to the flat panel display 3, and the display operation for line 2 is performed. Subsequently, the data of the 241st line is supplied from the CRT controller I2 after the wait is canceled to the flat panel display 3, and at the same time, the data of the 241st line is stored in the frame buffer 17. Next, the data on the second line is read out from the frame buffer 17 and supplied to the panel display 3. When the above operation is repeated and the data of the 480th line is stored in the frame buffer 17, the data of the 241st to 480th lines will be stored in the frame buffer 17.

As described above, according to the display controller according to this embodiment, synchronization with the panel timing is achieved by forcibly applying a weight to the CRT controller 12 from the outside, which is different from that of the conventional CRT controller. Sufficient compatibility with application programs can also be ensured.

In addition, display data is sequentially stored in the /2 frame buffer 17, and display data PDAI output from the panel data conversion circuit 15 and display data PDAI output from the CRT controller 12 are alternately selected. This makes it possible to control the display of the two-screen single drive type flat panel display 3 without any trouble.

[Effects of the Invention] As described above, according to the present invention, the CRT controller is forcibly weighted by the panel timing controller, so that synchronization with the panel timing is performed. Full compatibility can be ensured without the need to change anything.

Further, according to the present invention, a 1/2 frame buffer is provided, and display data supplied from a CRT controller;
Since the display data read from the 1/2 frame buffer is selected alternately, data can be supplied in an order that matches the two-screen split panel display.

According to the present invention, the required buffer capacity is 1
/2 frames, so there is no need for a significant increase in the amount of hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a display controller according to an embodiment of the present invention, and FIG. 2 is a block diagram of a display controller according to an embodiment of the present invention.
Fig. 3 is a timing diagram showing the panel display timing by the same controller; Fig. 4 is a schematic diagram showing the flow of display data supplied to the panel display; Fig. 5 is a two-screen single drive FIG. 6 is a block diagram of a panel display of the same type, and a timing chart showing display timing of the same panel display. 1...Display controller, 2...VRAM,
3...Flat panel display, 11...Clock select circuit, 12...CRT controller, 3
...Panel timing controller, 14...External synchronization circuit, 15...Panel data conversion circuit, 1
6... Frame buffer interface, 17...
l/2 frame buffer, 18...data control circuit.

Claims (1)

[Claims] (1) A clock generating means that generates a basic clock that is the basis of the display timing of a two-screen split panel display whose display is to be controlled; a CRT controller that outputs a display timing signal and display data for the panel display based on a weight signal transmitted from the CRT controller; a panel data conversion circuit that converts the display data output from the CRT controller into display data for the panel; a 1/2 frame buffer that stores 1/2 frame of display data for the panel output from the panel data conversion circuit; and a panel that operates according to the basic clock and is synchronized with the wait signal for synchronization and this wait signal. a panel timing controller that outputs an up/down switching signal and a display control signal for the panel display; and display data output from the panel data conversion circuit and display data output from the 1/2 frame buffer according to the panel up/down switching signal. and a data control circuit that alternately selects and outputs the data to the panel display.