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JPH04163958A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04163958A
JPH04163958A JP2290392A JP29039290A JPH04163958A JP H04163958 A JPH04163958 A JP H04163958A JP 2290392 A JP2290392 A JP 2290392A JP 29039290 A JP29039290 A JP 29039290A JP H04163958 A JPH04163958 A JP H04163958A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor chip
power supply
semiconductor device
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2290392A
Other languages
Japanese (ja)
Inventor
Yoshiteru Ono
芳照 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2290392A priority Critical patent/JPH04163958A/en
Publication of JPH04163958A publication Critical patent/JPH04163958A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、半導体装置に係わり、特に半導体チップと外
部パッケージ間の接続にリードフレームやワイヤーボン
ディング等を使用するパッケージなどに於て、単一もし
くわ複数の電源系の複数の半導体チップを1個のパッケ
ージに納めた半導体装置に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor devices, and particularly to packages that use lead frames, wire bonding, etc. for connection between a semiconductor chip and an external package. More specifically, the present invention relates to a semiconductor device in which a plurality of semiconductor chips for a plurality of power supply systems are housed in one package.

[発明の概要] [従来の技術] 半導体装置の製造技術が益々進歩するにつれて使われる
トランジスタのチャンネル長も微細化が進み、現在ロジ
ック系半導体装置に標準的に使われている5v系の11
1源ではトランジスタの耐圧が足りなくなるものも出て
きている。また、液晶ドライバー用高耐圧半導体装置の
様にIOVから数十■の電源を必要とするもの、また、
時計に使われているような1.5v程度の電源で動作す
るものまで様々である。また、パーソナルコンピュータ
ーなどのシステムの携帯化等が進む中で、低消費電力化
の要求が強まり、ある半導体装置は5v系、別のある半
導体装置は3v系というような複数の電源系の混在が進
んで行く。それと並行して、システム自身の信頼性やコ
ストの面からは部品点数の減少や小型化が益々要求され
ている。
[Summary of the Invention] [Prior Art] As the manufacturing technology of semiconductor devices progresses, the channel length of the transistors used also progresses to miniaturization.
Some transistors are starting to have insufficient breakdown voltage with a single source. In addition, devices that require a power supply of several tens of microseconds from the IOV, such as high-voltage semiconductor devices for liquid crystal drivers,
There are various types, including those that operate on a power supply of about 1.5V, such as those used in watches. Additionally, as personal computers and other systems become more portable, demands for lower power consumption have become stronger, leading to a coexistence of multiple power supply systems, such as one semiconductor device using a 5V system and another semiconductor device using a 3V system. Go ahead. At the same time, in terms of the reliability and cost of the system itself, there is an increasing demand for a reduction in the number of parts and miniaturization.

この様な状況の中で、1つのシステムを設計しようとす
る場合には、各々の機能の半導体装置を入手し、その各
々をシステムボード上に実装配置して機能を満足させて
いた。また部品点数の削減やその効果による小型化、ま
たそれに伴うコストの低減、信頼性の向上の面から同じ
電源系の複数の機能の半導体装置をまとめて1つの半導
体装置にすることも進められている。′ その際に使用される半導体装置は従来の例として第2図
に示すような1個のパッケージに1個の半導体チップが
組み立てられたものである。
Under these circumstances, when designing a single system, semiconductor devices for each function were obtained and each was mounted and arranged on a system board to satisfy the functions. In addition, in order to reduce the number of parts and reduce the size due to this effect, as well as to reduce costs and improve reliability, efforts are being made to combine semiconductor devices with multiple functions of the same power supply system into a single semiconductor device. There is. ' The semiconductor device used in this case is a conventional example in which one semiconductor chip is assembled in one package as shown in FIG.

[発明が解決しようとする課題] 今後益々、部品点数の削減やその効果による小型化、ま
たそれに伴うコストの低減、信頼性の向上の面からも半
導体装置の統合が進むことが考えられる。しかし、現在
の半導体チップの製造手法では、例えば現存している、
3v系、5v系、20v系の3個の半導体チップの機能
をを1個の半導体チップで実現することは非常に困難で
あり、そのことによる部品点数の削減やコストダウンの
効果を得ることは、これまで考えられていなかっまた、
単一電源系の複数の半導体チップにより実現されていた
機能を1つの半導体チップで実現するために全ての回路
構成、レイアウトから設計し直すことは半導体装置の動
作速度が指数関数的に大きくなりタイミング設計等が益
々困難になっている中、また製品サイクルが短くなって
きている昨今、大きなリスクを含むという問題点を有し
ていた。
[Problems to be Solved by the Invention] In the future, it is thought that semiconductor devices will be increasingly integrated in order to reduce the number of parts and achieve miniaturization, as well as to reduce costs and improve reliability. However, with current semiconductor chip manufacturing methods, for example,
It is extremely difficult to realize the functions of three semiconductor chips, 3V system, 5V system, and 20V system, with a single semiconductor chip, and it is difficult to achieve the effect of reducing the number of parts and cost by doing so. , which has not been thought of until now,
In order to realize the functions that were previously achieved by multiple semiconductor chips in a single power supply system with a single semiconductor chip, redesigning the entire circuit configuration and layout requires an exponential increase in the operating speed of semiconductor devices and timing problems. In recent years, as design has become increasingly difficult and product cycles have become shorter, this poses a problem in that it involves a large amount of risk.

本発明は、その様な状況の中で、単一もしくは複数の電
源系の複数の半導体チップの統合を容易に進める手法を
提供することを目的とする。
It is an object of the present invention to provide a method for easily integrating a plurality of semiconductor chips of a single power supply system or a plurality of power supply systems under such circumstances.

[課題を解決するための手段] 上記問題点を解決するために、本発明の半導体装置は、
1つのパッケージ内に単一もしくは複数の電源系の複数
の半導体チップを配置し、各々の半導体チップをワイヤ
ーボンディング等によりパッケージの入出力ビンと接続
することを特徴とする。
[Means for Solving the Problems] In order to solve the above problems, the semiconductor device of the present invention has the following features:
It is characterized in that a plurality of semiconductor chips of a single power supply system or a plurality of power supply systems are arranged in one package, and each semiconductor chip is connected to an input/output bin of the package by wire bonding or the like.

C実施例コ 以下に本発明の実施例を、図面に基づいて説明する。例
としてそれまでそれぞれ電源電圧が3 V。
C Embodiment Embodiments of the present invention will be described below based on the drawings. For example, until then, the power supply voltage was 3 V.

5v、20Vの3個の別々の半導体装置として組み立て
られていたものを1個の半導体装置として組み立てる場
合を想定する。
Assume that three separate 5V and 20V semiconductor devices are assembled into one semiconductor device.

第1図は本発明による前記想定によるところの半導体装
置のリードフレームの平面図である。第2図は従来の、
1個の半導体チップを1個のパッケージに組み立てた半
導体装置のリードフレームの平面図である。101は3
V系の半導体チップ、102は5V系の半導体チップ、
1o3は2oV系の半導体チップ、104は半導体チッ
プの入出力パッド、105はパッケージのインナーリー
ドビン、106はタブ吊りリード、1’07は半導体チ
ップとインナーリードビンを接続するためのボンディン
グワイヤー、108は絶縁シート、1゜9はダイパッド
である。まず、rノードフレームのダイパッド109に
絶縁シート108を装着し、その上に3V系の半導体チ
ップ101.5v系の半導体チップ102.20Viの
半導体チップ103を各々固定する。この後工程は通常
の半導体装置の組立と同様でよい。この様な簡単な手法
により複数の電源系の複数の半導体チップの統合を容易
に進めることが可能である。
FIG. 1 is a plan view of a lead frame of a semiconductor device according to the above assumption according to the present invention. Figure 2 shows the conventional
FIG. 2 is a plan view of a lead frame of a semiconductor device in which one semiconductor chip is assembled into one package. 101 is 3
V series semiconductor chip, 102 is a 5V series semiconductor chip,
1o3 is a 2oV semiconductor chip, 104 is an input/output pad of the semiconductor chip, 105 is an inner lead bin of the package, 106 is a tab hanging lead, 1'07 is a bonding wire for connecting the semiconductor chip and the inner lead bin, 108 is an insulating sheet, and 1°9 is a die pad. First, the insulating sheet 108 is attached to the die pad 109 of the r-node frame, and the semiconductor chips 103 of the 3V-based semiconductor chip 101, the 5v-based semiconductor chip 102, and the 20Vi-based semiconductor chip 103 are respectively fixed thereon. This post-process may be similar to the assembly of a normal semiconductor device. With such a simple method, it is possible to easily integrate a plurality of semiconductor chips of a plurality of power supply systems.

この例の想定は3v、5■、20Vの3個の電源電圧の
半導体であったが、それ以外の電源電圧系であっても同
様の効果が期待出来る。また、統合する半導体チップが
単一の電源系であれば、絶縁シートは必要無いし、複数
の電源系であったとしても基準電位が同じであれば同様
に必要無い。
Although this example assumes semiconductors with three power supply voltages of 3V, 5V, and 20V, similar effects can be expected with other power supply voltage systems. Further, if the semiconductor chips to be integrated have a single power supply system, an insulating sheet is not necessary, and even if there are multiple power supply systems, as long as the reference potential is the same, there is no need for an insulating sheet.

例に示した図に於て、リードフレームの概略図は日本電
子機会工業界規格のQFPを模して表現しであるが、他
のどの様なパッケージにも同様の手法を用いて、同様の
効果を期待することが出来る。
In the diagram shown in the example, the schematic diagram of the lead frame is modeled after the QFP of the Japan Electronic Machinery Industry Standards, but any other package can be constructed using the same method. You can expect good results.

[発明の効果コ 本発明の半導体装置は、以上説明したように複数の半導
体チップを絶縁シートを装着したダイパッド上に配置し
た後ワイヤーボンディングを行い1つのパッケージに組
み立てるという手法によって複数の半導体チップの統合
を容易に進めることが出来、システムの小型化、低コス
ト化、信頼性の向上に効果がある。
[Effects of the Invention] As explained above, the semiconductor device of the present invention is capable of assembling a plurality of semiconductor chips into one package by arranging the plurality of semiconductor chips on a die pad equipped with an insulating sheet and then performing wire bonding. It can be easily integrated, and is effective in reducing system size, lowering costs, and improving reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による前記想定によるところの半導体装
置のリードフレームの平面図。 第2図は従来の1個の半導体チップを、1個のパッケー
ジに組み立てた半導体装置の平面図。 101・・・3v系の半導体チップ 102・・・5v系の半導体チップ 103・・・2OV系の半導体チップ 104・・・半導体チップの入出力パッド105・・・
パッケージのインナーリードビン106・・・タブ吊り
リード 107・・・ボンディングワイヤー 108・ ・・絶縁シート 109・・・ダイパッド 201・・・半導体チップ 202・・・半導体チップの入出力パッド203・・・
パッケージのインナーリードピン204・・・タブ吊り
リード 205・・・ボンディングワイヤー 206・・・ダイパッド 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 鈴木喜三部(他1名)第 17
FIG. 1 is a plan view of a lead frame of a semiconductor device according to the above assumption according to the present invention. FIG. 2 is a plan view of a conventional semiconductor device in which one semiconductor chip is assembled into one package. 101... 3V type semiconductor chip 102... 5V type semiconductor chip 103... 2OV type semiconductor chip 104... Input/output pad 105 of the semiconductor chip...
Package inner lead bin 106...Tab suspension lead 107...Bonding wire 108...Insulating sheet 109...Die pad 201...Semiconductor chip 202...Semiconductor chip input/output pad 203...
Package inner lead pin 204...Tab suspension lead 205...Bonding wire 206...Die pad and above Applicant Seiko Epson Corporation Agent Patent attorney Kizobe Suzuki (1 other person) No. 17

Claims (1)

【特許請求の範囲】[Claims]  単一もしくは複数の電源系の複数の半導体チップを、
1個のパッケージに納めることを特徴とする半導体装置
Multiple semiconductor chips for single or multiple power supply systems,
A semiconductor device characterized by being housed in one package.
JP2290392A 1990-10-26 1990-10-26 Semiconductor device Pending JPH04163958A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2290392A JPH04163958A (en) 1990-10-26 1990-10-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2290392A JPH04163958A (en) 1990-10-26 1990-10-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04163958A true JPH04163958A (en) 1992-06-09

Family

ID=17755420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2290392A Pending JPH04163958A (en) 1990-10-26 1990-10-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04163958A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5451814A (en) * 1992-02-28 1995-09-19 Mega Chips Corporation Multi-chip module integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5451814A (en) * 1992-02-28 1995-09-19 Mega Chips Corporation Multi-chip module integrated circuit

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