JPH04162633A - Thin film transistor - Google Patents

Abstract

PURPOSE:To reduce the variations of transistor characteristics with the elapse of time, and ensure the high withstand voltage, high integration, and high yield of the transistor by connecting a lead terminal from a field plate electrode to a lead terminal from a gate electrode. CONSTITUTION:A field plate terminal 19b led from a field plate electrode is constructed such that a constant hole 23 is formed through an interlayer insulating film 18 and the field plate terminal 19b is connected to a gate terminal 12a led from a gate electrode 12. Etching is performed through a fourth photolithography process to form a pattern of the interlayer insulating film 18. A contact hole 23 is formed through a source electrode 21 and a drain electrode 22, to which electrodes wiring metal layers 20a, 20b are formed. Further, a contact hoke 23 is formed through the gate terminal 12a to which the field plate terminal 19b is connected. After separation of a resist aluminum Al is deposited on the upper part of the separated part. Al is etched through a fifth photolithography process to form the field plate electrode 19 and a wiring metal film 20.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a thin film transistor used for driving an electrostatic block head, etc., and particularly has a high breakdown voltage and is capable of achieving high integration. Regarding thin film transistors.

(Prior Art) The structure of a high-voltage thin film transistor (TPT) used as a conventional electrostatic plotter head is shown in the plan view of FIG. 4 and the cross-sectional view taken along line BB' in FIG. The device had the structure shown in FIG.

As shown in FIGS. 4 and 5, this high-voltage thin film transistor includes a gate electrode 12 formed of chromium (Cr) or the like on an insulating substrate 11 made of glass or the like, and a gate electrode 12 that is covered with chromium (Cr) or the like. A gate insulating film 13 made of silicon nitride (SiNx) and an intrinsic amorphous silicon (ia-a-
5i), a channel protective film 15 formed of SiNx for protecting the semiconductor layer 14 provided on the upper part of the gate electrode 12, and an n+ layer provided on the semiconductor layer 14 for ohmic contact. The ohmic contact layer 16 is made of amorphous silicon (n"a-5i), and the metal layer 20 for wiring of aluminum (AI) provided on the ohmic contact layer 16 is made of chromium (Al) that prevents it from diffusing into the ohmic contact layer 16.
an ohmic contact layer 1 formed with a diffusion prevention layer 17 made of Cr) and divided by a channel protective film 15;
6a and 16b1, diffusion prevention layers 17a and 17b, and wiring metal layers 20a and 20b constituted a source electrode 21 and a drain electrode 22, respectively, forming an inverted staggered transistor.

By providing an offset region L2 between the gate electrode 12 and the drain electrode 22 as shown in FIG. 5, the thin film transistor element can be made to have a high breakdown voltage.

Note that the channel region L1 extends from the end of the channel protection film 15 on the source electrode 21 side to the end of the gate electrode 12 on the drain electrode 22 side, and from the end of the channel protection film 15 on the drain electrode 22 side to the end of the gate electrode 12 on the drain electrode 22 side. The offset region L2 extends up to the end on the drain electrode 22 side.

Further, the end portion of the gate electrode 12 on the drain electrode 22 side, that is, the portion on the drain electrode 22 side in the channel region L1, and the source electrode 21 in the offset region L2.
A field plate electrode 19 is formed of aluminum (Al) or the like through an interlayer insulating film 18 made of an organic film such as polyimide so as to cover the side portion.

By applying a voltage of about 100 V to the field plate electrode 19, the inflow path of electrons from the channel region L1 to the offset region L2 can be stably controlled, so that changes over time in the thin film transistor element are reduced. It was possible to obtain stable and good characteristics of the thin film transistor element.

When the above-mentioned high voltage thin film transistor element is used, for example, as an electrostatic plotter head, as shown in the inverter circuit diagram in FIG.
An inverter is constructed by using these, and these are integrated to form an array.

(Problems to be Solved by the Invention) However, in the configuration of the conventional thin film transistor described above, the field plate electrode 19 is connected to the source electrode 21,
A field plate terminal 19a serves as a fourth electrode for the drain electrode 22 and gate electrode 12, and is drawn out from the field plate electrode 19 as shown in FIG.
Since voltage is applied through wiring, the number of terminals increases, which hinders high integration when creating devices that integrate high-voltage thin film transistors, and may result in defective products. There is a problem in that a large amount of is produced, which causes a decrease in yield.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a thin film transistor that has a high breakdown voltage, has small changes in transistor characteristics over time, and can achieve high integration and high yield.

(Means for Solving the Problems) The invention according to claim 1 for solving the problems of the conventional example includes a gate electrode, a gate insulating film, a semiconductor layer, a channel protective film, a source layer, and a gate electrode on a substrate. A thin film transistor comprising an electrode and a drain electrode, an offset region is provided between the gate electrode and the drain electrode, and a field plate electrode is provided on the upper part through an interlayer insulating film so as to cover an end of the gate electrode on the drain electrode side. A terminal drawn out from the field plate electrode is connected to a terminal drawn out from the gate electrode.

A second aspect of the invention for solving the problems of the prior art is characterized in that, in the thin film transistor according to the first aspect, the interlayer insulating film is an inorganic film.

(Function) According to the invention according to claim 1, it has an offset area,
In a high voltage thin film transistor provided with a field plate electrode, the terminal drawn out from the field plate electrode is connected to the terminal drawn out from the gate electrode, so the terminal drawn out from the field plate terminal pole is connected separately. There is no need to connect to the wiring, etc., and it is possible to achieve high integration of devices.

According to the invention according to claim 2, it has an offset area,
In a high voltage thin film transistor in which a field plate electrode is provided on a channel protective film via an interlayer insulating film, a terminal drawn out from the field plate electrode is
Since the thin film transistor is connected to the terminal drawn out from the gate electrode and the interlayer insulating film is an inorganic film, the inorganic interlayer insulating film has excellent dielectric properties and voltage resistance.
Even if the field plate electrode has the same potential as the gate electrode, the inflow path of electrons inside the semiconductor layer can be stably controlled.

(Example) An example of the present invention will be described with reference to the drawings.

FIG. 1 is an explanatory plan view of a thin film transistor according to an embodiment of the present invention, and FIG. 2 is an explanatory cross-sectional view taken along the line AA' in FIG. Portions having the same configuration as in FIGS. 4 and 5 will be described with the same reference numerals.

As shown in FIGS. 1 and 2, the thin film transistor of this embodiment includes a gate electrode 12 formed of chromium (Cr), tantalum (Ta), etc. on a substrate 11 of glass or the like; Covering silicon nitride film (S i N
x) and an intrinsic amorphous silicon (i) deposited on the gate insulating film 13.
-a-3t) and 5iN for protecting the semiconductor layer 14 provided above the gate electrode 12.
a channel protective film 15 of
, a chromium (Cr) diffusion prevention layer 17 provided on the ohmic contact layer 16 for diffusion prevention, an aluminum (AI) wiring metal layer 20 provided on the diffusion prevention layer 17, and a channel. An interlayer insulating film 18' made of an inorganic film such as silicon oxide (S i Ox ) coated on the protective film 15, and an aluminum insulating film 18' provided on the interlayer insulating film 18' so as to span both the channel region and the offset region. (AI) field plate electrode 19.

Then, ohmic contact layers 16a and 16b and a diffusion prevention layer 17a formed separately by the channel protection film 15 are formed.
and 17b1 wiring metal layers 20a and 20b constitute a source electrode 21 and a drain electrode 22, respectively.

In addition, an offset region L2 is provided between the gate electrode 12 and the drain electrode 22 so that the thin film transistor of this embodiment also has a high breakdown voltage, and a channel protective film 1 on the source side is provided.
The channel region L1 extends from the end of the gate electrode 5 to the end of the gate electrode 12 on the drain side.

As shown in FIG. 1, the field plate terminal 19b drawn out from the field plate electrode 19 is connected to the gate terminal 12a drawn out from the gate electrode 12 by forming a contact hole 23 in the interlayer insulating film 18'. is configured to do so.

Next, the manufacturing method of the above thin film transistor is shown in FIG. 3(a).
The explanation will be given below using the manufacturing process cross-sectional explanatory diagrams shown in (d).

A film of Cr or Ta is deposited to a thickness of about 500 Å on a substrate 11 made of glass or the like by sputtering. A pattern for the gate electrode 12 is formed through a first photolithography process.

Next, a silicon nitride film (S i
Nx ) at about 3000A, SiH.

1, which is the semiconductor layer 14, by a plasma CVD method using
-a-3i at about 500 A at a temperature of 250°C to 300°C, and SiNx as a channel protective film 15 by a plasma CVD method using SiH and NH at a temperature of 200°C to 270°C.
It is continuously deposited to a thickness of about 150 OA at a temperature of .degree. C. (see FIG. 3(a)).

Next, a resist pattern for the channel protective film 15 is formed through a second photolithography process, and HF and N
Etching is performed with a mixture of H and F to form the channel protective film 1.
Form 5 patterns.

After degreasing and cleaning process, PH,
The n+ amorphous silicon (n+a-8i) which is the ohmic contact layer 16 is made of 100O
It is deposited to a thickness of about A.

Subsequently, a Cr film serving as the diffusion prevention layer 17 is deposited to a thickness of about 1500 Å by sputtering.

Cr is patterned through a third photolithography process, and then n''a-5i is patterned in an etching process using a mixed solution of hydrofluoric acid, nitric acid, and phosphoric acid. At this time, the pattern of the semiconductor layer 14 is also formed using the resist pattern in which the patterns of the source electrode 21 and the drain electrode 22 are formed (FIG. 3(b)).
reference).

Thereafter, silicon oxide (S i Ox
) is deposited to a thickness of approximately 5000A (see Figure 3(c)).
)reference).

Next, through a fourth photolithography process, HF, NH, and F
A pattern of the interlayer insulating film 18' is formed by etching with a mixed solution of the above. At this time, the source electrode 21 and the drain electrode 2
A contact hole 23 for connecting the wiring metal layers 20a and 20b is formed in 2, and a contact hole 23 for connecting the field plate terminal 19b to the gate terminal 12a is further formed.

After removing the resist, aluminum (AI) is deposited on the resist to a thickness of about 1 μm by sputtering.

``After the fifth photolithography process, the AI is etched using a mixed solution of acetic acid, nitric acid, phosphoric acid, and water to form the field plate electrode 19 and the wiring metal layer 20 (see FIG. 3(d)). ).

In this way, a thin film transistor is manufactured in which silicon oxide (SiOx) is used for the interlayer insulating film 18' and the field plate terminal 19b and the gate terminal 12a are in contact.

In this embodiment, the field plate terminal 19b and the gate terminal 12a are brought into contact so that the gate electrode 12 and the field plate electrode 19 are at the same potential.

In the conventional example, a voltage of 100V was applied to the field plate electrode and 20V to the gate electrode, but as in this embodiment, the interlayer insulating film is made of silicon oxide (S).
If a thin inorganic film having a high dielectric constant εr such as silicon nitride (iOx) or silicon nitride (S i Nx ) is used, the field plate electrode 19 can function satisfactorily even at a voltage of 20V.

Specifically, the conventional interlayer insulating film 18 has a dielectric constant εr-4
A polyimide organic film with a thickness of about 1 μm was used in
The interlayer insulating film 18' of this embodiment is an inorganic film of silicon oxide (SiOx) with a dielectric constant of εr-4 or silicon nitride (S i NX ) with a dielectric constant of εr-6.5 and has a thickness of 0.5 μm.
I plan to use it to a certain degree. Therefore, even if the field plate electrode 19 is applied with the same voltage of 20V as the gate electrode 12, the field plate can sufficiently control the inflow path of electrons from the channel region L1 to the offset region L2, and the transistor characteristics It functions to reduce changes over time.

In another embodiment, the interlayer insulating film 18' is made of 5iON.
An inorganic membrane such as a membrane may also be used.

According to this embodiment, since the field plate terminal 19b drawn out from the field plate electrode 19 is connected to the gate terminal 12a drawn out from the gate electrode 12 via the contact hole 23, the field plate terminal 19b is connected to the field plate terminal 19b drawn out from the field plate electrode 19. There is no need to connect wiring, etc., which gives you more leeway in your design when increasing integration.
This has the effect of realizing high-density devices.

Furthermore, since the number of terminals is reduced and there is more leeway in the design, there is an effect that the manufacturing yield can be increased.

(Effect of the invention) According to the invention as claimed in claim 1, the offset area is provided,
In a high voltage thin film transistor provided with a field plate electrode, the terminal drawn out from the field plate electrode is connected to the terminal drawn out from the gate electrode, so the terminal drawn out from the field plate electrode is connected to another terminal drawn out from the field plate electrode. There is no need to connect to wiring, etc., and there is an effect that the device can be highly integrated.

According to the invention according to claim 2, it has an offset area,
In a high voltage thin film transistor in which a field plate electrode is provided on a channel protective film via an interlayer insulating film, a terminal drawn out from the field plate electrode is
Since the thin film transistor is connected to the terminal drawn out from the gate electrode and the interlayer insulating film is an inorganic film, the inorganic interlayer insulating film has excellent dielectric properties and voltage resistance.
Even if the field plate electrode has the same potential as the gate electrode, it is possible to stably control the inflow path of electrons inside the semiconductor layer, which has the effect of reducing changes in the transistor element over time.

[Brief explanation of the drawing]

FIG. 1 is an explanatory plan view of a thin film transistor according to an embodiment of the present invention, FIG. 2 is an explanatory cross-sectional view of the section A-A' in FIG. FIG. 4 is a plan view of a conventional thin film transistor, FIG. 5 is a cross-sectional view taken along line BB' in FIG. 4, and FIG. 6 is an inverter circuit diagram. 11...Substrate 12...Gate electrode 13...Gate insulating film 14...Semiconductor layer 15...Channel protective film 16... ...Ohmic contact layer 17...
...Diffusion prevention layer 18...Interlayer insulating film 19...Field plate electrode 20...
...Metal layer for wiring 21...Source electrode 22...Drain electrode 23...Contact hole 1st cause Figure 2 υ ℃ Figure 4 Figure 5 Figure 6

Claims (2)

[Claims] (1) A gate electrode, a gate insulating film, a semiconductor layer, a channel protective film, a source electrode, and a drain electrode are provided on a substrate, and an offset region is provided between the gate electrode and the drain electrode, and an offset region is provided between the gate electrode and the drain electrode. In a thin film transistor having a field plate electrode on the upper side via an interlayer insulating film so as to cover the end portion on the drain electrode side, a terminal drawn out from the field plate electrode,
A thin film transistor, characterized in that it is connected to a terminal drawn out from the gate electrode. (2) The thin film transistor according to item 1, wherein the interlayer insulating film is an inorganic film.