JPH04162532A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04162532A JPH04162532A JP2289707A JP28970790A JPH04162532A JP H04162532 A JPH04162532 A JP H04162532A JP 2289707 A JP2289707 A JP 2289707A JP 28970790 A JP28970790 A JP 28970790A JP H04162532 A JPH04162532 A JP H04162532A
- Authority
- JP
- Japan
- Prior art keywords
- film
- barrier film
- opening part
- bump electrode
- barrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052802 copper Inorganic materials 0.000 abstract description 10
- 239000010949 copper Substances 0.000 abstract description 10
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000009713 electroplating Methods 0.000 abstract description 2
- 230000001681 protective effect Effects 0.000 abstract 5
- 238000000034 method Methods 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 14
- 229910052782 aluminium Inorganic materials 0.000 description 14
- 238000007747 plating Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に突起電極を有する半導
体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having protruding electrodes.
従来の突起電極（以下バンブ電極と記す）を有する半導
体装置について、図面を参照して説明する。A semiconductor device having a conventional bump electrode (hereinafter referred to as a bump electrode) will be described with reference to the drawings.
第４図は従来の半導体装置の一例を示す断面図である。FIG. 4 is a sectional view showing an example of a conventional semiconductor device.
第４図に示すように、シリコン基板１の上に厚い酸化シ
リコン膜２を設け、酸化シリコン膜２の上にトランジス
タや抵抗素子などを相互に接続し外部に引き出すための
アルミニウム配線３を形成する０次に、アルミニウム配
線３を含む表面に表面保護膜として窒化シリコン膜５を
形成し、アルミニウム配線３上の窒化シリコン膜３に開
孔部を設ける。この開孔部を含む表面に設けたチタン族
等のバリア膜４を介して、電気めっき法によって形成さ
れた１５〜２０μｍの厚さの銅めっき膜からなるバンブ
電極７が配置されている。更に、このバンブ電極７の表
面には酸化防止の為に３〜４μｍの厚さの金めつき膜８
が形成されて半導体装置が構成されている。As shown in FIG. 4, a thick silicon oxide film 2 is provided on a silicon substrate 1, and aluminum wiring 3 is formed on the silicon oxide film 2 for interconnecting transistors, resistance elements, etc. and drawing them out to the outside. Next, a silicon nitride film 5 is formed as a surface protection film on the surface including the aluminum wiring 3, and an opening is provided in the silicon nitride film 3 on the aluminum wiring 3. A bump electrode 7 made of a copper plating film with a thickness of 15 to 20 μm formed by electroplating is arranged via a barrier film 4 of titanium group or the like provided on the surface including the opening. Furthermore, a gold plating film 8 with a thickness of 3 to 4 μm is provided on the surface of the bump electrode 7 to prevent oxidation.
are formed to constitute a semiconductor device.
このバンブ電極７には外部リードが熱圧着によって接続
される。An external lead is connected to this bump electrode 7 by thermocompression bonding.
この従来の半導体装置は、表面保護膜の上に、バリア膜
と銅めっき膜からなるバンブ電極が接して形成される。In this conventional semiconductor device, a bump electrode made of a barrier film and a copper plating film is formed on a surface protection film in contact with the bump electrode.
従って、外部リードを熱圧着した際に圧力が表面保護膜
にも加わり表面保護膜にクラックが生じ半導体装置の信
頼性を低下させるという問題点があった。Therefore, when the external leads are bonded by thermocompression, pressure is applied to the surface protection film, causing cracks in the surface protection film and reducing the reliability of the semiconductor device.
又、クラック防止の為に、外部リードを熱圧着する際に
加える圧力を小さくすると、バンブ電極と外部リードと
の接着強度が小さくなりリード剥れが生ずるという問題
点があった。Furthermore, if the pressure applied when thermocompression bonding the external leads is reduced in order to prevent cracks, there is a problem in that the adhesive strength between the bump electrode and the external leads decreases, resulting in lead peeling.
本発明の半導体装置は、半導体基板の一生面に設けた絶
縁膜の上に設けた配線と、前記配線の上に設けたバリア
膜と、前記バリア膜を含む表面に設けた表面保護膜と、
前記バリア膜の上の表面保護膜に設けた開孔部と、前記
バリア膜上に設け且つ前記開孔部周囲の表面保護膜との
間に空隙を有する突起電極とを備えている。A semiconductor device of the present invention includes a wiring provided on an insulating film provided on a whole surface of a semiconductor substrate, a barrier film provided on the wiring, and a surface protection film provided on a surface including the barrier film.
The device includes an aperture provided in a surface protection film above the barrier film, and a protruding electrode provided on the barrier film and having a gap between the surface protection film and the surface protection film around the aperture.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（Ｃ）は本発明の一実施例の製造方法を
説明するための工程順に示した半導体チップの断面図で
ある。FIGS. 1A to 1C are cross-sectional views of a semiconductor chip shown in order of steps for explaining a manufacturing method according to an embodiment of the present invention.
まず、第１図（ａ）に示すように、シリコン基板１の上
に厚い酸化シリコン膜２を設ける。次に、酸化シリコン
膜２の上に厚さ１〜１．５μｍのアルミニウム膜及びチ
タン膜を順次スパッタにより堆積し、選択的にエツチン
グしてパターニングしアルミニウム配線３上にチタン膜
からなるバリア膜４を積層して設ける。このアルミニウ
ム配線３はシリコン基板１内に形成されているトランジ
スタや抵抗等の素子と電気的に接続されている。次に、
アルミニウム配線３を含む表面に気相成長法により表面
保護膜用の窒化シリコン膜５を１μｍの厚さに堆積し、
アルミニウム配線３上の窒化シリコン膜５を選択的にエ
ツチングしてバンブ電極形成用の開孔部６を形成する。First, as shown in FIG. 1(a), a thick silicon oxide film 2 is provided on a silicon substrate 1. Next, an aluminum film and a titanium film with a thickness of 1 to 1.5 μm are sequentially deposited on the silicon oxide film 2 by sputtering, selectively etched and patterned, and a barrier film 4 made of a titanium film is placed on the aluminum wiring 3. are laminated. This aluminum wiring 3 is electrically connected to elements such as transistors and resistors formed in the silicon substrate 1. next,
A silicon nitride film 5 for a surface protection film is deposited to a thickness of 1 μm on the surface including the aluminum wiring 3 by vapor phase growth.
The silicon nitride film 5 on the aluminum wiring 3 is selectively etched to form an opening 6 for forming a bump electrode.
次に、開孔部６を含む表面にスパッタ法により０．５μ
ｍの厚さの銅膜９を設け、めっき電流路用の導電膜を形
成する。Next, the surface including the opening 6 is coated with a 0.5 μm coating by sputtering.
A copper film 9 having a thickness of m is provided to form a conductive film for a plating current path.
次に、第１図（ｂ）に示すように、フォトレジスト膜１
０を全面に塗布してパターニングし、開孔部６の内側に
開孔部６よりも小さい寸法の開孔部を設けて露出させた
銅膜９の上に電気めっきを行ない厚さ２０μｍの銅めっ
き膜からなるバンブ電極７を形成する０次に、バンブ電
極７の表面に３〜４μｍの厚さに金めつき層８を設ける
。ここで、チタン膜等のバリア膜４はアルミニウム膜３
とバンプ電極材料である銅との反応を抑制するバリア膜
として作用する。Next, as shown in FIG. 1(b), the photoresist film 1
Copper film 9 with a thickness of 20 μm is applied on the exposed copper film 9 by forming an opening smaller than the opening 6 inside the opening 6 and patterning it. Next, a gold plating layer 8 is provided on the surface of the bump electrode 7 to a thickness of 3 to 4 μm. Here, the barrier film 4 such as a titanium film is replaced by the aluminum film 3.
It acts as a barrier film to suppress the reaction between copper and bump electrode material.
次に、第１図（ｃ）に示すように、有機溶剤でフォトレ
ジスト膜１０を除去した後に、バンブ電極７をマスクと
して銅膜９をリン酸溶液でエツチングして除去し、バン
ブ電極７の底部外周と窒化シリコン膜５との間に空隙を
設ける。Next, as shown in FIG. 1(c), after removing the photoresist film 10 with an organic solvent, the copper film 9 is removed by etching with a phosphoric acid solution using the bump electrode 7 as a mask. A gap is provided between the bottom outer periphery and the silicon nitride film 5.
第２図は本発明の第２の実施例を示す半導体チップの断
面図である。FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention.
第２図に示すように、バリア膜４がバンプ電極形成領域
のアルミニウム膜３よりも小さく且つ開孔部６よりも大
きい寸法で形成された以外は第１の実施例と同じ構成を
有しており、下層よりアルミニウム膜３．チタン膜４．
バンブ電極７の底面の順に寸法が小さく階段状に構成さ
れており、外部リードを接続するときの圧力が分散され
てクラックの発生を抑える効果を向上させる利点がある
。As shown in FIG. 2, the barrier film 4 has the same structure as the first embodiment except that the barrier film 4 is formed with dimensions smaller than the aluminum film 3 in the bump electrode formation region and larger than the openings 6. The aluminum film 3. Titanium film 4.
The bottom surface of the bump electrode 7 is structured in a stepped manner, with dimensions decreasing in order, which has the advantage of dispersing the pressure when connecting external leads and improving the effect of suppressing the occurrence of cracks.
以上説明したように本発明は、アルミニウム配線とバン
プ材との反応を防止する為のバリア膜をアルミニムラ配
線上に積層し、このバリア膜を含む表面に形成した表面
保護膜の開孔部の周囲に空隙を設けてバンブ電極を形成
することにより、外部リードを接着する際に発生してい
た表面保護膜のクラックを防止して、半導体装置の信頼
性を向上させるという効果を有する。As explained above, the present invention involves laminating a barrier film on uneven aluminum wiring to prevent a reaction between the aluminum wiring and the bump material, and forming a surface protection film around the openings on the surface including the barrier film. By forming a bump electrode with a gap provided in the bump electrode, cracks in the surface protection film that occur when external leads are bonded can be prevented, and the reliability of the semiconductor device can be improved.
第１図（ａ）〜（ｃ）は本発明の一実施例の製遣方法を
説明するための工程順に示した半導体チップの断面図、
第２図は本発明の第２の実施例を示す半導体チップの断
面図、第３図は従来の半導体装置の一例を示す半導体チ
ップの断面図である。
１・・・シリコン基板、２・・・酸化シリコン膜、３・
・・アルミニウム配線、４・・・バリア膜、５・・・窒
化シリコン膜、６・・・開孔部、７・・・バンプ電極、
８・・・金めつき膜、９・・・銅膜、１０・・・フォト
レジスト膜。FIGS. 1(a) to 1(c) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to an embodiment of the present invention;
FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention, and FIG. 3 is a sectional view of a semiconductor chip showing an example of a conventional semiconductor device. 1... Silicon substrate, 2... Silicon oxide film, 3.
... Aluminum wiring, 4... Barrier film, 5... Silicon nitride film, 6... Opening part, 7... Bump electrode,
8... Gold plating film, 9... Copper film, 10... Photoresist film.
Claims (1)
と、前記配線の上に設けたバリア膜と、前記バリア膜を
含む表面に設けた表面保護膜と、前記バリア膜の上の表
面保護膜に設けた開孔部と、前記バリア膜上に設け且つ
前記開孔部周囲の表面保護膜との間に空隙を有する突起
電極とを備えたことを特徴とする半導体装置。A wiring provided on an insulating film provided on one main surface of a semiconductor substrate, a barrier film provided on the wiring, a surface protection film provided on a surface including the barrier film, and a surface protection film provided on the barrier film. 1. A semiconductor device comprising: an aperture provided in a surface protection film; and a protruding electrode provided on the barrier film and having a gap between the surface protection film and the surface protection film around the aperture.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2289707A JPH04162532A (en) | 1990-10-25 | 1990-10-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2289707A JPH04162532A (en) | 1990-10-25 | 1990-10-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04162532A true JPH04162532A (en) | 1992-06-08 |
Family
ID=17746714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2289707A Pending JPH04162532A (en) | 1990-10-25 | 1990-10-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04162532A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917231A (en) * | 1997-02-17 | 1999-06-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including an insulative layer having a gap |
| JP2010535411A (en) * | 2007-07-30 | 2010-11-18 | エヌエックスピー ビー ヴィ | Stress buffering semiconductor components |
-
1990
- 1990-10-25 JP JP2289707A patent/JPH04162532A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917231A (en) * | 1997-02-17 | 1999-06-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including an insulative layer having a gap |
| JP2010535411A (en) * | 2007-07-30 | 2010-11-18 | エヌエックスピー ビー ヴィ | Stress buffering semiconductor components |
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