JPH04158466A - Inter-processor data transfer system - Google Patents

Abstract

PURPOSE:To shorten the occupied time of a common bus according to data transfer by storing transfer data from buffer memory in a transmission FIFO part when the data transfer is performed, and storing the transfer data from the common bus in a reception FIFO part via a bus transfer control part. CONSTITUTION:When the data transfer is performed, the transfer data from the buffer memory 5, 55 are stored in the transmission FIFO parts 1, 51, and also, the transfer data from the common bus 7 are stored in the reception FIFO parts 2, 52 via bus transfer control parts 3, 53. As a result, transmission underflow and reception overflow generated due to the access contention of the buffer memory 5, 55 can be prevented from occurring. Thereby, the access contention of the buffer memory 5, 55 during a data transfer operation on the common bus 7 can be evaded, therefore, the occupied time of the common bus according to those data transfer can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer method between processors, and more particularly to an inter-processor data transfer method that performs burst transfer of data via a common bus.

[Prior Art] FIG. 3 shows a block diagram of a device to which this type of conventional inter-processor data transfer method is applied. In the figure, one access port of a dual port memory control unit (hereinafter referred to as DPMC) 4 in a processor module 10 is connected to an address line 20 of a processor (hereinafter referred to as CPU) 6. A data line 21 and a control line 22 are connected to the other access port, and address lines 30 . A data line 31 and a control line 32 are connected to perform access arbitration between the CPU 6 and BCTL 3, and at the same time, a buffer memory (hereinafter referred to as BM)
Execute read/write operation to 5. The common bus access side of the BCTL 3 is connected to the common bus 7, and the processor module 11 connected to the common bus 7 has a similar configuration.

Next, the operation during data transfer from the processor module 10 to the processor module 11 will be described.

The CPU 6 in the processor module 10 writes the data to be transferred to the 8M5 via the DPMC 4, and then
The BCTL 3 is instructed to perform a transfer operation by specifying the address of the transfer data and the number of transfer bytes. Upon receiving this instruction, the BCTL 3 acquires the right to use the common bus 7 from a bus arbiter (not shown), accesses the 8M5 via the DPMC 4, and starts reading the instructed transfer data.

The thus read transfer data is output to the common bus 7 in bursts at predetermined timing via the BCTL 3. The BCTL 53 in the processor module 11 receives transfer data on the common bus 7 in a burst manner at a predetermined timing, and transfers the data to the D PMC 5 via the BCTL 53.
This transfer data is written to a pre-designated address in the BM 55 via 4. At this time, in either the processor module 10 or the processor module 11, access conflict with the CPU 6.56 occurs when accessing 8M5 and 8M55, and as a result,
A transmission underflow occurs in the BCTL 3 on the sending side, and a reception overflow occurs in the BCTL 53 on the receiving side.To prevent these occurrences, the common bus 7
Transfer control is performed using the wait output of the bus.

Then, the BCT in the processor module 10 on the sending side
When the L3 completes data transfer for the designated number of bytes, it notifies the CPU 6 of the completion of the transfer. Further, when the transfer operation on the bus is completed, the BCTL 53 in the processor module 11 on the reception side notifies the CPU 56 of the completion of the reception operation. FIG. 4 shows the sequence of transmitting and receiving operations during such data transfer.

[Problem to be solved by the invention] In the conventional inter-processor data transfer system, BCT
As a result of the access conflict that occurs when L3 and 5B access 8M5.55, transfer control is performed by wait output on the common bus 7, which has the disadvantage that the exclusive time of the common bus 7 becomes long. And such problems are solved by CP
If there is a high frequency of access to 8M5.55 of U6.56 or DM for 8M5.55 from CPU6,56
When directly transferring data using method A,
Especially noticeable.

[Means for Solving the Problems] In order to solve these problems, the inter-processor data transfer method according to the present invention includes a bus transfer control section that controls data transfer via a common bus, and a bus transfer control section that stores transfer data. a buffer memory for sending the transfer data to the common bus via the bus transfer control unit; a transmission FIFO unit for storing transfer data read from the buffer memory for sending the transfer data to the common bus via the bus transfer control unit; and a reception FIFO section for storing transfer data.

[Operation] When data is transferred, data transferred from the buffer memory is stored in the transmission FIFO section, and data transferred from the common bus is stored in the reception FIFO section via the bus transfer control section. As a result, the transmission underflow and reception overflow that occur due to buffer memory access contention no longer occur.

[Example code] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a device to which the inter-processor data transfer method of the present invention is applied. In the figure, one access port of the DPMC 4 in the processor module 10 has an address line 20. While the data line 21 and II control line 22 are connected,
An address line 30 and a control line 32 for memory access of the BCTL 3 are connected to the other access port, and data 1142 from a transmission FIFO (hereinafter referred to as 5PIFO) 1 and a reception FIFO (hereinafter referred to as RFIFO) 2 are connected to the other access port.
is connected. In addition, the data line 31 of BCTL3 is a 5P that temporarily stores transmission data read from the BMS.
It is connected to the data input side from IFOI and the data output side to RFIFO2 which temporarily stores received data input from common bus 7, and at the same time access arbitration between CPU6 and BCTL3 is performed, read/write operation to 8M5 is performed. is executed.

As mentioned above, BCTL3 connects the data line 31 to the data output side of 5PIFOI and the data input side of RFIFO2.
is connected, and writes data received from the common bus 7 to the RFI FO2 during a data transfer operation via the common bus 7. Note that the processor module 11 connected to this common bus 7 also has a similar configuration.

Next, the operation of data transfer from the processor module 10 to the processor module 11 will be described.

The CPU 6 in the processor module 10 writes the data to be transferred to the 8M5 via the DPMC 4, and then
The BCTL 3 is instructed to perform a transfer operation by specifying the address within 8MS of transfer data and the number of transfer bytes. BCTL3, which received this instruction, sends 8M5 via DPMC4.
, read the specified transfer data, and return to 5F.
Write to IFO1. The write operation to this 5 FIFOI is instructed via the control line 40 at a predetermined timing.

In this way, BCTL3 stores all transferred data in 5 FIFOI
After writing to the SF I FOl, the right to use the common bus 7 is acquired from a bus arbiter (not shown), and while reading the transfer data from the SF I FOl, it is transmitted onto the common bus 7 in bursts at a predetermined timing. At this time, since all the data to be transmitted is within the 5 FIFOI, the transmission under 70-, which conventionally occurred due to access contention of the BM5, no longer occurs.

On the other hand, the BCTL in the processor module 11 on the receiving side
5B receives transfer data on the common bus 7 in a burst manner at a predetermined timing, and writes it to the RFIFO 52.
1, the BCTL 53 issues an instruction at a predetermined timing. At this time, since the received data is written to the RFIFO 52, the reception overflow that conventionally occurred due to access contention of the BM 55 does not occur.

When the BCTL 53 starts writing received data to the RFIFO 52 or when writing all received data to the RFIFO 52 is completed, the address line 70
．． Control line 72 and RFIFO control line 81 are instructed at predetermined timing to transfer data in RFIFO 52 to DP.
Write to 8M55 via MC54.

In this way, the BC in the processor module 10 on the sending side
When the TL3 completes data transfer for the designated number of bytes, it notifies the CPU 6 of the completion of the transfer. In addition, the BCTL53 in the processor module ll on the receiving side is
When all the data received from the common bus 7 and written to the RFIFO 52 is written to the 8M55, the CPU 56
Notify the recipient of the completion of the receiving operation. FIG. 2 shows the sequence of transmission and reception operations for such data transfer.

As described above, according to the present invention, buffer memory access contention during data transfer operations on a common bus is avoided, and therefore the exclusive time of the common bus associated with these data transfers can be shortened.

[Effects of the Invention] As explained above, the inter-processor data transfer method according to the present invention stores the transfer data from the buffer memory in the transmission FIFO section when transferring data, and also stores the transfer data from the common bus into the bus. Receive F via transfer control unit
Since the data is stored in the IFO section, transmission underflow and reception overflow caused by buffer memory access conflicts are avoided, and the time required for the common bus to be used for these data transfers can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a device to which the inter-processor data transfer method according to the present invention is applied, FIG. 2 is an explanatory diagram showing this operation sequence, and FIG. The block diagram shown in FIG. 4 is an explanatory diagram illustrating this operation sequence. 1.51...Transmission FIFO 52, 52...Reception FIFO 13, 53...Bus transfer control unit, 4.54
...Dual port memory control section, 5, 55...
・Buffer memory, 6゜56... Processor, 7.
... common bus, 10.11 ... processor module, 20.30.60.70 ... address line, 2
1.31, 42, 61, 71.82...data line,
22, 32, 40, 41, 62, 72, 80.81...
...Control line.

Claims (1)

[Scope of Claims] An inter-processor data transfer method in which burst transfer of data is performed between a plurality of processor modules connected to a common bus via the common bus, comprising: a bus for controlling data transfer via the common bus; a transfer control unit, a buffer memory that stores transfer data, and a transmission FIFO unit that stores transfer data read from the buffer memory in order to send the transfer data to the common bus via the bus transfer control unit. An inter-processor data transfer method, comprising: a receiving FIFO unit that stores transfer data sent from the bus transfer control unit to the buffer memory.