JPH04156072A - Head split type camera - Google Patents

Abstract

PURPOSE:To detect a delay quantity depending on a length of a cable without increasing number of wires by superimposing a phase shift detection pulse onto a sensor output signal with a phase shift detection pulse superimposing circuit. CONSTITUTION:A pulse used for a phase compensation circuit 8 of a CCU section 5 is outputted for an optional period within a blanking period of a sensor output signal of a solid-state image pickup element 2 and superimposed on the sensor output signal by a phase shift detection pulse superimposing circuit 4. The sensor output signal is inputted to a process circuit 7 and a phase compensation circuit 8 of the CCU section 5 via a cable section 9 and the superimposed pulse is separated from the sensor output signal inputted to the phase compensation circuit 8 and the timing of the CCU section 5 is compared to generate a timing pulse for clamp or sample and holding for the process circuit 7. The process circuit 7 receives the timing pulse and the phase shift in the sensor output signal is compensated and processed. Thus, the delay is detected without increasing number of wires in the cable section to eliminate the phase shift.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a head-separated camera in which a camera head section and a camera control unit section (hereinafter abbreviated as CCU section) are separated via a cable section. .

[Conventional technology]

Conventionally, when observing a narrow area or when it is necessary to install a camera in a limited space, a camera head section with a compact mounted solid-state image sensor and a CCU section equipped with a process circuit etc. for processing the imaging signal are used. A separate camera system is used. FIG. 8 is a diagram showing an example of the configuration of such a camera system, in which a solid-state image sensor 101 and a drive circuit 10 that sends a signal to drive the image sensor 101 are shown.
2, an SSG circuit 104 that generates a clock signal etc. to the drive circuit 102 of the camera head section 103, and a process circuit 105 that processes the output signal of the solid-state image sensor 101. part 106, the camera head part 103 and 000 part 1
06.

In addition, as a solid-state image sensor suitable for head-separated cameras used for purposes such as observing narrow areas or installing in limited spaces, it has a low number of input clocks and a high degree of freedom in driving clock signals. A solid-state image sensor with a built-in drive circuit has been proposed by the inventor of the present invention in Japanese Patent Laid-Open No. 86677/1983. That is, as shown in FIG. 9, the proposed solid-state image sensor 111 includes a counter circuit 1112 to which a reference clock signal FCK and an input signal FIIX are input, a vertical scanning circuit 113 consisting of a shift register, and a charge modulation element (Charge Mod).
a light receiving section 114 in which photoelectric conversion elements such as CMD (abbreviated as CMD) are arranged in a matrix; a horizontal scanning circuit 116 consisting of a horizontal clock generation circuit 115 to which a clock signal FCx is input; and a shift register; These peripheral circuits and the light receiving section are formed on the same semiconductor substrate.

Then, the counter circuit 112 receives the reference clock signal Fcx.
The counting operation starts when a change in the input signal FIX occurs based on the vertical scanning circuit 113 and horizontal scanning circuit 1
16 and the vertical clock signal■, respectively. , outputs a vertical input pulse signal VIN and a horizontal input pulse signal HIN. On the other hand, horizontal clock generation circuit 115 outputs horizontal clock signal HCK to horizontal scanning circuit 116 based on reference clock signal Fcw. When the horizontal input pulse signal HIM is input to the horizontal scanning circuit 116, the signal HI
The horizontal output pulse signal H8U is fed back to the counter circuit 112, counted again, and sent to the horizontal scanning circuit 116 as the horizontal input pulse signal HIN. In this way, the device is configured to run by itself when a horizontal input pulse signal is generated.

In this way, the vertical scanning circuit 113 receives the vertical clock signal ■. and the vertical input pulse signal VIN, and the horizontal scanning circuit 116 generates a driving pulse signal according to the horizontal clock signal HCK and the horizontal input pulse signal HIM.
14 photoelectric conversion elements are driven and scanned.

[Problem to be solved by the invention]

By the way, in a head-separated camera configured as described above in which the camera head section and the CCU section are separated, the length of the cable section can be changed depending on the object to be imaged. When the length of the CCU section is changed, there is a problem in that the amount of delay changes between the timing of the process circuit and the output signal from the solid-state image sensor in the CCU section, resulting in a phase shift. The amount of delay due to this cable length is empirically said to be 5 ns/m.

Conventionally, as a means for detecting the amount of delay due to the cable length, as shown in FIG. ! via 108, SSG
The clock signal from the circuit 104 is passed through the cable section 107 without any phase shift, and the clock signal is used as a phase shift detection pulse to detect the amount of delay.
The timing of the process circuit 105 of the 00 unit 106 is corrected. Note that in FIG. 10, 109 is a signal output line.

However, the delay amount detection means having such a configuration has the problem of increasing the number of wiring lines.

The present invention has been made to solve the above-mentioned problems in conventional head-separated cameras. The purpose is to provide a type camera.

[Means and effects for solving the problems] In order to solve the above problems, the present invention provides a camera head section equipped with a solid-state image sensor and a camera head section equipped with a process circuit for processing an image pickup signal.
In a head-separated camera in which a CU section is separated via a cable section, a pulse is sent to the camera head section to detect a phase shift in the output signal of the image sensor due to the length of the cable section. A phase shift detection pulse superimposition circuit is provided to superimpose the phase shift detection pulse on the output signal, and the CCU section sends a signal whose phase has been compensated for the delay caused by the cable section based on the phase shift detection pulse superimposed on the output signal to the process circuit. A phase compensation circuit is provided.

In a head-separated camera configured in this way,
The phase shift detection pulse superimposition circuit provided in the camera head section superimposes the phase shift detection pulse on the image sensor output signal, and transmits it to the CCU section via the cable section with a delay depending on the length of the cable section. be done. Then, based on the E phase shift detection pulse transmitted to the CCU section, the phase compensation circuit sends a signal with the phase shift compensated for to the process circuit, and the process circuit processes the imaging signal output with an appropriate phase. Thereby, it is possible to easily detect the amount of delay in the cable section and eliminate the phase shift without increasing the number of wires in the cable section.

〔Example〕

Next, an example will be described. FIG. 1 is a block diagram showing a first embodiment of a head-separated camera according to the present invention. In FIG. A solid-state image sensor 2 in which peripheral circuits such as a circuit and a preamplifier are integrally formed;
A phase shift detection pulse superimposition circuit 4 connected to the sensor output line 3 of the solid-state image sensor 2 is provided. 5 is CCU
The section includes an SSG circuit 6 that sends pulses such as a reference clock to the solid-state image sensor 2 of the camera head section 1, a process circuit 7 that processes the sensor output signal of the solid-state image sensor 2, and a phase compensation circuit for cable length delay. A circuit 8 is provided. The camera head section 1 and the CC0 section 5 are connected by a cable section 9.

In a head-separated camera configured in this way,
The phase shift detection pulse superimposition circuit 4 detects the sensor output signal of the solid-state image sensor 2 during an arbitrary period within the blanking period.
A pulse used in the phase compensation circuit 8 of the CC0 section 5 is output and superimposed on the sensor output signal.

The sensor output signal on which the second pulse is superimposed is sent to the cable section 9.
After that, the process circuit 7 and the phase compensation circuit 8 of the CC0 section 5
is input to. The sensor output signal input to the process circuit 7 is subjected to processing such as clamping or sample hold for each pixel. On the other hand, the superimposed pulses of the sensor output signal input to the phase compensation circuit are separated and compared with the timing of the CC0 section 5 to create a timing pulse for clamping or sample hold in the process circuit 7. . The process circuit 7 receives this timing pulse, compensates for the phase shift of the sensor output signal, and performs processing.

Next, a configuration example of the phase shift detection pulse superimposition circuit 4 will be explained. FIG. 2 shows a pulse superimposition circuit for phase shift detection applied to a camera head using a solid-state image pickup device with CMD pixels. In FIG. a horizontal selection switch that selects the vertical signal line 13 of and connects it to the sensor output line 14;
15 is a horizontal shift register for driving the horizontal selection switch 12; 16 is an overflow voltage source V for causing the CMD pixels constituting the light receiving section to perform an overflow operation. A switch connected between F and the sensor output line 14, which is conductive while the EOS (one pulse signal output from the final stage of the shift register) of the horizontal shift register 15 is at "H" level. Then, an overflow voltage source ■ is applied to the sensor output line 14. , is configured so that current flows through it. Note that 17 is a vertical shift register.

In the pulse superimposition circuit for phase shift detection configured in this way, as shown in FIG.
8 is generated, and an output is obtained in which the pulse 18 is superimposed on the sensor output signal.

FIG. 4 is a diagram showing another example of the configuration of the pulse superimposition circuit for detecting a phase shift, and this example configuration is applied to a camera head using a CMD image sensor with a built-in self-running drive circuit shown in FIG. 9. In FIG. 0, reference numeral 21 denotes a free-running drive circuit, which corresponds to the counter circuit and horizontal clock generation circuit in the solid-state image pickup device shown in FIG. This free-running drive circuit 21 generates a pulse of a certain arbitrary width within the IH blanking period, and uses it as a control pulse for a switch 22 whose one end is connected to the sensor output line 14 and the other end is connected to the reference clock signal F0.

In the phase shift detection pulse superimposition circuit configured in this manner, as shown in FIG. 5, an output in which the reference clock signal Fcx is superimposed on the sensor output signal is obtained during any period within the IH blanking period.

Next, a configuration example of the process circuit 7 and phase compensation circuit 8 shown in FIG. 1 is shown in FIG. The phase compensation circuit 8 includes a superimposed pulse extraction circuit 311, a phase adjustment circuit 32. Phase comparator 33. Low-pass filter 34° voltage controlled oscillator (■
○F) 35.1/N circuit 36, and the process circuit 7 includes a sample hold circuit 41 and a video processing circuit 42.

Next, the operations of the phase compensation circuit 8 and the process circuit 7 configured as described above will be explained. The sensor output signal on which the phase shift detection pulse is superimposed is input to two circuit blocks, the phase compensation circuit 8 and the process circuit 7. In the phase compensation circuit 8, the superimposed pulse extraction circuit 31 is first input.
, only the superimposed phase shift detection pulses shown in FIGS. 3 and 5 are extracted. The extracted pulses are phase-adjusted in the phase adjustment circuit 32, and then
The phase comparator 33 compares the phase with the timing pulse to the sample and hold circuit 41 of the process circuit 7, and inputs the result to the voltage controlled oscillator 35 via the low pass filter 34, and outputs the timing pulse to the sample and hold circuit 41. Apply a phase shift compensation feedbank to .

In the process circuit 7, the sensor output signal is input to the sample and hold circuit 41, and is sampled and held by the timing pulse corrected to an appropriate phase by the phase compensation circuit 8. At step 42, video processing such as A/D conversion is added.

FIG. 7 is a block diagram showing the second embodiment,
Components that are the same as or equivalent to those of the embodiment shown in FIG. 1 are designated by the same reference numerals. In this embodiment, a pulse superimposition circuit 4 for detecting a phase shift is integrally formed on the same semiconductor substrate 51 as a solid-state image sensor 2 consisting of a light receiving element and its peripheral circuits, and the other configuration is This is the same as the first embodiment. In this embodiment, the phase shift detection pulse can be superimposed on the sensor output signal without increasing the mounting area of the camera head section 1.

〔Effect of the invention〕

As described above based on the embodiments, according to the present invention, the phase shift detection pulse is superimposed on the sensor output signal by the phase shift detection pulse superimposition circuit.
The amount of delay due to cable length can be detected without increasing the number of wires.

Furthermore, by forming the phase shift detection pulse superimposition circuit on the same semiconductor substrate as the solid-state image sensor, the phase shift detection pulse can be superimposed on the sensor output signal without increasing the mounting area of the camera head.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing a first embodiment of a head-separated camera according to the present invention, FIG. 2 is a circuit configuration diagram showing an example of the configuration of a pulse superimposition circuit for detecting a phase shift, and FIG. , a signal waveform diagram showing its operation, FIG. 4 is a circuit configuration diagram showing another example of the configuration of the pulse superimposition circuit for phase shift detection,
The figure is a signal waveform diagram showing its operation, and FIG. 6 is a block configuration diagram showing an example of the configuration of a phase compensation circuit and a process circuit.
FIG. 7 is a block diagram showing a second embodiment of the present invention;
FIG. 8 is a diagram showing an example of the configuration of a general head-separated camera, FIG. 9 is a diagram showing an example of the configuration of a solid-state image sensor used in the camera head, and FIG. 10 is a diagram showing an example of the configuration of a conventional head-separated camera. FIG. 3 is a diagram showing phase shift detection means. In the figure, 1 is a camera head, 2 is a solid-state image sensor,
3 is a sensor output line, 4 is a pulse superimposition circuit for phase shift detection, 5 is a CCU section, 6 is a 580 circuit, 7 is a process circuit,
Reference numeral 8 indicates a phase compensation circuit, and reference numeral 9 indicates a cable section. Patent applicant: Olympus Optical Industry Co., Ltd. r mlCMD light receiving section Figure 3 Figure 4 Figure 5 Horizontal image period Horizontal blanking period

Claims (1)

[Claims] 1. A head-separated camera in which a camera head section equipped with a solid-state image sensor and a camera control unit section equipped with a process circuit for processing an image pickup signal are separated via a cable section, The camera head section is provided with a pulse superimposition circuit for detecting a phase shift that superimposes a pulse on the image sensor output signal to detect a phase shift of the output signal of the image sensor due to the length of the cable section, and the camera control unit section includes a A head-separated camera characterized in that a phase compensation circuit is provided for sending a signal, which has undergone phase compensation for a delay due to a cable section, to the process circuit based on a phase shift detection pulse superimposed on the output signal. 2. The head-separated camera according to claim 1, wherein the pulse superimposition circuit for phase shift detection is formed on the same semiconductor substrate as a solid-state image sensor.