JPH04155692A - Row decoder circuit for semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce current consumption at the time of stand by altering ON, OFF of a transistor connected to a word line according to whether it is replaced with redundancy or not. CONSTITUTION:For example, ON, OFF of a transistor Q2 connected to a word line WLO is altered according to whether it is replaced with redundancy or not. When the line WLO is not replaced with the redundancy, the transistor Q2 is turned OFF when the decoder is activated to separate the line WLO from a ground level, and turned ON when it is not activated to suppress the line WLO to the ground level. When the line WLO is replaced with the redun dancy, it is turned ON at the time of activating to suppress the word line to the ground level, turned OFF at the time of stand-by to prevent the line WLO from floating and leaking.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a row decoder circuit for a semiconductor memory.

[Conventional technology]

Conventionally, in semiconductor memory, word lines or digit lines,
A method in which memory cells containing redundant (hereinafter referred to as redundancy) word lines and digit lines are arranged in advance to prevent yields from decreasing in the event of some kind of defect in a memory cell, and the defective words or digits are replaced. is taken.

FIG. 6 shows such a conventional example, and FIG. 7 is a timing diagram showing the operating state of the circuit shown in FIG. In Figure 7,
The solid line shows the waveform when replaced, and the broken line shows the waveform when not replaced.

6 and 7, a P-channel field effect transistor (hereinafter P
The source of MO3) - called transistor) Qm is connected to the power supply and the drain is connected to node NVI. Address signal φ1. φ2. Three channel field effect transistors (hereinafter referred to as NMO) with φ3 as their gate input
(referred to as S transistor) Ql4. Ql5. Qg6
is connected in series with transistor Q13.

That is, the drain of transistor QI4 is connected to node NVI, and the source of transistor Q14 is connected to node NVI.
5 train, transistor Q1. The source of transistor Qrb is connected to the drain of transistor Qrb, and the source of transistor Q16 is connected to ground level. When the decoder circuit of FIG. 3 is inactive, the control signal φP and the address signal φ.

φ2. At least one of φ3 is at low level, transistor Q13 is on, transistor Q14+Q
At least one of the 15+ Q lbs is off,
Node NVI is precharged to high level. When the control signal φP and the address signals φl and φ2゜φ all become high level, the transistor Q13 is turned off and the transistors Q14+Q15. Q16 turns on and pulls out the charge at node NVI and sets it to low level, thereby activating the decoder circuit shown in FIG. 3.
is the input of the inverter 11, and the node NV2, which is the output of the inverter 11, is connected to a plurality of N nodes whose gates are connected to the power supply.
Connected to the drain of the MOS transistor. Here, transistors Q9, Qto, Qll, Q
Four cases of l2 will be described, but this number is not limited. The source of transistor Q9 is connected to the gate of NMOS transistor Q1, and transistor Q1
The source of is connected to node NV5. The train of the transistor Q1 is connected to the word activation signal φRO, the second node NV5 is connected to the word line WLO, and the first node NV3 receives the low level of the node NVI via the inverter 11 transistor Q9 when the decoder is activated. It becomes a high level that is lower than the power supply by the threshold voltage VT (hereinafter abbreviated as VT) of the transistor Q9. After that, when the word activation signal φRQ goes to the high level of the power supply level, through the capacitance between the gate and drain of the transistor Q1,
The gate of transistor Q1 reaches a level higher than the power supply by more than 2V. Therefore, word &i, WLO rises to the power supply level.

In addition, node NV5 is an NMOS whose source is at ground level.
) is connected to the drain of the transistor Q2, and the inverted signal NV4 of the node NV2 by the inverter 2 is input to the gate of the transistor Q2. Therefore, the transistor Q2 is turned off when the decoder is activated, turned on when the decoder is deactivated, and holds the word line WLO at the ground level when it is not selected. Similarly, there are three refinement circuits made up of transistors Q9, Ql, and Q2, and word activation signals φR1+φR2+φλ3 are input to each of them, and word lines WLI, WL2, . WL3 is connected. Further, a node NV4 is connected to the gate of a transistor whose drain is connected to the word line and whose source is at ground level. The word activation signal φ□ is a signal that is decoded by the address signal and generated only once, and has a one-to-one correspondence with the word line included in the decoder, and is a signal that directly activates a word, but it is not redundant. If it has been replaced, it is inactivated by the redundancy address selection signal and the redundancy word is selected.

[Problem to be solved by the invention]

The conventional decoder circuit described above connects the drain to the word line W.
Transistor Q connected to Ln and whose source is at ground level
The same applies even if 2, Q4, Q6, and Qg are all turned on when the decoder is deactivated or are replaced with dundancy. Further, during standby, the bit line is supplied with 1/2 Vcc level from the precharge power supply. As a result of the above, if a defective word due to a short circuit between word II W L n and the bit line is replaced with redundancy, the precharge level of the bit line (level such as VcC/2) will change from the bit line precharge level (level such as VcC/2) to the bit line during standby. Connect the bit line and word line to the word line through the short circuit, and connect the drain from the word line to the word line.
A leakage current flows to the ground level through the floating prevention transistors Q2, Q4, Q6, and Qs whose sources are at the ground level, resulting in an increase in current consumption during standby.

SUMMARY OF THE INVENTION An object of the present invention is to provide a row decoder circuit for a semiconductor memory that solves the above-mentioned drawbacks and reduces current consumption during standby.

[Means to solve the problem]

The configuration of the row decoder circuit of the semiconductor memory of the present invention includes a first circuit that determines whether redundancy has been replaced and holds the determined output signal, and a first circuit that determines the output signal of the first circuit. , if the transistor whose one main pole is connected to the word line and the other main pole is at the ground level is not replaced with the redundancy, it should be replaced with the redundancy by turning on when the decoder is deactivated and turning off when the decoder is activated. For example, a second circuit is provided that is turned off during standby and turned on when active.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic diagram showing a row decoder circuit according to a first embodiment of the present invention, and FIG. 2 is a timing chart showing its operating waveforms.

1 and 2, this embodiment is a PMOS transistor Q2 whose source is connected to the power supply and whose drain is connected to the node NVI, with the precharge signal φP as the gate input signal.
5, and address signals φ1゜φ2. Three NMOS) transistors Q26. with φ3 as their respective gate input signals.
Q2 and Q28 are connected in series. That is, the drain of the transistor Q26 is connected to the node NVI, the source of the transistor Q26 is connected to the train of the transistor Q27, the source of the transistor Q27 is connected to the drain of the transistor Q28, and the transistor Q211 is connected to the drain of the transistor Q26.
The 8-node NVI, whose source is grounded, becomes the input of the inverter 1, and the output of the inverter 1 is connected to the node NV2. Furthermore, the node NV2 has NMOS transistors Q5, Q6, Q whose gates are connected to the power supply.
17. Qlg, and is connected to the drain of circuit blocks BLOCKI, BL○CK2. BLOCK3.
This is the input signal for the BLOCK4 circuit. The source and drain of transistor Q5 are connected to word activation signal φR.
NMOS with Q input and source connected to node NV5)
0 node NV5 connected to the gate of transistor Q
is connected to the word line WLO, which is connected to a train of NMOS transistors whose sources are at ground level and whose gates are connected to node NV4. Transistor Ql
, Q2, and Q5, a circuit similar to the circuit configured by
Transistor Qv, Q4. Qb and word line WLI,)
-Ran resistor Q +3. Q14. Q lf and word 1iWL2. ) Ransistor Q +5+ Q 161
Q1g and word line WL3. In addition, word activation signals φ81. φ8□
, φ milk 3 are similarly input. BLOCKI and BL
OCK3. BLOCK2 and BLOCK4 are similar circuits, so BLOCKI and BLOCK2 will be explained.

First, we will explain the configuration of BLOCKI.The output of the input Nantes circuit N1 which receives the input node NV2, the address signal T" and the redundancy address selection signal φD is connected to the contact NV13, and the node NV7 is an NMOS whose source is connected to the node NV8). The drain of the transistor and the train are connected to the node N
PMO8 connected to V8) Node NV8 connected to the source of the transistor is the input of inverter 3, and the output of inverter 3 is connected to node NV3. Furthermore, node NV3 is connected to inverter 2 and inverter 4.
The output of inverter 2 is connected to the gate of transistor Qll, and the output of inverter 4 is connected to node N8, which is connected to the gate of transistor Q12. Further, the node NV3 uses the one-shot signal φON at power-on as a gate input signal, and is connected to the drain of a transistor Q29 whose source is grounded, and the node NV3 serves as an output of BLOCKl.

Next, the configuration of BLOCK2 will be explained. Node NV3, which is the output of BLOCKl, is connected to the gate, and the source is connected to node N.
The train of the NMOS transistor connected to V4 and the source of a PMOS transistor Q8 whose gate is connected to the output of the inverter 5 whose input is the node NV3 and whose drain is connected to the node NV4 are connected, and the precharge is applied to the intermediate node. A signal φp is connected. Also, the output of the inverter I5 is used as the gate input, and the source is connected to the node NV4.The drain of the transistor Q9 and the node NV
3 as the gate input and the drain connected to the node NV4. A zero node NV4, to which the source of BLOCK2 is connected and the output of an inverter I6 whose input is node NV2 is connected to its intermediate node, serves as the output of BLOCK2 and is connected to the gates of transistors Q2 and Q4. BLOCK3JfBLOCK1<7) The input signal i just changed to φX, and BLOCK4 becomes BLO
It is exactly the same circuit as CK2.

Next, the operation will be explained using FIG. 2 as well. First is the one-shot signal φ that is generated when current is turned on. , the transistor Q29 is turned on and turned off after setting the node NV3 to a low level. That is, the output of BLOCKI is initially at a low level. Considering the case where the address corresponding to word 1liWLo is selected after the internal circuit initial state B setting operation after power-on is completed, precharge signal φP and address signals φl, φ2 . All of φ3 become high level, transistor Q25 turns off, transistor Q26゜Q2
71 Q2g are all turned on and the 0 node NVI which pulls the node NVI to the low level becomes a low level, so that the output node NV2 of the inverter 11 which receives the node NVI as an input becomes a high level, and the decoder is activated. The inputs of the three-man powered NAND N1 are all low level in the initial state, so the output node NV7 of the NAND N1 is initially high level.The low level of the zero node NV3 is the inverter I.
2 to turn on the NMO5) transistor Q1t and directly turn on the PMOS transistor Q12. Therefore, the level of node NV7 remains the same, and node NV8
It is in a state where it can be reported. If word 1 WLO is not replaced with redundancy in the activated state of the decoder, redundancy address selection signal φD is not generated, so even if node NV2 and address signal T1 become high level, the output NVI of NAND N1 remains at high level. The state of BLOCKI remains unchanged and the node NV3 remains at the low level. Depending on the level of WJ point NV3, transistor Q7. Q8 is off, transistors Q9, Q
to is turned on, the inverted signal of node NV2 is transmitted to node NV4, and transistors Q2 and Q4 are turned off. Further, the high level of the node NV2 is transmitted to the gates of the transistors Q1 and Q3 at a level lowered by 7 degrees by the transistors Qs and Q6. That is, the gate level of transistors Q1 and Q3 becomes VCC-V, and transistors Q1 and Q3 are turned on. In this state, the word activation signal φλ0 is generated and is booted up by the parasitic capacitance between the gate and drain of the transistor Q1, and the gate of the transistor Qt rises to a level equal to or higher than Vcc. Therefore WL
The level of word activation signal φλ0 is directly transmitted to WLO, and WLO rises to the Vcc level. When the decoder is inactivated, the address signal φ1. φ2. At least one of the signals φ3 is at a low level, and the precharge signal φP is at a low level or drops to a low level by -degrees and becomes a high level again. In any case, as the precharge signal φP becomes low level, the transistor Q
25 is turned on, and the address signal φ1. φ2. At least one of the transistors Q26.φ3 becomes low level, so that the transistors Q26. Q2g.

At least one of the transistors Q29 is turned off, and the node NVI is precharged and becomes high level.The 0 node NV1 becomes high level, so that the node NV2 becomes low level, and the transistors Ql and Q2 are turned off. Also, node NV2
As a result, the node NV4 becomes a high level and transistors Q2. Q4 turns on and word line WL
Assuming that the 0th order word line WLO with O and WLI at the ground level is redundantly replaced, when the decoder is activated, the node NVI becomes low level, the node NV2 becomes high level, and the transistor Qt.

The point where the gate of Q3 is at the VCCV level is the same as when it is not replaced by redundancy. but,
BLOCKI and BLOCK2 operate differently. Since the word line WLO has been replaced with redundancy, the redundancy address selection signal φD is generated, all inputs of the three-power NAND N1 become high level, and the output of the NAND N1, that is, the node NV7 changes from high level to low level. The level of one node NV7 is directly transmitted to the node NV8, and the inverter 3 sets the node NV3 to a high level. Furthermore, as the node NV3 becomes high level, the transistors Q1t and Q1□ are turned off and no longer receive the level of the node NV7. Further, the high level of the node NV3 is transmitted as a low level to the input of the inverter I3 by the inverter 4, and the high level of the node NV3 is latched. ′! ? Due to the high level of point i NV3, transistor Q7. Q8 is on, transistor Q9. Q
l.

turns off, node NV4, i.e. transistors Q2 and Q4
A precharge signal φP is input to the gate of. Therefore, transistor Q2. Q4 is turned off during standby and turned on when active. Word activation signal φλ
0 is the redundancy address selection signal φ. Deactivated by . Therefore, the word line WLO also does not go to high level.

According to the circuit operation described above, when the word line WLO is not replaced with redundancy, the transistor Q2 turns off when the decoder is activated, disconnecting the word line from the ground level, and when it is inactivated, it turns on and connects the word line. WL
Keep O to ground level. Also, word lI! When WLO is replaced with redundancy, it is turned on when active to suppress the word line WLO to the ground level, and turned off during standby to make the word floating and prevent leakage. In FIG. 2, solid lines indicate the case of substitution, and broken lines indicate the case of no substitution.

FIG. 3 is a circuit diagram of a second embodiment of the invention.

In FIG. 3, this embodiment realizes the operations of BLOCK2 and BLOCK4 in FIG. 1 using another circuit format. Other than these BLOCK2 and BLOCK4 circuits,
It is exactly the same as the circuit in Figure 1, and BLOCK2 and B
LOCK4tl'L Since it is a small circuit, here we use BLOCK.
2 will be illustrated and explained.

FIG. 4 is a timing diagram showing operating waveforms of the circuit of FIG. 3. Waveforms not shown in FIG. 4 are the same as those in FIG. 2, and therefore will be omitted.

The output of the inverter 5 whose input is the node NV2 and the output of the inverter 6 whose input is the output node NV6 of the judgment latch circuit BLOCK1 are input to the NAND N2, and the node NV6 and the precharge signal φP are the inputs of the NAND N3. It becomes.

The output of NAND N2 and the output of NAND N3 are respectively input to NAND N4, and the output NV7 of NAND N4 is connected to the transistor Q2. This is the gate input for Q4.

Similar to the previous embodiment, when the decoder is activated, WLO
BLOCKI if not replaced with redundancy
The output node NV6 of is low level, and the 0 node NV6 is
Since it is input to NAND N3 together with precharge signal φP and node NV6 is at low level, the output of NAND N3 becomes high level regardless of precharge signal φP. Further, the nodes NV2 and NV6 are connected to inverters I5. It is input to NAND N2 via I6,
Since the node NV2 is at a high level, the output of NAND2, which has the inverted signal of the node NV2 as an input, is at a high level. Furthermore, the outputs of NAND N2 and NAND N3 are both NAND N4
The output of NAND N4 is BLOCK.
2 output, and the transistor Q2. Connected to the gate of Q4. Since the outputs of NAND N2 and N3 are both high level, the output of NAND N4 becomes low level, and the transistor Q2. Q4 is turned off and the word lines WLO and W
Disconnect LI from ground level.

After that, the word line WLO is activated by the word activation signal φKO.
becomes high level. When the decoder is inactivated, the node NV2 becomes low level, so all the inputs of NAND N2 become high level, and the output of NAND N2 becomes low level. Therefore, the output of NAND N4, which receives the output of NAND N2 as input, becomes high level unconditionally, turns on transistors Q2 and Q4, and brings word lines WLO and WLI to the ground level. If WLO has been replaced with redundancy, the output node NV6 of BLOCKI becomes high level, making the output of NAND N2 unconditionally high level.

In addition, the node NV6 is input to the NAND N3 along with the precharge signal φP, and since the node NV6 is fixed at a high level, the output of the NAND N3 is controlled by the signal φP, and is at a high level during standby and a low level during active. Become. Furthermore, since the output of NAND N2 is also fixed at high level by node NV6, the output of NAND N4,
That is, the gates of transistors Q2 and Q4 are controlled by the output of NAND N3. Therefore, the output node N of NAND N4
V7 is low level during standby and high level when active, and transistors Q2. Q4 is turned on when active to suppress words 1iWLo and WLI to the ground level, and turned off during standby to keep the words floating to prevent leakage.

FIG. 5 is a circuit diagram showing a row decoder circuit according to a third embodiment of the present invention.

In FIG. 5, only the parts of this embodiment that are different from those in FIG. 1 are shown, and the circuit parts not shown are the same as those in FIG. 1.

In this embodiment, each word line WLO,
WLI, WL2. N0 between WL3 and ground level respectively.
M5) Transistor Q3s, Q32.

Q33. Q34 is connected, and a reverse phase signal φP of the precharge signal φp is input to the gate of each transistor. Therefore, transistors Q31°Q32.
Q33. Q34 is turned on during standby to prevent the word from floating, and turned off when active to isolate the word from ground level. Q34 has a very small size and a small current capacity.In this embodiment, when the word line is redundantly replaced, the word line is floating during standby in the first embodiment, but the capacity is changed to lJX. Small transistor Q3+, Q
gz, Q33. By placing Q34 in, there is an advantage that floating of words can be prevented and the same effect as in the first embodiment can be obtained.

In response to an increase in current consumption during standby due to a short circuit between a defective word line and a bit line that is replaced with redundancy, which is unavoidable in the conventional row decoder circuit described above, this embodiment replaces the word line of the selected address with redundancy. It has a circuit that determines and stores whether or not the word has been replaced with redundancy, and turns off the transistor that grounds the word when the decoder is inactivated during standby.

As explained above, the first to third embodiments are based on a first node, a first control signal, a first field effect in which the first control signal is used as a gate input, and a source is connected to a power source. a transistor, a second field effect transistor whose drain is connected to the first node, whose gate input is an address signal and whose source is grounded; a first inverter to which the first node is input; and a first inverter. a third field effect transistor with the output of the transistor connected to the drain, the gate connected to the power source, the second node connected to the source, and the third field effect transistor with the second node connected to the source;
a fourth field effect transistor having a control signal inputted to its drain, the source of the third field effect transistor connected to its gate, a first word line tangent to the second node, and a fourth field effect transistor connected to the gate thereof; Determine whether the circuit has been replaced with a redundant circuit.

a first circuit for storing data, and a drain connected to a second node;
It has a fifth field effect transistor whose source is at a common level, and a second circuit which has an output signal connected to the gate of the fifth field effect transistor and controls turning on and off of the fifth transistor.

〔Effect of the invention〕

As explained above, in the present invention, when a word line and a bit line are short-circuited and become defective, and there is a word line that has been replaced with redundancy, it is determined whether or not the word line has been replaced with redundancy, and the determination output is retained. The output signal of the circuit is
By connecting a defective word line to its drain, for example, and turning off a transistor whose source is, for example, at ground level, during standby, it is effective to reduce the steady current flowing through the short end of the defective word and defective bit line during standby.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a row decoder circuit of a semiconductor memory according to a first embodiment of the present invention, FIG. 2 is a timing diagram of the circuit of FIG. 1, and FIG. 4 is a timing diagram of the circuit in FIG. 3, FIG. 5 is a circuit diagram showing a part of the third embodiment of the present invention, and FIG. 6 is a circuit diagram showing a conventional example. FIG. 7 is a timing diagram of the circuit of FIG. In the figure, Q1 to Q34...field effect transistor, ■1
~Ill...Inverter, N1~N4...Nand,
φl~φX...address signal, WLO~WL3...
Word line, NVI to NV7...node.

Claims (1)

[Claims] a first circuit that determines whether the redundancy has been replaced and holds the determined output signal;
Determine the output signal of the circuit, and if the transistor whose one main pole is connected to the word line and the other main pole is at the ground level is not replaced with the redundancy described above, it is turned on when the decoder is deactivated and turned off when it is activated. and a second circuit that is turned off during standby and turned on when active if the redundancy has been replaced.