JPH04154314A - Output circuit - Google Patents

Abstract

PURPOSE:To reduce the fluctuation of through-rate by detecting a state of an output waveform, and stabilizing the output waveform in a certain prescribed inclination. CONSTITUTION:In the case an input terminal IN falls, since transistors P3, P5 turn on, a current I3 is nearly eliminated, and on the contrary, since a current I4 flows, when a load capacity CL increases, a fall time VOUT becomes later than that of Ve. Accordingly the output of a comparator 3 comes to a High level, the level of a nodal point (d) falls, and a current I2 increase. When the current I2 becomes higher, the current I4 increases, and a fall of an output OUT becomes larger. In such a way, when the load capacity CL increases, the output OUT and a nodal point (e) are compared by the comparator 3, and by increasing the current I4, a fluctuation rate is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an output circuit, and particularly to an output circuit using CMOS transistors made of semiconductor integrated circuits.

[Conventional technology]

In the conventional output circuit of this type, as shown in FIG. 3, the input signal IN is manually input to the level timing adjustment circuit 1.2, and the level timing IIM times! The output signal of #11 is connected to the gate of P-channel MO5 transistor P1, and the output signal of level timing adjustment circuit 2 is connected to the gate of N-channel MO5 transistor P1.
It was connected to the gate of the S transistor N1, the source of the transistor P1 was connected to the power supply VDD, the source of the transistor N1 was connected to the power supply SS, and the drains of the transistors PL and Nl were connected to the output OUT.

FIG. 4 is a circuit diagram showing a specific circuit configuration of the block diagram of FIG. 3.

In FIG. 4, the level timing adjustment circuit 1 of FIG.
As P-channel MOS transistor P2. P3. N
Channel MOS transistor N4. A bias BIASI is applied to the gate of the transistor N4. As the level timing adjustment circuit 2, a P channel MOS transistor P4. P5. N-channel MOS transistor N2. A bias BIAS2 is applied to the gate of the transistor P4.

[Problem to be solved by the invention]

In the conventional output circuit described above, as shown in FIG. 4, for example, the biases BIASI and BIAS2 were fixed at a certain potential, so the current 11.12 flowing through the transistor NI P4 was fixed. Also, capacitor C1
, C2 are also fixed at a certain capacitance value, the respective rise and fall times of nodes a and b are determined by the following equations.

Since dt is determined by times A and B, when the output OUT is rising, it is given by the following equation.

6"・1゛, ., 21 pieces 8.1) dt CL dv (1 Therefore, when the load capacitance CL becomes large, dt becomes small and the slew rate of the output OUT becomes small. Conversely, when the load capacitance CL becomes If it becomes smaller, the slew rate of the output OUT increases, and as shown in the conventional example shown in FIG. 6, there is a drawback that the slew rate varies greatly with respect to the load capacity.

SUMMARY OF THE INVENTION An object of the present invention is to provide an output circuit which solves the above-mentioned drawbacks and reduces fluctuations in slew rate with respect to load capacitance.

[Means to solve the problem]

The configuration of the output circuit of the present invention includes a slew rate reference waveform generation circuit, a first . Second level timing adjustment circuit, comparator, P-channel MOS transistor, N-channel MO
S) - transistor, an input signal is supplied to the slew rate reference waveform generation circuit, an output signal of the slew rate reference waveform generation circuit is supplied to the negative side of the comparator, and an output signal of the comparator is supplied to the first . a second level timing adjustment circuit, the output signal of the first level timing adjustment circuit is applied to the gate of the P channel MOS transistor, and the output signal of the second level timing adjustment circuit is applied to the gate of the N channel MOS transistor. Each is connected to the previous 5 P channels, N Chao, Le MO
5) - It is characterized by having runci and stars connected in series.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an output circuit according to an embodiment of the present invention.

In FIG. 1, the output circuit of this embodiment includes first and second level timing adjustment circuits 1.2.

Slew rate standard waveform generation circuit (reference circuit) 4
, operational amplifier (comparator) 3, and P-channel MO
It is configured to include an S transistor PL and an N channel MoS transistor N1.

FIG. 2 is a circuit diagram specifically showing the output circuit of the embodiment shown in FIG. 1.

In the second [21], input terminal IN, bias BIAS
IBIAS2. Output terminal OUT, inverter I N
V, comparator 3. P-channel MOS transistor P1. P2. P3. P, 4. P5P6. P7. P8. P
9. No. Yanel MoS transistor N1. N2. N3.
N4. N5. N6°N7. N8. N9. Phase correction capacitor C1゜(2, capacitor C3, capacitive load CL,
Nodes a, b, c, d, e, power supply VDD, VSS,
VCC and GND are shown.

As the slew rate reference waveform generation circuit 4, invert I
NV, transistor P8. P9. N8°N9. a first level timing adjustment circuit 1 having a capacitor C3;
is transistor P2. P3゜P6. N4. N5. N7
．． It has a capacitor C1. 2 level timing adjustment circuit 2 includes transistors P4. P5. P7. N2. N3
．． N6. It has a capacitor C2.

Now, the transistor P of the slew rate reference waveform generation circuit 4
8. Bias BIASI connected to the gate of N8
, BIAS2 to a certain potential, transistors P8. @, which flows to N8, controls the flow 17, 1B,
Furthermore, by setting the capacitor C3 to a certain capacitance value, the rise and fall of the output at node e are determined by the following equation.

dt　　　C.

dt C3 Next, the operation will be explained using FIGS. 2 and 5.

In FIG. 5, the dotted line indicates a state of change from the solid line.

When input terminal IN falls, transistor P3.
Since P5 turns ON, the level of node a is VDD IV
The potential becomes tpl. Further, the current (3) at the node almost disappears, and conversely, the current (L dt ) of the current (7X I4) becomes slower), and the fall time of Vout becomes slower than in (2). Therefore, the output of the comparator 3 becomes High level. From this, the level of node d decreases, and the current I2
The level of the 0 node that increases is d t C2 d. When the current 4 increases, the output OUT falls t.In other words, when the input terminal IN falls, the load capacitance C
As L increases, the output OUT and the node e are compared by the comparator 3 (I4 is constant), and the fluctuation rate of this embodiment becomes smaller than the conventional fluctuation rate. Load capacity C
The same applies when L is small.

Further, the same thing as above can be said when the input terminal IN rises.

Next, in this example, Vcc=5 V, VDD=
9V.

Under the conditions of Vss=9V, GND=OV, load capacitance C
Examples of simulation results when L is changed from 10 μpF to 2500 pF are shown.

When performing a simulation with a conventional output circuit, CL=
At 10pF, worst case is 9.7 V/μs, CL=250
At 0 pF, the worst slew rate value was 5.7 V/μs. The maximum fluctuation rate for the center 7.6μs is 3
It was 3.3%. However, when a simulation is performed using the output circuit of this embodiment under the same conditions, the worst case is 9. OV/μs.

Is it worst when CL = 2500pF? A slew rate value of , OV/μs was obtained. The maximum fluctuation rate for the center 7.6 V/μS was 18.4%. Therefore, it can be said that the output circuit of this embodiment has an improvement of 14.9% compared to the conventional one.

In addition, in Fig. 5, when the output OUT is falling,
In the output OUT, the solid line has a higher level than the node e, the 0 node a has almost no change, and the 1 node is conventionally constant. In the case of falling, the solid line is lower than node e and the bell is 0.
Conventionally, wJ point a is a constant one node and hardly changes.

As shown in the waveform of this embodiment in FIG. 6, even if the load capacity becomes large, the output waveform remains "accented" [Effects of the Invention] As explained above, the output port r according to the present invention has the following characteristics: Even if a large load capacity is attached to the output, by detecting the state of the output waveform, the output waveform can be stabilized at a certain slope and fluctuations in the slew rate can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an output circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific circuit of FIG. 1, FIG. 3 is a block diagram showing a conventional output circuit, and FIG. 4 is a circuit diagram showing the specific circuit in Figure 3, and Figures 5 and 6 are both circuit diagrams showing the specific circuit in Figure 1.
FIG. 3 is a timing chart showing operation waveforms of the illustrated embodiment and the conventional example. PL, P2. P3. P4. P5, P6. P7゜P8. P
9.--P channel MO5) - transistor, Nl, N2
．． N3. N4. N5. N6. N7°N8. N9...N
Channel MOS transistor. [Ki C1, C2, C3 - Capacitors a, b, c. d, e---node, BIASI, BIAS2. ,, bias, CL...load capacitance, INV・-inverter, 3
.... Comparator, IN...input terminal, OUT...output terminal, VDD, VSS, VCC, GND...power supply.

Claims (1)

[Claims] The slew rate reference waveform generation circuit includes a slew rate reference waveform generation circuit, first and second level timing adjustment circuits, a comparator, a P-channel MOS transistor, and an N-channel MOS transistor. The output signal of the generation circuit is sent to the negative side of the comparator, the output signal of the comparator is sent to the first and second level timing adjustment circuits, and the output signal of the comparator is sent to the first and second level timing adjustment circuits.
The output signal of the second level timing adjustment circuit is connected to the gate of the P channel MOS transistor, and the output signal of the second level timing adjustment circuit is connected to the gate of the N channel MOS transistor. An output circuit characterized by connecting in series.