JPH04153977A - semiconductor memory - Google Patents

Abstract

PURPOSE:To enable high density and high S/N by connecting dummy cells to a word line, providing a signal conversion means on each data line and dummy data line, and inputting/detecting the output of the signal conversion means of the dummy data line common with the output of the signal conversion means on a differential signal detection means provided on each data line. CONSTITUTION:Signal current Is and reference signal current ir flow an earth electric potential through respective current voltage conversion circuits LD1 to LDn, and LDd according to the signal from memory cells MC11 to MCmn read out on data lines d1 to dn and a dummy data line dd. These signals are converted again into a voltage signal and inputted to respective differential signal detection means SA1 to SAn. A voltage signal vs is inputted to one of the input terminals of each differential signal detection means SA. The output of a current voltage conversion circuit LDd provided on the dummy data line is commonly inputted to the other input terminal of the differential signal detec tion means SA1 to SAn, and respective differential signal detection means SA1 to SAn discriminate and detect voltage signals while utilizing a reference voltage signal vr. Thus, the high density and high S/N are realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and particularly to a semiconductor memory that has a high S/N ratio and is suitable for high integration.

[Conventional technology]

In recent years, semiconductor memories have been increasingly integrated, and in particular semiconductor memories consisting of one transistor and one capacitor memory cell have a high degree of integration because the number of elements constituting a memory cell is small. The memory array configuration of this highly integrated semiconductor memory is described in IE, Proceedings Part I, Vol. 130, 3 (1
June 1983) pages 127 to 135 (IEEE P
roceedings Part I.

vol, 130. no, 3. pp, 127-135
(June 1983)),
There are two main configurations. One is a folded data line method, and the other is an open data line method.
It is a method. In the folded data line method, paired data lines, that is, a data line from which a signal is read from a memory cell and a data line from which a reference signal is read, are placed close to each other. Noise can be canceled by the paired data lines, minute signals from memory cells can be read out with a high S/N ratio, and stable operation is possible. On the other hand, in the open data line method, the paired data lines sandwich the amplifier (sense amplifier) and belong to different memory arrays.
It is difficult to cancel the noise generated in the memory array using the paired data lines, and this method is inferior to the above-mentioned folded data line method in terms of S/N ratio. However, in the open data line system, a so-called one-intersection device in which memory cells are always arranged at the intersections of data lines and word lines is possible, and the density of memory cells can be increased. For example, 1986 IEE International Solid State Circuits Conference, Digest of Technical Papers, pp. 268-269 (1986 IEE
E l5SCCDig-est of Technic
al Papers.

A memory cell such as the one described in JP, pp. 268-269) can be made to have a high density because the memory cell is arranged in a groove shape at the intersection of a word line and a data line.

[Problem to be solved by the invention]

In this way, the folded data line method is superior in terms of S/N, but it is inferior in terms of high memory cell density because memory cells can only be placed at one of the intersections of the word line and the data pair line. . On the other hand, in the open data line system, 1
Although intersection point arrangement is possible, it is inferior in terms of S/N. As a solution to these problems, the special public Sho 5g-1871
5, but it was impossible to realize it using a one-transistor, one-capacitor memory cell.

The present invention has been made to solve these conventional problems. In other words, an object of the present invention is to use a 1-transistor, 1-capacitor memory cell to enable a single intersection arrangement that increases the density of memory cells, and to achieve a high S/N equivalent to that of the folded data line system. An object of the present invention is to provide a method for configuring a memory array.

[Means to solve the problem]

The above purpose is to provide a plurality of word lines, a plurality of data lines arranged to intersect with these, a plurality of memory cells provided at arbitrary intersections of the plurality of word lines and the plurality of data lines, and A dummy data line to which a plurality of dummy cells for generating signals are connected is provided in common to the plurality of data lines, the dummy cell is connected to a word line to which the same signal as the memory cell is applied, and each data A signal conversion means is provided on the line and the dummy data line, and the output of the signal conversion means and the output of the signal conversion means of the dummy data line provided in common are input to the differential signal detection means provided on each data line and detected. This is achieved by

[Effect]

Signals are simultaneously read from a plurality of memory cells connected to one selected word line onto each data line, and reference signals are read from dummy cells onto the dummy data line. The signal read out onto each data line is input to a signal conversion means provided on each data line, and an output signal corresponding to the signal read out onto the data line is obtained. Similarly, the reference signal read onto the dummy data line is input to a signal conversion means provided on the dummy data line, and an output signal corresponding to the reference signal read onto the dummy data line is obtained. Thereafter, the output signal of the signal conversion means obtained for each data line is input to the differential signal detection means provided on each data line, and the output signal of the signal conversion means connected to the dummy data line is input to the differential signal detection means provided for each data line. It is commonly input to the differential signal detection means provided on the line. Then, the differential signal detection means detects the signals from the memory cells using a commonly input reference signal. By doing so, it is possible to detect the signal from the memory cell read out onto the data line using the reference signal read out onto the dummy data line provided in common to a plurality of data lines. That is, a pair of data lines, that is, a data line from which a reference signal is read, which was conventionally provided for each data line, can be provided in common for a plurality of data lines. Therefore, memory cells can be arranged at each intersection of a word line and a data line, that is, a single intersection arrangement, and the density of memory cells can be increased. Furthermore, by connecting a dummy cell connected to a commonly provided dummy data line to a word line to which the same signal as the memory cell is applied, it becomes possible to cancel out noise on the data line and the dummy data line. A high S/N ratio equivalent to that of the folded data line system can be achieved. Therefore, a highly integrated semiconductor memory with a high S/N ratio can be realized.

〔Example〕

The present invention will be explained below with reference to examples.

FIG. 1 shows a first embodiment of the present invention, and shows a memory array configuration of a semiconductor memory according to the present invention.
C,~MC,,) are word lines W1~W and data line d.
They are arranged in a matrix at the intersections of d and d. Further, apart from the data line to which memory cells are connected, a data line to which only dummy cells (DC1 to DC,) are connected, that is, dummy data @dd, is provided in common for a plurality of data. The dummy cell is connected to the same word line as the memory cell. Here, the dummy data line is for reading a reference signal when detecting the signal from the memory cell read to the data line, as will be described later, and is used to cancel noise during the read operation. , it is necessary to configure the electrical characteristics such as parasitic capacitance value to be balanced with the data line. In addition, the dummy cell is Tl I I stored in the memory cell.
A device is used that outputs to the dummy data line approximately the intermediate level of both voltages on the data line when the information at t 910 j+ is read from the memory cell. A specific example of the configuration of the dummy data line and dummy cell will be described later.

TR (TR, ~TRn, TRd) is a signal conversion means.

It is provided for each data line and dummy data line.

The signal conversion means TR (TR, ~TR, TR,) is a voltage-current conversion circuit SW2 (SV40-8W2..5W2d)
and current-voltage conversion circuit LD (LD, ~LDn, LD,)
Here is an example configured with: The voltage-current conversion circuit SW2 shows an example in which two MOS transistors are connected in series, and the control signal RG of the voltage-current conversion circuit 5112 is applied to the gate of one MOS transistor. A data line or a dummy data line is connected to the gate of the other MOS transistor. Current voltage conversion circuit LD
has the function of converting the current signal that is the output of the voltage-current conversion circuit SW2 into a voltage signal, and has the function of converting the current signal that is the output of the voltage-current conversion circuit SW2 into a voltage signal, and has the function of converting the current signal, which is the output of the voltage-current conversion circuit SW2, into a voltage signal.
It can be configured with an OS transistor. This signal conversion means can separate the parasitic capacitance of the data line or dummy data line from the parasitic capacitance of the differential signal detection means, which will be explained next, even if the capacitance of the one-transistor, one-capacitor memory is reduced. High S/N ratio can be obtained 1) SA (SA, ~SA,) is a differential signal detection means, which is provided on each of the data lines d, ~d, and one of the input terminals of the differential signal is It is connected to the output terminal of the signal conversion means TR (TR1 to TR, . . . ) provided for each data line.

The other input terminal is connected to the output terminal of the signal conversion means TRa provided on the dummy data line dd via the common reference signal line Cr. sww (sn1 to SWW,) is a signal transmission means for rewriting information to the memory cell using the detection result of the differential signal detection means SA;
dn, and is controlled by a control signal WG. Here, the signal transmission means S W W a provided on the dummy data line dd is provided to balance the electrical characteristics of the dummy data line and the data line.

The read operation in this embodiment will be explained below with reference to FIG. First, each data line d, -dn and dummy data line dd are precharged to a certain potential Vp.

The precharging method will be described later. Then one word line,
For example, Wl is selected, so that read signals simultaneously appear on each of the data @d~dn from the memory cells connected to this word line. At the same time, a reference signal is read from a dummy cell connected to this word line to a dummy data line dd. This reference signal is stored in the memory cell.
71 and 41 Q It is set to approximately the intermediate level between the two voltages on the data line when the information is read from the memory cell. The signals and reference signals read out to each data line and dummy data line in this way are transferred to each signal conversion means T.
R(T R, - T Rn, T RJ. Then, when the control signal RG of each voltage-current conversion circuit gsW2 is set to a high potential, the voltage-current conversion circuit SW2 is operated. As a result, the data line or dummy data According to the signal from the memory cell read out on the line or the reference signal, each current-voltage conversion circuit LD (LD1-LDo, LDd) to voltage-current conversion circuit 5W2 (SW21-5W2n, 5W2d)
A signal current i8 or a reference signal current lr flows to the ground potential via. Here, signal current is or reference signal current 1. Since the current value is determined according to the voltage signal read onto the data line or dummy data line, the voltage signal is converted into a current signal. The signals from the memory cells and the reference signals converted into current signals in this way are converted into voltage signals again by each current-voltage conversion circuit LD (LD, ~LDn, LD,), and each differential signal detection means 5A
(SA1 to SA,) are input. At this time, the voltage signal v5 obtained for each data line is
is input to one of the input terminals. Further, the output of the current-voltage conversion circuit LDd provided on the dummy data line, that is, the reference voltage signal V, is connected to the other input terminal of the differential signal detection means SA (SA~5An) via the common reference signal 1icr. are commonly input. Each differential signal detection means SA
(SA1 to SA5An) use the commonly input reference voltage signal Vr in this way to discriminate and detect the voltage signals obtained from each data line.

Next, in a one-transistor, one-capacitor memory cell, reading out stored information is destructive and requires rewriting.

Therefore, the memory cells are rewritten based on the detection results of the differential signal detection means SA. In other words, the signal transmission means sww
(SWW, ~5WWn) are rendered conductive by control signal WG, and rewrite information is transmitted to each data line. As a result, rewrite information is written into the memory cells, and the word line is brought into a non-selected state, thereby completing the rewrite to each memory cell.

As described above, according to this embodiment, a signal from a memory cell read out to a data line can be detected using a reference signal read out to a dummy data line provided in common to a plurality of data lines. can. That is, a pair of data lines, that is, a data line from which a reference signal is read, which was conventionally provided for each data line, can be provided in common for a plurality of data lines.

Therefore, memory cells can be arranged at each intersection of a word line and a data line, that is, a single intersection arrangement, and the density of memory cells can be increased. In addition, by connecting the data line and dummy data line to the differential signal detection means through a signal conversion means, the parasitic capacitance of the data line or dummy data line and the parasitic capacitance of the differential signal detection means are separated. This makes it possible to obtain a high signal-to-noise ratio even if the capacitor capacity of the memory cell is reduced, thereby further increasing the density of the memory cell. Further, since the parasitic capacitance is separated by the signal conversion means, even if the dummy data line is provided in common to a plurality of data lines, the electrical characteristics such as the parasitic capacitance of the data line and the dummy data line can be maintained in balance. In addition, noise on the data line and dummy data line can be canceled by connecting a dummy cell connected to a commonly provided dummy data line to a word line to which the same signal as the memory cell is applied. becomes possible.

Therefore, it is possible to realize a continuous output operation with a high S/N ratio equivalent to that of the folded data line system. From the above, this embodiment makes it possible to realize a high S/N and highly integrated semiconductor memory.

FIG. 3 shows a second embodiment of the present invention, in which memory cells MC, dummy cells DC,
Data line d, dummy data line dd, voltage-current conversion circuit S
This is an example in which a block BLK is formed by W2 and the signal transmission means SWW, and a differential signal detection means SA and a current-voltage conversion circuit LD are provided in common to a plurality of blocks. The figure shows a case in which it is provided in common to two blocks (BLK-BLKr). One block BLK includes a plurality of memory cell blocks MCA (MCA1, 1 to MCA, , n, etc.) including memory cells MC, data lines d, voltage-current conversion circuit SW2, and signal transmission means SWW;
The dummy cell block DCA includes a dummy cell DC, a dummy data line dd, a voltage-current conversion circuit 5W2d, and a signal transmission means 5Wa.

The read operation of the embodiment shown in FIG. 3 is as follows. First, one of the multiple word lines.

For example, a word line W in memory cell blocks MCA, .
A read signal appears simultaneously on each data line (d, z, etc.) in □ to MCA□, n. At the same time, a reference signal is read from the dummy cell connected to this word line to the dummy data line dd□ in the dummy cell block DCA□. The signals and reference signals read to each data line and dummy data line in this way are transmitted to the voltage-current conversion circuit SW2 or 5W2d in each memory cell block or dummy cell block.
is input. After that, voltage-current conversion circuits SW2 and S
When the control signal RG of V/2 m is set to a high potential, each current-voltage conversion circuit LD (LD1 to LDn , LD4) to the ground potential via the common data line cd (cd, ~cd-) and the voltage-current conversion circuit SW2 or the common dummy data line cdd and the voltage-current conversion circuit SW2m.
s or reference signal current i r flows. These currents flow through each current-voltage conversion circuit LD (LD□ to LDn).

LDa) converts the signal into a voltage signal again and inputs it to each differential signal detection means SA (SA~SA,).

At this time, as explained in FIG. 1, the voltage signal v5 obtained for each data line is inputted to one of the input terminals of each differential signal detection means SA, and the reference voltage signal obtained from the dummy data line V, is commonly input to the other input terminal of the differential signal detection means 5A (SA1 to SAI,) via the common reference signal line Cr, and detects the signal. Next, the memory cells are rewritten based on the detection results of the differential signal detection means SA. At this time, the voltage-current conversion circuit SW2 and each current-voltage conversion circuit LD (LD, ~LDn, LDa
) is inactive. The rewrite information output from the differential signal detection means SA is sent to the write signal transmission means 5WD.
(SWD, ~5WDn) is transmitted to the common data line cd (cd1 to cdn), and further transmitted to the signal transmission means SWW in the memory cell block. The signal transmission means SWW is rendered conductive by the control signal WG, and transmits rewrite information to each data line. As a result, rewrite information is written into the memory cells, and the word line is brought into a non-selected state, thereby completing the rewrite to each memory cell.

In this embodiment, in addition to the effects described in FIG. 1, since the differential signal detection means and the current-voltage conversion circuit can be shared by a plurality of memory cell blocks, the relative area occupied by these can be reduced. Further, in this embodiment, since the data line and the common data line are connected through the voltage-current conversion circuit, these parasitic capacitances can be completely separated when reading signals. In other words, even if a common data line is provided to share the differential signal detection means and the current-voltage conversion circuit, the signal voltage read from the memory cell on the data line is not affected by the parasitic capacitance of the common data line, and the high S /N reading is possible. Since the common data line is provided, there is a concern about noise due to coupling capacitance between the common data line and the data line, but this does not pose a particular problem since the voltage fluctuation of the common data line during the read operation is small.

FIG. 4 shows a third embodiment of the present invention, in which a dummy cell block O provided in common to a plurality of memory cell blocks MCA is shown.
An example in which CA is arranged between a plurality of memory cell blocks is shown. With this configuration, the current-voltage conversion circuit L D m connected to the common dummy data line cdd is connected to the differential signal detection means SA (in the figure S
Ai or 5An), and the length of the common reference signal #Ier between them can be halved compared to the embodiment shown in FIG. Therefore, current-voltage conversion circuit LDd
The parasitic resistance and parasitic capacitance from to the differential signal detection means SA can be halved, and the time required for the reference signal output from the current-voltage conversion circuit LDi to be input to the differential signal detection means SA can be reduced. . In other words, the speed of the read operation can be increased.

The operation can be performed in the same manner as the embodiment shown in FIG.

FIG. 5 shows a fourth embodiment of the present invention, in which the differential signal detection means S
An example is shown in which A is arranged alternately at both ends of the common data line cd, and the layout pitch of the differential signal detection means SA is relaxed.

Since the differential signal detection means SA is arranged at both ends of the common data line cd, the dummy cell block DCA (
It is necessary to output reference signals from DCA1 to OCA, ) to both ends. Therefore, in this embodiment, current-voltage conversion circuits LDd□ and LDa are connected to both ends of the common dummy data line cdd.
2 is provided, and the reference signal current 1r converted in the dummy cell block DCA is connected to a current-voltage conversion circuit L D di,
The reference voltage signal V is distributed equally to both of the LDd2 and outputted to common reference signal lines cr1) and Cr2 provided at both ends. For this reason, current-voltage conversion circuits LDd□, LDd
2 is a current value half of the reference signal current ir, that is, ir/
A current-voltage conversion circuit LD (LD
The conversion coefficient from a current value to a voltage value is set to be twice as compared to LDn). For example, if the current-voltage conversion circuit is configured with a resistor, this can be done by doubling the resistance value. Also, the current voltage conversion circuit is MOS)
- When configured with transistors, the channel width is 172
This is possible by making According to this embodiment, the layout pitch of the differential signal detection means and the current-voltage conversion circuit can be relaxed, so that the layout thereof can be facilitated.

FIG. 6 shows a fifth embodiment of the present invention, in which, like the embodiment shown in FIG. A circuit LD is provided, and a plurality of data lines d (sixth
In the figure, one voltage-current conversion circuit SW2 and one signal transmission means SWW are provided in common for four data lines dα to dδ. For this purpose, each data line and voltage-current conversion circuit S
Switch means S connects W2 and signal transmission means SWW.
This is done via W. Similarly, in the dummy cell block DCA, a plurality of dummy data lines dd (dd
α to ddδ) have a common voltage-current conversion circuit SW2. and a signal transmission means 5WWi, and each dummy data line dd is connected to the voltage-current conversion circuit 5W2d and the signal transmission means 5WWa via a switch means SWa. In this way, by making the configuration of the dummy cell block DCA the same as that of the memory cell block MCA, these electrical characteristics can be balanced.

Furthermore, in the embodiment shown in FIG. 6, an example is shown in which the differential signal detection means SA and the current-voltage conversion circuit LD, which were not specifically shown in the previous embodiments, are constructed from CMO5.

In the embodiment shown in FIG. 6, a plurality of memory cell signals read out simultaneously to a plurality of data lines in a memory cell block by a selection operation of one word line can be read at one time by selecting a switch means SW. The operation of this embodiment will be described using FIG. 7, which is an example in which a memory cell signal is inputted to the voltage-current conversion circuit SW2 in series, and its output is inputted to the differential signal detection means to detect the memory cell signal in time series. I will explain. Here, an example will be described in which a high potential is stored in each memory cell. First, signals PCD and signals GC1α to QC δ are set to a high potential, and data lines dα to dδ and dummy data lines ddα to ddδ are set to a certain potential Vp (here, V c.
c/2.

Vcc is the power supply voltage).

In addition, the signal FL is set to a high potential, and the common data line cd and the common dummy data line cdd are set in advance to the current-voltage conversion circuit LD=L.
Keep it at a constant voltage determined by D4. Furthermore, the signal PCI is set to a low potential, and the nodes a and b in the differential signal detection means SA are precharged to Vcc. In this way, common data line cd, common dummy data li c d
By setting d to a constant voltage in advance, the memory cell signal and the dummy cell signal can be read out faster than when the voltage is not set to a constant voltage. In this situation,
When one word line, for example, W, is selected, a memory cell signal is transmitted from the memory cell MC connected to it to each data line dα to dδ, and from a dummy cell DC to each dummy data line d.
Reference signals are read out from dα to ddδ. At this time, the signal GC device α that controls the switch means SW (or 5Wd)
~GC engineering δ.

If only one signal (GC□α in the figure) is set to a high potential and the remaining signals are set to a low potential in advance, only the signal read to the data line dα out of the memory cell signals read to the data line will be The signal is transmitted to the voltage-current conversion circuit SW2. Memory cell signals read onto the remaining data lines are held on the data lines. Similarly, among the reference signals read out to the dummy data line, only the reference signal read out to the dummy data line ddα goes to the voltage-current conversion circuit SW2. and the remaining dummy data
The reference signal on the data line is held on the dummy data line. Next, when the signal RG circuit is set to a high potential, the voltage-current conversion circuit S
W2 operates, and a current flows from the current-voltage conversion circuit LD to the ground potential via the voltage-current conversion circuit SW2. This current has a voltage value applied to the gate of the MOS transistor constituting the voltage-current conversion circuit SW2, that is, a current value corresponding to the memory cell signal input to the voltage-current conversion circuit SW2. Furthermore, since this current flows through the MOS transistors constituting the current-voltage conversion circuit LD, its source potential, that is, the potential of the common data line cd, changes in accordance with the flowing current value, and is converted into a voltage signal by the differential signal detection means SA. is input.

In this way, the memory cell signal read to the data line dα is converted into a current signal by the voltage-current conversion circuit SW2, and this current signal is further converted into a voltage signal by the current-voltage conversion circuit LD, and then sent to the differential signal detection means SA. is input. Similarly, the reference signal read to the dummy data line ddα is converted into a current signal by the voltage-current conversion circuit 5w2i, further converted into a voltage signal by the current-voltage conversion circuit LD-, and inputted to the differential signal detection means SA. Ru. Thereafter, when the signal RD is set to a high potential, the potential difference between the potentials of the nodes a and b in the differential signal detecting means SA is determined according to the difference between the signal from the memory cell input to the differential signal detecting means SA and the reference signal. occurs. and signal R
When D is set to a low potential and signal C3N is set to a high potential, the potential difference is amplified and the signal from the memory cell can be detected.

At this time, if a high potential is stored in the memory cell, the node a becomes a high potential and the node b becomes a low potential.

Next, rewrite information is written to the data line using the result detected by the differential signal detection means SA. First, the signal RG and the signal FL are set to low potential in advance, and the common data line cd
Prevent unnecessary current from flowing when rewriting information is transmitted to the device. Then, the signal WD is set to a high potential, and the amplified signal at node b is transferred to the common data line c through the inverter.
to communicate.

Further, the signal WG is set to a high potential, and rewrite information is written to the data line dα via the signal transmission means SWW and the switch means SW. Then, when the signal GC1α is set to a low potential, the rewritten information is held in the data line dα.

As described above, after detecting the memory cell signal read onto the data line dα and writing rewrite information onto the data line dα, a memory cell signal on another data line is then detected.

The method is similar to the signal on the data line dα.

That is, the signal GC1β is set to a high potential, and the data, ma
The memory cell signal on dβ is input to the voltage-current conversion circuit SW2, and at the same time, the reference signal on the dummy data line ddp is input to the voltage-current conversion circuit SW2m. Thereafter, the same operation as when detecting the signal on the data line dα is performed to detect the signal on the data line dβ and write rewrite information to the data line dβ. By repeating this operation, the data line dα
Detect all signals on ~dδ and write rewrite information to the data line. Finally, by setting the word line to a non-selected state, rewrite information is stored in each memory cell, and the read operation is completed.

Further, in order to transfer the information read from each memory cell to the outside of the chip, the information is extracted when the information is detected by the differential signal detection means SA. As a method, 1, for example, the 6th
As shown in the illustrated embodiment, the nodes a and b in the differential signal detection means SA are connected to the output signal Y (
Switch YG whose on/off is controlled by
(YG Inato), the input/output pair I10. I10
This can be done by connecting to. After the signal from the memory cell transmitted to nodes a and b in the differential signal detection means SA is sufficiently amplified, the output signal Y of the decoder is set to a high potential, and the switch YGn is turned on to connect the five output pairs. I10. The information is transmitted to I10. The information is read out of the chip via the output circuit. On the other hand, writing from outside the chip is performed on the input/output pair I10. This can be done by writing the write information transmitted to I10 to nodes a and b in differential signal detection means SA via switch YG.

Although FIG. 6 only shows one column of memory cell blocks, a plurality of columns of memory cell blocks are provided as in FIG. 3. Memory cell signals are simultaneously read out to the data lines in these memory cell blocks, and detected using a reference signal from a dummy cell block OCA provided in common to the memory cell blocks of the plurality of columns.

Now, although the method of configuring the dummy data lines and dummy cells has not been specifically described so far, a method of configuring the dummy data lines and dummy cells suitable for this embodiment will now be described. As mentioned in Figure 1, the dummy data line is
It is necessary to configure the electrical characteristics such as parasitic capacitance value to be balanced with the data line. Further, a dummy cell is required that outputs to the dummy data line approximately the intermediate level between the two types of voltages on the data line when the information of llj+ and tlQT'' stored in the memory cell is read out from the memory cell. One way to achieve this is to use the same dummy cell as the memory cell, and connect the terminals in the dummy cell to KL I IIIt OII in the memory cell.
There is a method of storing a voltage that is an intermediate value for the information. This method will be explained in more detail using FIG. 6.

In FIG. 6, the dummy cell DC is constructed of the same cell as the memory cell MC. Then, in advance, store in the terminal in the dummy cell an intermediate voltage of the information IL lu tL O1'', that is, Vcc / 2, where the high potential in the memory cell is Vcc and the low potential is Ov. (For this method, (described later).If you select a word line in this state,
A voltage corresponding to the information "1" 71 Q n is outputted to the data line as a memory cell signal, and a voltage approximately in the middle thereof is outputted to the dummy data line as a reference signal. Thereafter, a read operation is performed as described above. First, a signal on one data line dα is detected, and the result is written to data vAdα as rewrite information. At this time, the reference signal voltage Vr (=Vcc/2) is simultaneously written to the dummy data line ddα by the MOS transistor Q1 via the common dummy data line cdd and the signal transmission means 5WWd. Similarly, when writing rewrite information to other data lines, a reference signal voltage is written to the dummy data line at the same time. After repeating this operation for all data lines, when the word line is made unselected, voltages corresponding to the information "1" and "O" are stored in the memory cells, and Vcc/2 is stored in the dummy cells. It turns out.

In this way, if the same dummy cell as the memory cell is used, the dummy data line has the same structure as the data line, and the electrical characteristics can be balanced with the data line. In addition, since the intermediate voltage of information "1" 071 is stored in the terminal in the dummy cell, when the word line is selected, the information tz output to the data line is stored in the dummy data line.
It is possible to output an intermediate level of the voltage of IF+110 II. Furthermore, in this method, after the intermediate voltage stored in the dummy cell is written at the same time as information is written into the memory cell, it is left as it is until the next selection.

That is, like the high-potential information stored in the memory cell, the information attenuates over time due to leakage current. Therefore, the relative vertical relationship between the information on the high potential side in the memory cell and the information in the dummy cell is determined by conventional dummy cell construction methods, such as the 1980 International Solid State Circuits Conference, International Solid State Circuits Conference, Digest of Technical Papers, pages 234-235 (1980 IEEE
ISSCCDigest of Technical
Compared to the method described in Paper S, pp. 234-235, in which a circuit is added to the dummy cell to set the terminal within the dummy cell to a desired potential, and the potential is fixed at that potential during the precharge period, etc. , retained for a long time. In other words, it is possible to lengthen the time until information on the high potential side is attenuated and erroneously determined as information on the low potential side, that is, the data retention time. This means that the time interval at which memory cells are refreshed can be lengthened, and the time that the semiconductor memory is performing refresh operations can be shortened for the system, and conversely, the time that the semiconductor memory can be used can be lengthened. This also reduces the power consumption required for refreshing, which has the advantage of extending the battery life when backing up the semiconductor memory with a battery.

Note that various ways of configuring the dummy data lines and dummy cells can be considered in addition to this method. For example, as mentioned in the main prayer example,
In the method of precharging the data line to Vcc/2, the precharge voltage can be used as a reference signal. Therefore, a dummy cell having the same shape as a memory cell is used, but the transistor of the tummy cell may be configured not to be turned on even when a word line is selected. This can be achieved by increasing the threshold voltage of the transistor, for example, by implanting ions into the channel portion of the transistor of the dummy cell, or by partially increasing the thickness of the gate oxide film of the transistor. This method also allows the electrical characteristics of the dummy data line and the data line to be balanced. Further, although this method complicates the process steps, it is not necessary to set the terminals in the dummy cell to an intermediate voltage as in the method described above, so the operation can be easily controlled.

Now, in the embodiment shown in FIG. 6, rewriting to the data line is performed by using the result to rewrite information to the data line every time the signal read to the data line is detected by the differential signal detection means. This was explained by writing.

However, as the pitch of the data lines becomes smaller, it is necessary to pay attention to noise caused by coupling capacitance between the data lines. For example, in FIG. 6, it is assumed that a signal on the data line dα is detected and rewrite information is written to the data line dα. At that time, if there is a signal on the data line dβ that has not been amplified yet, when rewriting information is written on the data line dα, the data line d
The coupling capacitance between α and 66 induces large noise on the data line dβ, and as a result, when the signal on the data line dβ is detected by the differential signal detection means, it may be detected incorrectly.

However, this problem can be solved by, for example, IE Transactions on Electron Devices,
Volume 7, 3 (March 1990), pages 737 to 74
Page 3 (IEEE, ■rans, on Electr
on Devices.

VOl, 37. on, 3 (March1990)pp
This problem can be avoided by using a memory cell in which the coupling capacitance between the data lines is reduced by shielding the data lines with another conductive layer, as described in Japanese Patent No. 737-743).

Further, by using such a memory cell in which the data lines are shielded, noise due to coupling capacitance between the data lines can be reduced even when a signal is read from the memory cell to the data line. Regarding the noise during reading, the noise can be reduced by using the above-mentioned memory cells in the embodiments described so far.

As described above, the embodiment shown in FIG. 6 has a configuration in which the dummy data line is shared by a plurality of data lines.
Therefore, the memory cells can be arranged in a single-crossing arrangement, and in the read operation, the same word line intersects the data line and the dummy data line, similar to the data line folded configuration, resulting in high density and high S/S/ It becomes possible to convert into N. Furthermore, multiple data lines are used to connect the voltage-current conversion circuit SW2) signal transmission means SWW, current-voltage conversion circuit LD, differential signal detection means S-
Since A is shared, the layout pitch of these circuits can be relaxed, and consistency with a high-density memory cell layout can be easily achieved.

In FIG. 6, a precharge circuit PD is provided in common for a plurality of data lines, and each data line is thereby precharged via a switch means SW, but a precharge circuit may be provided for each data line.

In this case, since there is no need to use the switch means SW, control of the signals GC1α to GC1δ becomes simple.

Although the present invention has been described above with reference to several embodiments, the present invention is not limited to the embodiments described herein unless it deviates from the spirit of the invention. For example, although FIG. 6 shows a circuit constituted by a CMO 8 as a specific example of the differential signal detection means SA, this may have a different circuit configuration. The gist of the present invention is to commonly use a reference signal from a dummy data line provided commonly to a plurality of data lines to detect signals read out to a plurality of data lines.

That is, the reference signal input to the differential signal detection means is used in common by the plurality of differential signal detection means.

Therefore, the differential signal detecting means may be any differential signal detecting means such that at least the reference signal input to the differential signal detecting means SA does not change when the individual differential signal detecting means detects the signal. Also.

Although FIG. 6 shows a circuit made up of CMO8, it may also be a bipolar circuit or a bipolar and 0MO3 circuit. Generally, the circuit composed of these is CMO8
Although it tends to occupy a larger area than a circuit constructed solely of the above, it makes use of the bipolar characteristics to enable highly sensitive differential signal detection.

〔Effect of the invention〕

According to the present invention, the density of memory cells can be increased, and a read operation with a high S/H can be performed.

Therefore, a highly integrated semiconductor memory with a high S/N ratio can be realized.

[Brief explanation of drawings]

FIG. 1 is a memory array configuration diagram of a semiconductor memory according to the present invention, FIG. 2 is an operation timing diagram for explaining the operation of FIG. 1, and FIGS. 3 to 6 show other embodiments according to the present invention. 7 are operation timing charts for explaining the operation of FIG. 6. MC! MCx, tMCmn...Memory cell, DC. DC□, DC,... dummy cell, Wl, W,... word line, dl, dn... data line, dd... dummy data line, T R□, T Rn, T Rd-signal conversion means, SW2□. SW2□, 5W2d...voltage-current conversion means, LDl. L Dn, L Dd”/current voltage conversion means, SWW,
. sww, sww, t=·=signal transmission means, SA1. S
A. S A a... Differential signal detection means, CdlHCdn.
...Common data line, cdd...Common dummy data line. -m-・ku agent patent attorney Katsuo Ogawa V... Figure 1 Figure 2 dd V. Fig. 3 Fig. 4 Fig. 5 RG+ G Fig. 7 m3 ding-]”mT

Claims (1)

[Claims] 1) A plurality of word lines, a plurality of data lines arranged to intersect with these, and one transistor provided at any intersection of the plurality of word lines and the plurality of data lines. a memory cell consisting of only one capacitor; a dummy data line provided in common to the plurality of data lines;
A plurality of dummy cells for generating reference signals provided at arbitrary intersections of the plurality of word lines and the dummy data lines, and a signal conversion means electrically connected to the plurality of data lines and the dummy data line, respectively. and differential signal detection means provided on each of the plurality of data lines,
The output of the signal conversion means provided on each of the data lines and the output of the signal conversion means provided on the dummy data line are input to the differential signal detection means provided on each of the data lines. semiconductor memory. 2) The semiconductor memory according to claim 1, wherein the dummy data line is arranged between the data lines. 3) In the semiconductor memory according to any one of claims 1 to 2, the signal conversion means and the differential signal detection means are arranged alternately at both ends of any adjacent data lines. A semiconductor memory characterized by: 4) A semiconductor memory according to claim 3, wherein the signal conversion means provided on the dummy data line are arranged at both ends of the dummy data line. 5) A semiconductor memory according to any one of claims 1 to 4, wherein the signal conversion means includes a voltage-current conversion circuit and a current-voltage conversion circuit. 6) From only a plurality of word lines, a plurality of data lines arranged to intersect with these, one transistor and one capacitor provided at any intersection of the plurality of word lines and the plurality of data lines. a dummy data line provided in common to the plurality of data lines,
A block including a dummy cell for generating a reference signal provided at an arbitrary intersection of the plurality of word lines and the dummy data line, and a voltage-current conversion circuit connected to each of the plurality of data lines and the dummy data line. , which has a plurality of the above blocks, and further has a plurality of common data lines and common dummy data lines for connecting the respective corresponding voltage-current conversion circuits, and is connected to the plurality of common data lines and common dummy data lines, respectively. It has a current-voltage conversion circuit and a differential signal detection means provided on each of the plurality of common data lines, and the differential signal detection means provided on each of the common data lines has a current-voltage conversion circuit and a differential signal detection means provided on each of the plurality of common data lines. A semiconductor memory characterized in that an output of a current-voltage conversion circuit provided and an output of a current-voltage conversion circuit provided on the common dummy data line are input. 7) In the semiconductor memory according to claim 6, the voltage-current conversion circuit is provided in common to the plurality of data lines or the plurality of dummy data lines, and the voltage-current conversion circuit and the plurality of data lines or the plurality of dummy data lines are connected to each other. A semiconductor memory comprising switch means for connecting to each of the dummy data lines. 8) A semiconductor memory according to any one of claims 6 to 7, wherein the common dummy data line is arranged between the common data lines. 9) In the semiconductor memory according to any one of claims 6 to 8, the current-voltage conversion circuit and the differential signal detection means are arranged alternately at both ends of any adjacent common data line. A semiconductor memory characterized by being arranged. 10) The semiconductor memory according to claim 9, wherein the current-voltage conversion circuit provided on the common dummy data line is arranged at both ends of the common dummy data line. 11) In the semiconductor memory according to any one of claims 1 to 10, an electrode in contact with one impurity doped region of the transistor of the memory cell extends above the transistor and the data line, and A semiconductor memory characterized in that an electrode in contact with an impurity-doped region forms a capacitor of a memory cell together with an insulating film provided thereon and a conductive electrode further provided thereon.