JPH04153779A - Gate array designing cad device - Google Patents

Abstract

PURPOSE:To design a gate array at the stage for production of a circuit diagram in consideration of the element except a logical element by providing a circuit diagram input device, a logical simulation device, and an arranging/ wiring device which has an algorithm that can arrange and wire the prescribed elements. CONSTITUTION:A buffer 1 is provided together with a buffer 2, an input pin 3, an input pin 4, and a contact hole 6 for delay. In other words, the data on a delay element like the hole 6, etc., except a logical element are provided to the libraries of a circuit diagram input device and a logical simulation device respectively. Thus the data on the delay element are obtained together with an algorithm obtained for an arranging/wiring device to automatically detect such a place that has a spatial margin and to arrange and wire the elements except the logical element. As a result, the elements except the logical element can be treated like the normal logical elements at a designing stage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CAD device for designing gate arrays.

[Conventional technology]

In general, in a CAD device for gate array design, a circuit diagram is read in by a circuit diagram input device and simulated by a logic simulation device.Only the logic elements and their connection relationships are described in the circuit diagram. The simulation is performed based on the operation of . After the simulation is completed, a placement/routing device determines the positions of logic elements according to the circuit design results, and determines wiring routes between these elements. I am trying to create mask data from the second result.

FIG. 5 is a flowchart showing the work flow of the C'AD device for gate array design. First, a circuit diagram 1 is input into a CAD system for gate array design using a circuit diagram input device 2. The circuit diagram 1 shows the connection relationships between logic elements. Next, the logic simulation device 4 simulates the input circuit using the prepared test pattern 3. Modify the circuit diagram and repeat the above flow until you get the desired result.

After the logic simulation is completed, the placement/routing device 6 determines the positions of logic elements according to the circuit design results, and determines the wiring routes between these elements. If the expected placement/routing results are not obtained, change the placement/routing. Correct the environment variables and perform placement and routing again. If a good result is still not obtained, the circuit diagram 1 must be modified. 1. If the expected placement and wiring results are obtained, mask data 8 is created based on it.

FIG. 3 is a circuit diagram used in a conventional CAD device for designing gate arrays. In the figure, (1) is buffer 1 (
2) is buffer 2, (3) is input bin 3, and (4) is input bin 4. In this circuit diagram, it is assumed that the signal transmitted from buffer 2 to input bin 4 is transmitted too quickly compared to the signal transmitted from buffer 1 to input bin 3. Conventional circuit diagrams can only describe logic elements and their connections. Therefore, a common method to delay the propagation of the signal from buffer 2 to input bin 4 is to insert a delay inverter 5 between buffer 2 and input bin 4, as shown in FIG. It is.

However, in this method, an inverter, which is a logic element, is used just to provide a delay, and the corresponding transistor and wiring area are used.

Conventionally, in gate arrays, when adding a delay to prevent signals from propagating too quickly, multiple inverters were inserted in series. On the other hand, to add a delay,
There is also a method of placing a contact hole with a large capacity on the wiring, or creating a long wiring so that the capacity becomes large. Conventional logic simulation systems only deal with logic elements, so they cannot take into account contact holes or delays caused by particularly long wiring.

[Problem to be solved by the invention]

Since the conventional CAD device for designing gate arrays is configured as described above, logic simulation and placement/wiring are performed based only on logic elements and their connection relationships. Therefore, circuit diagrams should be created, logic simulations, and layouts performed, taking into consideration elements other than logic elements, such as contact holes for providing delay and long wiring.
It is not possible to perform wiring, and therefore, there is a problem in that several dozen stages of inverters are used simply to provide a delay, which wastes transistors and wiring area.

This invention was made in order to solve the above-mentioned problems, and the object is to obtain a CAD device for gate array design that can be designed taking elements other than logic elements into consideration from the stage of creating a circuit diagram. .

[Means to solve the problem]

The CAD device for gate array design according to the present invention has data on elements other than logic elements, such as delay elements such as contact holes, in the respective libraries of the circuit diagram input device and the logic simulation device.

In addition, the placement and wiring equipment of this CAD system for gate array design searches for a space with sufficient space after the conventional placement and wiring is completed, and removes elements other than logic elements specified in the circuit diagram, such as contact holes, etc. It has an algorithm for arranging and wiring elements.

[Effect]

The CAD device for gate array design according to the present invention has data for delay elements other than normal logic elements in the respective libraries of the circuit diagram input device and the logic simulation device, and the placement and wiring device automatically By having an algorithm that detects areas with sufficient space and places and wires elements other than logic elements, it is possible to treat elements other than logic elements in the same way as normal logic elements from the design stage. can.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 is an example of a circuit diagram that can be handled by this CAD device for gate array design.
2) is the buffer 2, (3) is the input bin 3, (4) is the input bin 4, and (6) is the delay contact hole. Here, a logical symbol diagram of the contact hole 6 used to provide a delay is defined as shown in FIG.

Next, the operation will be explained.

If a delay pot is provided using a contact hole as shown in FIG. 1, unlike the case where an inverter is used as shown in FIG. 4, transistors and wiring area are not wasted. By supplying data on elements other than logic elements to the libraries of the circuit diagram input device and logic simulation device, the placement and wiring device can detect locations with sufficient space on the chip and perform logic By providing an algorithm for arranging and wiring elements other than logic elements, elements other than logic elements can be handled in the same way as normal logic elements from the design stage.

〔Effect of the invention〕

As described above, according to the present invention, since delay elements other than logic elements can be handled from the stage of creating a circuit diagram, there is no need to use an inverter to add a delay. Due to this,
The number of gates used can be reduced, and contact holes can be placed relatively freely on the chip, so there are effects such as the ability to reduce placement and wiring time.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram that can be handled by this CAD device for designing gate arrays, Fig. 2 is a logical symbol diagram defining contact holes, and Fig. 3 is a circuit diagram used in a conventional CAD device for designing gate arrays. , FIG. 4 is a circuit diagram in which the timing of signal propagation is adjusted using an inverter in the circuit diagram of FIG. 3, and FIG. 5 is a flowchart showing the work flow of a conventional CAD system for designing gate arrays. In the figure, (1) is buffer 1, (2) is buffer 2
, (3) is the input pin 3, (4) is the input pin 4, and (6) is the contact hole for delay. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A circuit diagram input device that can define predetermined elements other than logic elements specified in a circuit diagram, a logic simulation device that can simulate the predetermined elements as logic simulation primitives, and an algorithm that can place and route the predetermined elements. A CAD device for gate array design, comprising a placement and wiring device having the following.